1 //===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Sparc implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SparcInstrInfo.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h"
29 #define GET_INSTRINFO_CTOR_DTOR
30 #include "SparcGenInstrInfo.inc"
32 // Pin the vtable to this file.
33 void SparcInstrInfo::anchor() {}
35 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
36 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(),
39 /// isLoadFromStackSlot - If the specified machine instruction is a direct
40 /// load from a stack slot, return the virtual or physical register number of
41 /// the destination along with the FrameIndex of the loaded stack slot. If
42 /// not, return 0. This predicate must return 0 if the instruction has
43 /// any side effects other than loading from the stack slot.
44 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
45 int &FrameIndex) const {
46 if (MI->getOpcode() == SP::LDri ||
47 MI->getOpcode() == SP::LDXri ||
48 MI->getOpcode() == SP::LDFri ||
49 MI->getOpcode() == SP::LDDFri ||
50 MI->getOpcode() == SP::LDQFri) {
51 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
52 MI->getOperand(2).getImm() == 0) {
53 FrameIndex = MI->getOperand(1).getIndex();
54 return MI->getOperand(0).getReg();
60 /// isStoreToStackSlot - If the specified machine instruction is a direct
61 /// store to a stack slot, return the virtual or physical register number of
62 /// the source reg along with the FrameIndex of the loaded stack slot. If
63 /// not, return 0. This predicate must return 0 if the instruction has
64 /// any side effects other than storing to the stack slot.
65 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
66 int &FrameIndex) const {
67 if (MI->getOpcode() == SP::STri ||
68 MI->getOpcode() == SP::STXri ||
69 MI->getOpcode() == SP::STFri ||
70 MI->getOpcode() == SP::STDFri ||
71 MI->getOpcode() == SP::STQFri) {
72 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
73 MI->getOperand(1).getImm() == 0) {
74 FrameIndex = MI->getOperand(0).getIndex();
75 return MI->getOperand(2).getReg();
81 static bool IsIntegerCC(unsigned CC)
83 return (CC <= SPCC::ICC_VC);
86 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
89 case SPCC::ICC_A: return SPCC::ICC_N;
90 case SPCC::ICC_N: return SPCC::ICC_A;
91 case SPCC::ICC_NE: return SPCC::ICC_E;
92 case SPCC::ICC_E: return SPCC::ICC_NE;
93 case SPCC::ICC_G: return SPCC::ICC_LE;
94 case SPCC::ICC_LE: return SPCC::ICC_G;
95 case SPCC::ICC_GE: return SPCC::ICC_L;
96 case SPCC::ICC_L: return SPCC::ICC_GE;
97 case SPCC::ICC_GU: return SPCC::ICC_LEU;
98 case SPCC::ICC_LEU: return SPCC::ICC_GU;
99 case SPCC::ICC_CC: return SPCC::ICC_CS;
100 case SPCC::ICC_CS: return SPCC::ICC_CC;
101 case SPCC::ICC_POS: return SPCC::ICC_NEG;
102 case SPCC::ICC_NEG: return SPCC::ICC_POS;
103 case SPCC::ICC_VC: return SPCC::ICC_VS;
104 case SPCC::ICC_VS: return SPCC::ICC_VC;
106 case SPCC::FCC_A: return SPCC::FCC_N;
107 case SPCC::FCC_N: return SPCC::FCC_A;
108 case SPCC::FCC_U: return SPCC::FCC_O;
109 case SPCC::FCC_O: return SPCC::FCC_U;
110 case SPCC::FCC_G: return SPCC::FCC_ULE;
111 case SPCC::FCC_LE: return SPCC::FCC_UG;
112 case SPCC::FCC_UG: return SPCC::FCC_LE;
113 case SPCC::FCC_ULE: return SPCC::FCC_G;
114 case SPCC::FCC_L: return SPCC::FCC_UGE;
115 case SPCC::FCC_GE: return SPCC::FCC_UL;
116 case SPCC::FCC_UL: return SPCC::FCC_GE;
117 case SPCC::FCC_UGE: return SPCC::FCC_L;
118 case SPCC::FCC_LG: return SPCC::FCC_UE;
119 case SPCC::FCC_UE: return SPCC::FCC_LG;
120 case SPCC::FCC_NE: return SPCC::FCC_E;
121 case SPCC::FCC_E: return SPCC::FCC_NE;
123 llvm_unreachable("Invalid cond code");
126 static bool isUncondBranchOpcode(int Opc) { return Opc == SP::BA; }
128 static bool isCondBranchOpcode(int Opc) {
129 return Opc == SP::FBCOND || Opc == SP::BCOND;
132 static bool isIndirectBranchOpcode(int Opc) {
133 return Opc == SP::BINDrr || Opc == SP::BINDri;
136 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
137 SmallVectorImpl<MachineOperand> &Cond) {
138 Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(1).getImm()));
139 Target = LastInst->getOperand(0).getMBB();
142 bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
143 MachineBasicBlock *&TBB,
144 MachineBasicBlock *&FBB,
145 SmallVectorImpl<MachineOperand> &Cond,
146 bool AllowModify) const {
147 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
151 if (!isUnpredicatedTerminator(I))
154 // Get the last instruction in the block.
155 MachineInstr *LastInst = I;
156 unsigned LastOpc = LastInst->getOpcode();
158 // If there is only one terminator instruction, process it.
159 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
160 if (isUncondBranchOpcode(LastOpc)) {
161 TBB = LastInst->getOperand(0).getMBB();
164 if (isCondBranchOpcode(LastOpc)) {
165 // Block ends with fall-through condbranch.
166 parseCondBranch(LastInst, TBB, Cond);
169 return true; // Can't handle indirect branch.
172 // Get the instruction before it if it is a terminator.
173 MachineInstr *SecondLastInst = I;
174 unsigned SecondLastOpc = SecondLastInst->getOpcode();
176 // If AllowModify is true and the block ends with two or more unconditional
177 // branches, delete all but the first unconditional branch.
178 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
179 while (isUncondBranchOpcode(SecondLastOpc)) {
180 LastInst->eraseFromParent();
181 LastInst = SecondLastInst;
182 LastOpc = LastInst->getOpcode();
183 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
184 // Return now the only terminator is an unconditional branch.
185 TBB = LastInst->getOperand(0).getMBB();
189 SecondLastOpc = SecondLastInst->getOpcode();
194 // If there are three terminators, we don't know what sort of block this is.
195 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
198 // If the block ends with a B and a Bcc, handle it.
199 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
200 parseCondBranch(SecondLastInst, TBB, Cond);
201 FBB = LastInst->getOperand(0).getMBB();
205 // If the block ends with two unconditional branches, handle it. The second
206 // one is not executed.
207 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
208 TBB = SecondLastInst->getOperand(0).getMBB();
212 // ...likewise if it ends with an indirect branch followed by an unconditional
214 if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
217 I->eraseFromParent();
221 // Otherwise, can't handle this.
226 SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
227 MachineBasicBlock *FBB,
228 ArrayRef<MachineOperand> Cond,
230 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
231 assert((Cond.size() == 1 || Cond.size() == 0) &&
232 "Sparc branch conditions should have one component!");
235 assert(!FBB && "Unconditional branch with multiple successors!");
236 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
240 // Conditional branch
241 unsigned CC = Cond[0].getImm();
244 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
246 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
250 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
254 unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
256 MachineBasicBlock::iterator I = MBB.end();
258 while (I != MBB.begin()) {
261 if (I->isDebugValue())
264 if (I->getOpcode() != SP::BA
265 && I->getOpcode() != SP::BCOND
266 && I->getOpcode() != SP::FBCOND)
267 break; // Not a branch
269 I->eraseFromParent();
276 bool SparcInstrInfo::ReverseBranchCondition(
277 SmallVectorImpl<MachineOperand> &Cond) const {
278 assert(Cond.size() == 1);
279 SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[0].getImm());
280 Cond[0].setImm(GetOppositeBranchCondition(CC));
284 void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
285 MachineBasicBlock::iterator I, DebugLoc DL,
286 unsigned DestReg, unsigned SrcReg,
287 bool KillSrc) const {
288 unsigned numSubRegs = 0;
290 const unsigned *subRegIdx = nullptr;
291 bool ExtraG0 = false;
293 const unsigned DW_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
294 const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
295 const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
296 const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd,
297 SP::sub_odd64_then_sub_even,
298 SP::sub_odd64_then_sub_odd };
300 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
301 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
302 .addReg(SrcReg, getKillRegState(KillSrc));
303 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) {
304 subRegIdx = DW_SubRegsIdx;
308 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
309 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
310 .addReg(SrcReg, getKillRegState(KillSrc));
311 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
312 if (Subtarget.isV9()) {
313 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
314 .addReg(SrcReg, getKillRegState(KillSrc));
316 // Use two FMOVS instructions.
317 subRegIdx = DFP_FP_SubRegsIdx;
321 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
322 if (Subtarget.isV9()) {
323 if (Subtarget.hasHardQuad()) {
324 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
325 .addReg(SrcReg, getKillRegState(KillSrc));
327 // Use two FMOVD instructions.
328 subRegIdx = QFP_DFP_SubRegsIdx;
333 // Use four FMOVS instructions.
334 subRegIdx = QFP_FP_SubRegsIdx;
338 } else if (SP::ASRRegsRegClass.contains(DestReg) &&
339 SP::IntRegsRegClass.contains(SrcReg)) {
340 BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg)
342 .addReg(SrcReg, getKillRegState(KillSrc));
343 } else if (SP::IntRegsRegClass.contains(DestReg) &&
344 SP::ASRRegsRegClass.contains(SrcReg)) {
345 BuildMI(MBB, I, DL, get(SP::RDASR), DestReg)
346 .addReg(SrcReg, getKillRegState(KillSrc));
348 llvm_unreachable("Impossible reg-to-reg copy");
350 if (numSubRegs == 0 || subRegIdx == nullptr || movOpc == 0)
353 const TargetRegisterInfo *TRI = &getRegisterInfo();
354 MachineInstr *MovMI = nullptr;
356 for (unsigned i = 0; i != numSubRegs; ++i) {
357 unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
358 unsigned Src = TRI->getSubReg(SrcReg, subRegIdx[i]);
359 assert(Dst && Src && "Bad sub-register");
361 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(movOpc), Dst);
365 MovMI = MIB.getInstr();
367 // Add implicit super-register defs and kills to the last MovMI.
368 MovMI->addRegisterDefined(DestReg, TRI);
370 MovMI->addRegisterKilled(SrcReg, TRI);
373 void SparcInstrInfo::
374 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
375 unsigned SrcReg, bool isKill, int FI,
376 const TargetRegisterClass *RC,
377 const TargetRegisterInfo *TRI) const {
379 if (I != MBB.end()) DL = I->getDebugLoc();
381 MachineFunction *MF = MBB.getParent();
382 const MachineFrameInfo &MFI = *MF->getFrameInfo();
383 MachineMemOperand *MMO = MF->getMachineMemOperand(
384 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
385 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
387 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
388 if (RC == &SP::I64RegsRegClass)
389 BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
390 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
391 else if (RC == &SP::IntRegsRegClass)
392 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
393 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
394 else if (RC == &SP::IntPairRegClass)
395 BuildMI(MBB, I, DL, get(SP::STDri)).addFrameIndex(FI).addImm(0)
396 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
397 else if (RC == &SP::FPRegsRegClass)
398 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
399 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
400 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
401 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
402 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
403 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
404 // Use STQFri irrespective of its legality. If STQ is not legal, it will be
405 // lowered into two STDs in eliminateFrameIndex.
406 BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
407 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
409 llvm_unreachable("Can't store this register to stack slot");
412 void SparcInstrInfo::
413 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
414 unsigned DestReg, int FI,
415 const TargetRegisterClass *RC,
416 const TargetRegisterInfo *TRI) const {
418 if (I != MBB.end()) DL = I->getDebugLoc();
420 MachineFunction *MF = MBB.getParent();
421 const MachineFrameInfo &MFI = *MF->getFrameInfo();
422 MachineMemOperand *MMO = MF->getMachineMemOperand(
423 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
424 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
426 if (RC == &SP::I64RegsRegClass)
427 BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)
429 else if (RC == &SP::IntRegsRegClass)
430 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)
432 else if (RC == &SP::IntPairRegClass)
433 BuildMI(MBB, I, DL, get(SP::LDDri), DestReg).addFrameIndex(FI).addImm(0)
435 else if (RC == &SP::FPRegsRegClass)
436 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
438 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
439 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
441 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
442 // Use LDQFri irrespective of its legality. If LDQ is not legal, it will be
443 // lowered into two LDDs in eliminateFrameIndex.
444 BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
447 llvm_unreachable("Can't load this register from stack slot");
450 unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
452 SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
453 unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
454 if (GlobalBaseReg != 0)
455 return GlobalBaseReg;
457 // Insert the set of GlobalBaseReg into the first MBB of the function
458 MachineBasicBlock &FirstMBB = MF->front();
459 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
460 MachineRegisterInfo &RegInfo = MF->getRegInfo();
462 const TargetRegisterClass *PtrRC =
463 Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
464 GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
468 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
469 SparcFI->setGlobalBaseReg(GlobalBaseReg);
470 return GlobalBaseReg;