1 //===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
17 let Inst{31-30} = op; // Top two bits are the 'op' field
19 dag OutOperandList = outs;
20 dag InOperandList = ins;
21 let AsmString = asmstr;
22 let Pattern = pattern;
25 //===----------------------------------------------------------------------===//
26 // Format #2 instruction classes in the Sparc
27 //===----------------------------------------------------------------------===//
29 // Format 2 instructions
30 class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
31 : InstSP<outs, ins, asmstr, pattern> {
35 let Inst{24-22} = op2;
36 let Inst{21-0} = imm22;
39 // Specific F2 classes: SparcV8 manual, page 44
41 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
42 : F2<outs, ins, asmstr, pattern> {
50 class F2_2<bits<3> op2Val, dag outs, dag ins, string asmstr,
51 list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
53 bit annul = 0; // currently unused
58 let Inst{28-25} = cond;
61 //===----------------------------------------------------------------------===//
62 // Format #3 instruction classes in the Sparc
63 //===----------------------------------------------------------------------===//
65 class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
66 : InstSP<outs, ins, asmstr, pattern> {
70 let op{1} = 1; // Op = 2 or 3
72 let Inst{24-19} = op3;
73 let Inst{18-14} = rs1;
76 // Specific F3 classes: SparcV8 manual, page 44
78 class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
79 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
80 bits<8> asi = 0; // asi not currently used
86 let Inst{13} = 0; // i field = 0
87 let Inst{12-5} = asi; // address space identifier
91 class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
92 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
98 let Inst{13} = 1; // i field = 1
99 let Inst{12-0} = simm13;
103 class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
104 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
110 let Inst{13-5} = opfval; // fp opcode
114 // floating-point unary operations.
115 class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
116 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
123 let Inst{13-5} = opfval; // fp opcode
127 // floating-point compares.
128 class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
129 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
136 let Inst{13-5} = opfval; // fp opcode
140 // Shift by register rs2.
141 class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
142 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
143 bit x = xVal; // 1 for 64-bit shifts.
149 let Inst{13} = 0; // i field = 0
150 let Inst{12} = x; // extended registers.
154 // Shift by immediate.
155 class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
156 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
157 bit x = xVal; // 1 for 64-bit shifts.
158 bits<6> shcnt; // shcnt32 / shcnt64.
163 let Inst{13} = 1; // i field = 1
164 let Inst{12} = x; // extended registers.
165 let Inst{5-0} = shcnt;
168 // Define rr and ri shift instructions with patterns.
169 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
170 ValueType VT, RegisterClass RC> {
171 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, IntRegs:$rs2),
172 !strconcat(OpcStr, " $rs, $rs2, $rd"),
173 [(set VT:$rd, (OpNode VT:$rs, i32:$rs2))]>;
174 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, i32imm:$shcnt),
175 !strconcat(OpcStr, " $rs, $shcnt, $rd"),
176 [(set VT:$rd, (OpNode VT:$rs, (i32 imm:$shcnt)))]>;
179 class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern>
180 : InstSP<outs, ins, asmstr, pattern> {
184 let Inst{29-25} = rd;
185 let Inst{24-19} = op3;
189 class F4_1<bits<6> op3, dag outs, dag ins,
190 string asmstr, list<dag> pattern>
191 : F4<op3, outs, ins, asmstr, pattern> {
198 let Inst{11} = cc{0};
199 let Inst{12} = cc{1};
201 let Inst{17-14} = cond;
202 let Inst{18} = cc{2};
206 class F4_2<bits<6> op3, dag outs, dag ins,
207 string asmstr, list<dag> pattern>
208 : F4<op3, outs, ins, asmstr, pattern> {
213 let Inst{10-0} = simm11;
214 let Inst{11} = cc{0};
215 let Inst{12} = cc{1};
217 let Inst{17-14} = cond;
218 let Inst{18} = cc{2};
221 class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,
222 string asmstr, list<dag> pattern>
223 : F4<op3, outs, ins, asmstr, pattern> {
229 let Inst{17-14} = cond;
230 let Inst{13-11} = opf_cc;
231 let Inst{10-5} = opf_low;