1 //===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction aliases for Sparc.
11 //===----------------------------------------------------------------------===//
13 // Instruction aliases for conditional moves.
15 // mov<cond> <ccreg> rs2, rd
16 multiclass intcond_mov_alias<string cond, int condVal, string ccreg,
17 Instruction movrr, Instruction movri,
18 Instruction fmovs, Instruction fmovd> {
20 // mov<cond> (%icc|%xcc), rs2, rd
21 def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
23 (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
25 // mov<cond> (%icc|%xcc), simm11, rd
26 def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
28 (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
30 // fmovs<cond> (%icc|%xcc), $rs2, $rd
31 def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg),
33 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
35 // fmovd<cond> (%icc|%xcc), $rs2, $rd
36 def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg),
38 (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
41 // mov<cond> <ccreg> rs2, rd
42 multiclass fpcond_mov_alias<string cond, int condVal,
43 Instruction movrr, Instruction movri,
44 Instruction fmovs, Instruction fmovd> {
46 // mov<cond> %fcc[0-3], rs2, rd
47 def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $rs2, $rd"),
48 (movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;
50 // mov<cond> %fcc[0-3], simm11, rd
51 def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $simm11, $rd"),
52 (movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>;
54 // fmovs<cond> %fcc[0-3], $rs2, $rd
55 def : InstAlias<!strconcat(!strconcat("fmovs", cond), " $cc, $rs2, $rd"),
56 (fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;
58 // fmovd<cond> %fcc[0-3], $rs2, $rd
59 def : InstAlias<!strconcat(!strconcat("fmovd", cond), " $cc, $rs2, $rd"),
60 (fmovd DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, condVal)>;
63 // Instruction aliases for integer conditional branches and moves.
64 multiclass int_cond_alias<string cond, int condVal> {
67 def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
68 (BCOND brtarget:$imm, condVal)>;
71 def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
72 (BCONDA brtarget:$imm, condVal)>;
75 def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
76 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
78 // b<cond>,pt %icc, $imm
79 def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %icc, $imm"),
80 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
82 // b<cond>,a %icc, $imm
83 def : InstAlias<!strconcat(!strconcat("b", cond), ",a %icc, $imm"),
84 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
86 // b<cond>,a,pt %icc, $imm
87 def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %icc, $imm"),
88 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
90 // b<cond>,pn %icc, $imm
91 def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %icc, $imm"),
92 (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
94 // b<cond>,a,pn %icc, $imm
95 def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %icc, $imm"),
96 (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
99 def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"),
100 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
102 // b<cond>,pt %xcc, $imm
103 def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %xcc, $imm"),
104 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
106 // b<cond>,a %xcc, $imm
107 def : InstAlias<!strconcat(!strconcat("b", cond), ",a %xcc, $imm"),
108 (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
110 // b<cond>,a,pt %xcc, $imm
111 def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %xcc, $imm"),
112 (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
114 // b<cond>,pn %xcc, $imm
115 def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %xcc, $imm"),
116 (BPXCCNT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
118 // b<cond>,a,pn %xcc, $imm
119 def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %xcc, $imm"),
120 (BPXCCANT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
123 defm : intcond_mov_alias<cond, condVal, " %icc",
125 FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>;
127 defm : intcond_mov_alias<cond, condVal, " %xcc",
129 FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>;
131 // fmovq<cond> (%icc|%xcc), $rs2, $rd
132 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"),
133 (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
134 Requires<[HasV9, HasHardQuad]>;
135 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"),
136 (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
137 Requires<[Is64Bit, HasHardQuad]>;
139 // t<cond> %icc, rs1 + rs2
140 def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $rs2"),
141 (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
144 // t<cond> %icc, rs => t<cond> %icc, G0 + rs
145 def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs2"),
146 (TICCrr G0, IntRegs:$rs2, condVal)>,
149 // t<cond> %xcc, rs1 + rs2
150 def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $rs2"),
151 (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
154 // t<cond> %xcc, rs => t<cond> %xcc, G0 + rs
155 def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs2"),
156 (TXCCrr G0, IntRegs:$rs2, condVal)>,
159 // t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2
160 def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),
161 (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>;
163 // t<cond> rs=> t<cond> %icc, G0 + rs2
164 def : InstAlias<!strconcat(!strconcat("t", cond), " $rs2"),
165 (TICCrr G0, IntRegs:$rs2, condVal)>;
167 // t<cond> %icc, rs1 + imm
168 def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $imm"),
169 (TICCri IntRegs:$rs1, i32imm:$imm, condVal)>,
171 // t<cond> %icc, imm => t<cond> %icc, G0 + imm
172 def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $imm"),
173 (TICCri G0, i32imm:$imm, condVal)>,
175 // t<cond> %xcc, rs1 + imm
176 def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $imm"),
177 (TXCCri IntRegs:$rs1, i32imm:$imm, condVal)>,
179 // t<cond> %xcc, imm => t<cond> %xcc, G0 + imm
180 def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $imm"),
181 (TXCCri G0, i32imm:$imm, condVal)>,
184 // t<cond> rs1 + imm => t<cond> %icc, rs1 + imm
185 def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $imm"),
186 (TICCri IntRegs:$rs1, i32imm:$imm, condVal)>;
188 // t<cond> imm => t<cond> %icc, G0 + imm
189 def : InstAlias<!strconcat(!strconcat("t", cond), " $imm"),
190 (TICCri G0, i32imm:$imm, condVal)>;
195 // Instruction aliases for floating point conditional branches and moves.
196 multiclass fp_cond_alias<string cond, int condVal> {
199 def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"),
200 (FBCOND brtarget:$imm, condVal), 0>;
203 def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $imm"),
204 (FBCONDA brtarget:$imm, condVal), 0>;
206 // fb<cond> %fcc0, $imm
207 def : InstAlias<!strconcat(!strconcat("fb", cond), " $cc, $imm"),
208 (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
211 // fb<cond>,pt %fcc0, $imm
212 def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt $cc, $imm"),
213 (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
216 // fb<cond>,a %fcc0, $imm
217 def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $cc, $imm"),
218 (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
221 // fb<cond>,a,pt %fcc0, $imm
222 def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt $cc, $imm"),
223 (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
226 // fb<cond>,pn %fcc0, $imm
227 def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn $cc, $imm"),
228 (BPFCCNT brtarget:$imm, condVal, FCCRegs:$cc)>,
231 // fb<cond>,a,pn %fcc0, $imm
232 def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn $cc, $imm"),
233 (BPFCCANT brtarget:$imm, condVal, FCCRegs:$cc)>,
236 defm : fpcond_mov_alias<cond, condVal,
237 V9MOVFCCrr, V9MOVFCCri,
238 V9FMOVS_FCC, V9FMOVD_FCC>, Requires<[HasV9]>;
240 // fmovq<cond> %fcc0, $rs2, $rd
241 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " $cc, $rs2, $rd"),
242 (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2,
244 Requires<[HasV9, HasHardQuad]>;
247 defm : int_cond_alias<"a", 0b1000>;
248 defm : int_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual
249 defm : int_cond_alias<"n", 0b0000>;
250 defm : int_cond_alias<"ne", 0b1001>;
251 defm : int_cond_alias<"nz", 0b1001>; // same as ne
252 defm : int_cond_alias<"e", 0b0001>;
253 defm : int_cond_alias<"eq", 0b0001>; // same as e
254 defm : int_cond_alias<"z", 0b0001>; // same as e
255 defm : int_cond_alias<"g", 0b1010>;
256 defm : int_cond_alias<"le", 0b0010>;
257 defm : int_cond_alias<"ge", 0b1011>;
258 defm : int_cond_alias<"l", 0b0011>;
259 defm : int_cond_alias<"gu", 0b1100>;
260 defm : int_cond_alias<"leu", 0b0100>;
261 defm : int_cond_alias<"cc", 0b1101>;
262 defm : int_cond_alias<"geu", 0b1101>; // same as cc
263 defm : int_cond_alias<"cs", 0b0101>;
264 defm : int_cond_alias<"lu", 0b0101>; // same as cs
265 defm : int_cond_alias<"pos", 0b1110>;
266 defm : int_cond_alias<"neg", 0b0110>;
267 defm : int_cond_alias<"vc", 0b1111>;
268 defm : int_cond_alias<"vs", 0b0111>;
270 defm : fp_cond_alias<"a", 0b0000>;
271 defm : fp_cond_alias<"", 0b0000>; // same as a; gnu asm, not in manual
272 defm : fp_cond_alias<"n", 0b1000>;
273 defm : fp_cond_alias<"u", 0b0111>;
274 defm : fp_cond_alias<"g", 0b0110>;
275 defm : fp_cond_alias<"ug", 0b0101>;
276 defm : fp_cond_alias<"l", 0b0100>;
277 defm : fp_cond_alias<"ul", 0b0011>;
278 defm : fp_cond_alias<"lg", 0b0010>;
279 defm : fp_cond_alias<"ne", 0b0001>;
280 defm : fp_cond_alias<"nz", 0b0001>; // same as ne
281 defm : fp_cond_alias<"e", 0b1001>;
282 defm : fp_cond_alias<"z", 0b1001>; // same as e
283 defm : fp_cond_alias<"ue", 0b1010>;
284 defm : fp_cond_alias<"ge", 0b1011>;
285 defm : fp_cond_alias<"uge", 0b1100>;
286 defm : fp_cond_alias<"le", 0b1101>;
287 defm : fp_cond_alias<"ule", 0b1110>;
288 defm : fp_cond_alias<"o", 0b1111>;
290 // Section A.3 Synthetic Instructions
292 // Most are marked as Emit=0, so that they are not used for disassembly. This is
293 // an aesthetic issue, but the chosen policy is to typically prefer using the
294 // non-alias form, except for the most obvious and clarifying aliases: cmp, jmp,
295 // call, tst, ret, retl.
297 // Note: cmp is handled in SparcInstrInfo.
298 // jmp/call/ret/retl have special case handling for output in
299 // SparcInstPrinter.cpp
301 // jmp addr -> jmpl addr, %g0
302 def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr), 0>;
303 def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr), 0>;
305 // call addr -> jmpl addr, %o7
306 def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr), 0>;
307 def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr), 0>;
309 // tst reg -> orcc %g0, reg, %g0
310 def : InstAlias<"tst $rs2", (ORCCrr G0, IntRegs:$rs2, G0)>;
312 // ret -> jmpl %i7+8, %g0 (aka RET 8)
313 def : InstAlias<"ret", (RET 8)>;
315 // retl -> jmpl %o7+8, %g0 (aka RETL 8)
316 def : InstAlias<"retl", (RETL 8)>;
318 // restore -> restore %g0, %g0, %g0
319 def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
321 // save -> restore %g0, %g0, %g0
322 def : InstAlias<"save", (SAVErr G0, G0, G0)>;
325 // (turns into a sequence of sethi+or, depending on the value)
326 // def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
327 def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">;
329 // not rd -> xnor rd, %g0, rd
330 def : InstAlias<"not $rd", (XNORrr IntRegs:$rd, IntRegs:$rd, G0), 0>;
332 // not reg, rd -> xnor reg, %g0, rd
333 def : InstAlias<"not $rs1, $rd", (XNORrr IntRegs:$rd, IntRegs:$rs1, G0), 0>;
335 // neg rd -> sub %g0, rd, rd
336 def : InstAlias<"neg $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rd), 0>;
338 // neg reg, rd -> sub %g0, reg, rd
339 def : InstAlias<"neg $rs2, $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rs2), 0>;
341 // inc rd -> add rd, 1, rd
342 def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;
344 // inc simm13, rd -> add rd, simm13, rd
345 def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
347 // inccc rd -> addcc rd, 1, rd
348 def : InstAlias<"inccc $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
350 // inccc simm13, rd -> addcc rd, simm13, rd
351 def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
353 // dec rd -> sub rd, 1, rd
354 def : InstAlias<"dec $rd", (SUBri IntRegs:$rd, IntRegs:$rd, 1), 0>;
356 // dec simm13, rd -> sub rd, simm13, rd
357 def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
359 // deccc rd -> subcc rd, 1, rd
360 def : InstAlias<"deccc $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
362 // deccc simm13, rd -> subcc rd, simm13, rd
363 def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
365 // btst reg_or_imm, reg -> andcc reg,reg_or_imm,%g0
366 def : InstAlias<"btst $rs2, $rs1", (ANDCCrr G0, IntRegs:$rs1, IntRegs:$rs2), 0>;
367 def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, i32imm:$simm13), 0>;
369 // bset reg_or_imm, rd -> or rd,reg_or_imm,rd
370 def : InstAlias<"bset $rs2, $rd", (ORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
371 def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
373 // bclr reg_or_imm, rd -> andn rd,reg_or_imm,rd
374 def : InstAlias<"bclr $rs2, $rd", (ANDNrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
375 def : InstAlias<"bclr $simm13, $rd", (ANDNri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
377 // btog reg_or_imm, rd -> xor rd,reg_or_imm,rd
378 def : InstAlias<"btog $rs2, $rd", (XORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
379 def : InstAlias<"btog $simm13, $rd", (XORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
382 // clr rd -> or %g0, %g0, rd
383 def : InstAlias<"clr $rd", (ORrr IntRegs:$rd, G0, G0), 0>;
385 // clr{b,h,} [addr] -> st{b,h,} %g0, [addr]
386 def : InstAlias<"clrb [$addr]", (STBrr MEMrr:$addr, G0), 0>;
387 def : InstAlias<"clrb [$addr]", (STBri MEMri:$addr, G0), 0>;
388 def : InstAlias<"clrh [$addr]", (STHrr MEMrr:$addr, G0), 0>;
389 def : InstAlias<"clrh [$addr]", (STHri MEMri:$addr, G0), 0>;
390 def : InstAlias<"clr [$addr]", (STrr MEMrr:$addr, G0), 0>;
391 def : InstAlias<"clr [$addr]", (STri MEMri:$addr, G0), 0>;
394 // mov reg_or_imm, rd -> or %g0, reg_or_imm, rd
395 def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
396 def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
398 // mov specialreg, rd -> rd specialreg, rd
399 def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>;
400 def : InstAlias<"mov %psr, $rd", (RDPSR IntRegs:$rd), 0>;
401 def : InstAlias<"mov %wim, $rd", (RDWIM IntRegs:$rd), 0>;
402 def : InstAlias<"mov %tbr, $rd", (RDTBR IntRegs:$rd), 0>;
404 // mov reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
405 def : InstAlias<"mov $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
406 def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
407 def : InstAlias<"mov $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
408 def : InstAlias<"mov $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
409 def : InstAlias<"mov $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
410 def : InstAlias<"mov $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
411 def : InstAlias<"mov $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
412 def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
414 // End of Section A.3
416 // wr reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
417 // (aka: omit the first arg when it's g0. This is not in the manual, but is
418 // supported by gnu and solaris as)
419 def : InstAlias<"wr $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
420 def : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
421 def : InstAlias<"wr $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
422 def : InstAlias<"wr $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
423 def : InstAlias<"wr $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
424 def : InstAlias<"wr $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
425 def : InstAlias<"wr $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
426 def : InstAlias<"wr $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
429 // flush -> flush %g0
430 def : InstAlias<"flush", (FLUSH), 0>;
433 def : MnemonicAlias<"lduw", "ld">, Requires<[HasV9]>;
434 def : MnemonicAlias<"lduwa", "lda">, Requires<[HasV9]>;
436 def : MnemonicAlias<"return", "rett">, Requires<[HasV9]>;
438 def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>;
439 def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>;
441 def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>;
442 def : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>;
445 def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
446 def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;
447 def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>,
448 Requires<[HasHardQuad]>;
450 def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
451 def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1,
453 def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1,
455 Requires<[HasHardQuad]>;
457 // signx rd -> sra rd, %g0, rd
458 def : InstAlias<"signx $rd", (SRArr IntRegs:$rd, IntRegs:$rd, G0), 0>, Requires<[HasV9]>;
460 // signx reg, rd -> sra reg, %g0, rd
461 def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Requires<[HasV9]>;