1 //===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction aliases for Sparc.
11 //===----------------------------------------------------------------------===//
13 // Instruction aliases for conditional moves.
15 // mov<cond> <ccreg> rs2, rd
16 multiclass cond_mov_alias<string cond, int condVal, string ccreg,
17 Instruction movrr, Instruction movri,
18 Instruction fmovs, Instruction fmovd> {
20 // mov<cond> (%icc|%xcc|%fcc0), rs2, rd
21 def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
23 (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
25 // mov<cond> (%icc|%xcc|%fcc0), simm11, rd
26 def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
28 (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
30 // fmovs<cond> (%icc|%xcc|%fcc0), $rs2, $rd
31 def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg),
33 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
35 // fmovd<cond> (%icc|%xcc|%fcc0), $rs2, $rd
36 def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg),
38 (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
42 // Instruction aliases for integer conditional branches and moves.
43 multiclass int_cond_alias<string cond, int condVal> {
46 def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
47 (BCOND brtarget:$imm, condVal)>;
50 def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
51 (BCONDA brtarget:$imm, condVal)>;
54 def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
55 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
57 // b<cond>,pt %icc, $imm
58 def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %icc, $imm"),
59 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
61 // b<cond>,a %icc, $imm
62 def : InstAlias<!strconcat(!strconcat("b", cond), ",a %icc, $imm"),
63 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
65 // b<cond>,a,pt %icc, $imm
66 def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %icc, $imm"),
67 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
69 // b<cond>,pn %icc, $imm
70 def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %icc, $imm"),
71 (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
73 // b<cond>,a,pn %icc, $imm
74 def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %icc, $imm"),
75 (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
78 def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"),
79 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
81 // b<cond>,pt %xcc, $imm
82 def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %xcc, $imm"),
83 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
85 // b<cond>,a %xcc, $imm
86 def : InstAlias<!strconcat(!strconcat("b", cond), ",a %xcc, $imm"),
87 (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
89 // b<cond>,a,pt %xcc, $imm
90 def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %xcc, $imm"),
91 (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
93 // b<cond>,pn %xcc, $imm
94 def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %xcc, $imm"),
95 (BPXCCNT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
97 // b<cond>,a,pn %xcc, $imm
98 def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %xcc, $imm"),
99 (BPXCCANT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
102 defm : cond_mov_alias<cond, condVal, " %icc",
104 FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>;
106 defm : cond_mov_alias<cond, condVal, " %xcc",
108 FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>;
110 // fmovq<cond> (%icc|%xcc), $rs2, $rd
111 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"),
112 (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
113 Requires<[HasV9, HasHardQuad]>;
114 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"),
115 (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
116 Requires<[Is64Bit, HasHardQuad]>;
121 // Instruction aliases for floating point conditional branches and moves.
122 multiclass fp_cond_alias<string cond, int condVal> {
125 def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"),
126 (FBCOND brtarget:$imm, condVal), 0>;
129 def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $imm"),
130 (FBCONDA brtarget:$imm, condVal), 0>;
132 // fb<cond> %fcc0, $imm
133 def : InstAlias<!strconcat(!strconcat("fb", cond), " %fcc0, $imm"),
134 (BPFCC brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
136 // fb<cond>,pt %fcc0, $imm
137 def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt %fcc0, $imm"),
138 (BPFCC brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
140 // fb<cond>,a %fcc0, $imm
141 def : InstAlias<!strconcat(!strconcat("fb", cond), ",a %fcc0, $imm"),
142 (BPFCCA brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
144 // fb<cond>,a,pt %fcc0, $imm
145 def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt %fcc0, $imm"),
146 (BPFCCA brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
148 // fb<cond>,pn %fcc0, $imm
149 def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn %fcc0, $imm"),
150 (BPFCCNT brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
152 // fb<cond>,a,pn %fcc0, $imm
153 def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn %fcc0, $imm"),
154 (BPFCCANT brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
156 defm : cond_mov_alias<cond, condVal, " %fcc0",
158 FMOVS_FCC, FMOVD_FCC>, Requires<[HasV9]>;
160 // fmovq<cond> %fcc0, $rs2, $rd
161 def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %fcc0, $rs2, $rd"),
162 (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
163 Requires<[HasV9, HasHardQuad]>;
166 defm : int_cond_alias<"a", 0b1000>;
167 defm : int_cond_alias<"n", 0b0000>;
168 defm : int_cond_alias<"ne", 0b1001>;
169 defm : int_cond_alias<"e", 0b0001>;
170 defm : int_cond_alias<"g", 0b1010>;
171 defm : int_cond_alias<"le", 0b0010>;
172 defm : int_cond_alias<"ge", 0b1011>;
173 defm : int_cond_alias<"l", 0b0011>;
174 defm : int_cond_alias<"gu", 0b1100>;
175 defm : int_cond_alias<"leu", 0b0100>;
176 defm : int_cond_alias<"cc", 0b1101>;
177 defm : int_cond_alias<"cs", 0b0101>;
178 defm : int_cond_alias<"pos", 0b1110>;
179 defm : int_cond_alias<"neg", 0b0110>;
180 defm : int_cond_alias<"vc", 0b1111>;
181 defm : int_cond_alias<"vs", 0b0111>;
183 defm : fp_cond_alias<"a", 0b0000>;
184 defm : fp_cond_alias<"n", 0b1000>;
185 defm : fp_cond_alias<"u", 0b0111>;
186 defm : fp_cond_alias<"g", 0b0110>;
187 defm : fp_cond_alias<"ug", 0b0101>;
188 defm : fp_cond_alias<"l", 0b0100>;
189 defm : fp_cond_alias<"ul", 0b0011>;
190 defm : fp_cond_alias<"lg", 0b0010>;
191 defm : fp_cond_alias<"ne", 0b0001>;
192 defm : fp_cond_alias<"e", 0b1001>;
193 defm : fp_cond_alias<"ue", 0b1010>;
194 defm : fp_cond_alias<"ge", 0b1011>;
195 defm : fp_cond_alias<"uge", 0b1100>;
196 defm : fp_cond_alias<"le", 0b1101>;
197 defm : fp_cond_alias<"ule", 0b1110>;
198 defm : fp_cond_alias<"o", 0b1111>;
201 // Instruction aliases for JMPL.
203 // jmp addr -> jmpl addr, %g0
204 def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr)>;
205 def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr)>;
207 // call addr -> jmpl addr, %o7
208 def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr)>;
209 def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr)>;
212 def : InstAlias<"retl", (RETL 8)>;
215 def : InstAlias<"ret", (RET 8)>;
217 // mov reg, rd -> or %g0, reg, rd
218 def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
220 // mov simm13, rd -> or %g0, simm13, rd
221 def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
223 // restore -> restore %g0, %g0, %g0
224 def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
226 def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>;
227 def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>;
229 def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>;
230 def : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>;
233 def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
234 def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;
235 def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>,
236 Requires<[HasHardQuad]>;