1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "SparcISelLowering.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcRegisterInfo.h"
18 #include "SparcTargetMachine.h"
19 #include "MCTargetDesc/SparcBaseInfo.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Module.h"
30 #include "llvm/Support/ErrorHandling.h"
34 //===----------------------------------------------------------------------===//
35 // Calling Convention Implementation
36 //===----------------------------------------------------------------------===//
38 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
39 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
40 ISD::ArgFlagsTy &ArgFlags, CCState &State)
42 assert (ArgFlags.isSRet());
44 // Assign SRet argument.
45 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
51 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
52 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
53 ISD::ArgFlagsTy &ArgFlags, CCState &State)
55 static const uint16_t RegList[] = {
56 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
58 // Try to get first reg.
59 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
60 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
62 // Assign whole thing in stack.
63 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
64 State.AllocateStack(8,4),
69 // Try to get second reg.
70 if (unsigned Reg = State.AllocateReg(RegList, 6))
71 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
73 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
74 State.AllocateStack(4,4),
79 // Allocate a full-sized argument for the 64-bit ABI.
80 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
81 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
82 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
83 assert((LocVT == MVT::f32 || LocVT.getSizeInBits() == 64) &&
84 "Can't handle non-64 bits locations");
86 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
87 unsigned Offset = State.AllocateStack(8, 8);
90 if (LocVT == MVT::i64 && Offset < 6*8)
91 // Promote integers to %i0-%i5.
92 Reg = SP::I0 + Offset/8;
93 else if (LocVT == MVT::f64 && Offset < 16*8)
94 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
95 Reg = SP::D0 + Offset/8;
96 else if (LocVT == MVT::f32 && Offset < 16*8)
97 // Promote floats to %f1, %f3, ...
98 Reg = SP::F1 + Offset/4;
100 // Promote to register when possible, otherwise use the stack slot.
102 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
106 // This argument goes on the stack in an 8-byte slot.
107 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
108 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
109 if (LocVT == MVT::f32)
112 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
116 // Allocate a half-sized argument for the 64-bit ABI.
118 // This is used when passing { float, int } structs by value in registers.
119 static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT,
120 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
121 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
122 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
123 unsigned Offset = State.AllocateStack(4, 4);
125 if (LocVT == MVT::f32 && Offset < 16*8) {
126 // Promote floats to %f0-%f31.
127 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
132 if (LocVT == MVT::i32 && Offset < 6*8) {
133 // Promote integers to %i0-%i5, using half the register.
134 unsigned Reg = SP::I0 + Offset/8;
136 LocInfo = CCValAssign::AExt;
138 // Set the Custom bit if this i32 goes in the high bits of a register.
140 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
143 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
147 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
151 #include "SparcGenCallingConv.inc"
153 // The calling conventions in SparcCallingConv.td are described in terms of the
154 // callee's register window. This function translates registers to the
155 // corresponding caller window %o register.
156 static unsigned toCallerWindow(unsigned Reg) {
157 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum");
158 if (Reg >= SP::I0 && Reg <= SP::I7)
159 return Reg - SP::I0 + SP::O0;
164 SparcTargetLowering::LowerReturn(SDValue Chain,
165 CallingConv::ID CallConv, bool IsVarArg,
166 const SmallVectorImpl<ISD::OutputArg> &Outs,
167 const SmallVectorImpl<SDValue> &OutVals,
168 SDLoc DL, SelectionDAG &DAG) const {
169 if (Subtarget->is64Bit())
170 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
171 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
175 SparcTargetLowering::LowerReturn_32(SDValue Chain,
176 CallingConv::ID CallConv, bool IsVarArg,
177 const SmallVectorImpl<ISD::OutputArg> &Outs,
178 const SmallVectorImpl<SDValue> &OutVals,
179 SDLoc DL, SelectionDAG &DAG) const {
180 MachineFunction &MF = DAG.getMachineFunction();
182 // CCValAssign - represent the assignment of the return value to locations.
183 SmallVector<CCValAssign, 16> RVLocs;
185 // CCState - Info about the registers and stack slot.
186 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
187 DAG.getTarget(), RVLocs, *DAG.getContext());
189 // Analyze return values.
190 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
193 SmallVector<SDValue, 4> RetOps(1, Chain);
194 // Make room for the return address offset.
195 RetOps.push_back(SDValue());
197 // Copy the result values into the output registers.
198 for (unsigned i = 0; i != RVLocs.size(); ++i) {
199 CCValAssign &VA = RVLocs[i];
200 assert(VA.isRegLoc() && "Can only return in registers!");
202 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(),
205 // Guarantee that all emitted copies are stuck together with flags.
206 Flag = Chain.getValue(1);
207 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
210 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
211 // If the function returns a struct, copy the SRetReturnReg to I0
212 if (MF.getFunction()->hasStructRetAttr()) {
213 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
214 unsigned Reg = SFI->getSRetReturnReg();
216 llvm_unreachable("sret virtual register not created in the entry block");
217 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
218 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
219 Flag = Chain.getValue(1);
220 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy()));
221 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
224 RetOps[0] = Chain; // Update chain.
225 RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);
227 // Add the flag if we have it.
229 RetOps.push_back(Flag);
231 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other,
232 &RetOps[0], RetOps.size());
235 // Lower return values for the 64-bit ABI.
236 // Return values are passed the exactly the same way as function arguments.
238 SparcTargetLowering::LowerReturn_64(SDValue Chain,
239 CallingConv::ID CallConv, bool IsVarArg,
240 const SmallVectorImpl<ISD::OutputArg> &Outs,
241 const SmallVectorImpl<SDValue> &OutVals,
242 SDLoc DL, SelectionDAG &DAG) const {
243 // CCValAssign - represent the assignment of the return value to locations.
244 SmallVector<CCValAssign, 16> RVLocs;
246 // CCState - Info about the registers and stack slot.
247 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
248 DAG.getTarget(), RVLocs, *DAG.getContext());
250 // Analyze return values.
251 CCInfo.AnalyzeReturn(Outs, CC_Sparc64);
254 SmallVector<SDValue, 4> RetOps(1, Chain);
256 // The second operand on the return instruction is the return address offset.
257 // The return address is always %i7+8 with the 64-bit ABI.
258 RetOps.push_back(DAG.getConstant(8, MVT::i32));
260 // Copy the result values into the output registers.
261 for (unsigned i = 0; i != RVLocs.size(); ++i) {
262 CCValAssign &VA = RVLocs[i];
263 assert(VA.isRegLoc() && "Can only return in registers!");
264 SDValue OutVal = OutVals[i];
266 // Integer return values must be sign or zero extended by the callee.
267 switch (VA.getLocInfo()) {
268 case CCValAssign::SExt:
269 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
271 case CCValAssign::ZExt:
272 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
274 case CCValAssign::AExt:
275 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
280 // The custom bit on an i32 return value indicates that it should be passed
281 // in the high bits of the register.
282 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
283 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
284 DAG.getConstant(32, MVT::i32));
286 // The next value may go in the low bits of the same register.
287 // Handle both at once.
288 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
289 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
290 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
291 // Skip the next value, it's already done.
296 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
298 // Guarantee that all emitted copies are stuck together with flags.
299 Flag = Chain.getValue(1);
300 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
303 RetOps[0] = Chain; // Update chain.
305 // Add the flag if we have it.
307 RetOps.push_back(Flag);
309 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other,
310 &RetOps[0], RetOps.size());
313 SDValue SparcTargetLowering::
314 LowerFormalArguments(SDValue Chain,
315 CallingConv::ID CallConv,
317 const SmallVectorImpl<ISD::InputArg> &Ins,
320 SmallVectorImpl<SDValue> &InVals) const {
321 if (Subtarget->is64Bit())
322 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
324 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
328 /// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
329 /// passed in either one or two GPRs, including FP values. TODO: we should
330 /// pass FP values in FP registers for fastcc functions.
331 SDValue SparcTargetLowering::
332 LowerFormalArguments_32(SDValue Chain,
333 CallingConv::ID CallConv,
335 const SmallVectorImpl<ISD::InputArg> &Ins,
338 SmallVectorImpl<SDValue> &InVals) const {
339 MachineFunction &MF = DAG.getMachineFunction();
340 MachineRegisterInfo &RegInfo = MF.getRegInfo();
341 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
343 // Assign locations to all of the incoming arguments.
344 SmallVector<CCValAssign, 16> ArgLocs;
345 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
346 getTargetMachine(), ArgLocs, *DAG.getContext());
347 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
349 const unsigned StackOffset = 92;
351 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
352 CCValAssign &VA = ArgLocs[i];
354 if (i == 0 && Ins[i].Flags.isSRet()) {
355 // Get SRet from [%fp+64].
356 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true);
357 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
358 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
359 MachinePointerInfo(),
360 false, false, false, 0);
361 InVals.push_back(Arg);
366 if (VA.needsCustom()) {
367 assert(VA.getLocVT() == MVT::f64);
368 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
369 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
370 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
373 CCValAssign &NextVA = ArgLocs[++i];
376 if (NextVA.isMemLoc()) {
377 int FrameIdx = MF.getFrameInfo()->
378 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
379 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
380 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
381 MachinePointerInfo(),
382 false, false, false, 0);
384 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
385 &SP::IntRegsRegClass);
386 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
389 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
390 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
391 InVals.push_back(WholeValue);
394 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
395 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
396 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
397 if (VA.getLocVT() == MVT::f32)
398 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
399 else if (VA.getLocVT() != MVT::i32) {
400 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
401 DAG.getValueType(VA.getLocVT()));
402 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
404 InVals.push_back(Arg);
408 assert(VA.isMemLoc());
410 unsigned Offset = VA.getLocMemOffset()+StackOffset;
412 if (VA.needsCustom()) {
413 assert(VA.getValVT() == MVT::f64);
414 // If it is double-word aligned, just load.
415 if (Offset % 8 == 0) {
416 int FI = MF.getFrameInfo()->CreateFixedObject(8,
419 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
420 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
421 MachinePointerInfo(),
422 false,false, false, 0);
423 InVals.push_back(Load);
427 int FI = MF.getFrameInfo()->CreateFixedObject(4,
430 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
431 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
432 MachinePointerInfo(),
433 false, false, false, 0);
434 int FI2 = MF.getFrameInfo()->CreateFixedObject(4,
437 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy());
439 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2,
440 MachinePointerInfo(),
441 false, false, false, 0);
444 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
445 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
446 InVals.push_back(WholeValue);
450 int FI = MF.getFrameInfo()->CreateFixedObject(4,
453 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
455 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
456 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
457 MachinePointerInfo(),
458 false, false, false, 0);
460 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
461 // Sparc is big endian, so add an offset based on the ObjectVT.
462 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
463 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
464 DAG.getConstant(Offset, MVT::i32));
465 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
466 MachinePointerInfo(),
467 VA.getValVT(), false, false,0);
468 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
470 InVals.push_back(Load);
473 if (MF.getFunction()->hasStructRetAttr()) {
474 // Copy the SRet Argument to SRetReturnReg.
475 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
476 unsigned Reg = SFI->getSRetReturnReg();
478 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
479 SFI->setSRetReturnReg(Reg);
481 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
482 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
485 // Store remaining ArgRegs to the stack if this is a varargs function.
487 static const uint16_t ArgRegs[] = {
488 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
490 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6);
491 const uint16_t *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
492 unsigned ArgOffset = CCInfo.getNextStackOffset();
493 if (NumAllocated == 6)
494 ArgOffset += StackOffset;
497 ArgOffset = 68+4*NumAllocated;
500 // Remember the vararg offset for the va_start implementation.
501 FuncInfo->setVarArgsFrameOffset(ArgOffset);
503 std::vector<SDValue> OutChains;
505 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
506 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
507 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
508 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
510 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
512 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
514 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr,
515 MachinePointerInfo(),
520 if (!OutChains.empty()) {
521 OutChains.push_back(Chain);
522 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
523 &OutChains[0], OutChains.size());
530 // Lower formal arguments for the 64 bit ABI.
531 SDValue SparcTargetLowering::
532 LowerFormalArguments_64(SDValue Chain,
533 CallingConv::ID CallConv,
535 const SmallVectorImpl<ISD::InputArg> &Ins,
538 SmallVectorImpl<SDValue> &InVals) const {
539 MachineFunction &MF = DAG.getMachineFunction();
541 // Analyze arguments according to CC_Sparc64.
542 SmallVector<CCValAssign, 16> ArgLocs;
543 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
544 getTargetMachine(), ArgLocs, *DAG.getContext());
545 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
547 // The argument array begins at %fp+BIAS+128, after the register save area.
548 const unsigned ArgArea = 128;
550 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
551 CCValAssign &VA = ArgLocs[i];
553 // This argument is passed in a register.
554 // All integer register arguments are promoted by the caller to i64.
556 // Create a virtual register for the promoted live-in value.
557 unsigned VReg = MF.addLiveIn(VA.getLocReg(),
558 getRegClassFor(VA.getLocVT()));
559 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
561 // Get the high bits for i32 struct elements.
562 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
563 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
564 DAG.getConstant(32, MVT::i32));
566 // The caller promoted the argument, so insert an Assert?ext SDNode so we
567 // won't promote the value again in this function.
568 switch (VA.getLocInfo()) {
569 case CCValAssign::SExt:
570 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
571 DAG.getValueType(VA.getValVT()));
573 case CCValAssign::ZExt:
574 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
575 DAG.getValueType(VA.getValVT()));
581 // Truncate the register down to the argument type.
583 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
585 InVals.push_back(Arg);
589 // The registers are exhausted. This argument was passed on the stack.
590 assert(VA.isMemLoc());
591 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
592 // beginning of the arguments area at %fp+BIAS+128.
593 unsigned Offset = VA.getLocMemOffset() + ArgArea;
594 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
595 // Adjust offset for extended arguments, SPARC is big-endian.
596 // The caller will have written the full slot with extended bytes, but we
597 // prefer our own extending loads.
599 Offset += 8 - ValSize;
600 int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true);
601 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain,
602 DAG.getFrameIndex(FI, getPointerTy()),
603 MachinePointerInfo::getFixedStack(FI),
604 false, false, false, 0));
610 // This function takes variable arguments, some of which may have been passed
611 // in registers %i0-%i5. Variable floating point arguments are never passed
612 // in floating point registers. They go on %i0-%i5 or on the stack like
613 // integer arguments.
615 // The va_start intrinsic needs to know the offset to the first variable
617 unsigned ArgOffset = CCInfo.getNextStackOffset();
618 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
619 // Skip the 128 bytes of register save area.
620 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
621 Subtarget->getStackPointerBias());
623 // Save the variable arguments that were passed in registers.
624 // The caller is required to reserve stack space for 6 arguments regardless
625 // of how many arguments were actually passed.
626 SmallVector<SDValue, 8> OutChains;
627 for (; ArgOffset < 6*8; ArgOffset += 8) {
628 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
629 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
630 int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true);
631 OutChains.push_back(DAG.getStore(Chain, DL, VArg,
632 DAG.getFrameIndex(FI, getPointerTy()),
633 MachinePointerInfo::getFixedStack(FI),
637 if (!OutChains.empty())
638 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
639 &OutChains[0], OutChains.size());
645 SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
646 SmallVectorImpl<SDValue> &InVals) const {
647 if (Subtarget->is64Bit())
648 return LowerCall_64(CLI, InVals);
649 return LowerCall_32(CLI, InVals);
652 static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
653 ImmutableCallSite *CS) {
655 return CS->hasFnAttr(Attribute::ReturnsTwice);
657 const Function *CalleeFn = 0;
658 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
659 CalleeFn = dyn_cast<Function>(G->getGlobal());
660 } else if (ExternalSymbolSDNode *E =
661 dyn_cast<ExternalSymbolSDNode>(Callee)) {
662 const Function *Fn = DAG.getMachineFunction().getFunction();
663 const Module *M = Fn->getParent();
664 const char *CalleeName = E->getSymbol();
665 CalleeFn = M->getFunction(CalleeName);
670 return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
673 // Lower a call for the 32-bit ABI.
675 SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
676 SmallVectorImpl<SDValue> &InVals) const {
677 SelectionDAG &DAG = CLI.DAG;
679 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
680 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
681 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
682 SDValue Chain = CLI.Chain;
683 SDValue Callee = CLI.Callee;
684 bool &isTailCall = CLI.IsTailCall;
685 CallingConv::ID CallConv = CLI.CallConv;
686 bool isVarArg = CLI.IsVarArg;
688 // Sparc target does not yet support tail call optimization.
691 // Analyze operands of the call, assigning locations to each operand.
692 SmallVector<CCValAssign, 16> ArgLocs;
693 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
694 DAG.getTarget(), ArgLocs, *DAG.getContext());
695 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
697 // Get the size of the outgoing arguments stack space requirement.
698 unsigned ArgsSize = CCInfo.getNextStackOffset();
700 // Keep stack frames 8-byte aligned.
701 ArgsSize = (ArgsSize+7) & ~7;
703 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
705 // Create local copies for byval args.
706 SmallVector<SDValue, 8> ByValArgs;
707 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
708 ISD::ArgFlagsTy Flags = Outs[i].Flags;
709 if (!Flags.isByVal())
712 SDValue Arg = OutVals[i];
713 unsigned Size = Flags.getByValSize();
714 unsigned Align = Flags.getByValAlign();
716 int FI = MFI->CreateStackObject(Size, Align, false);
717 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
718 SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
720 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
721 false, // isVolatile,
722 (Size <= 32), // AlwaysInline if size <= 32
723 MachinePointerInfo(), MachinePointerInfo());
724 ByValArgs.push_back(FIPtr);
727 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
730 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
731 SmallVector<SDValue, 8> MemOpChains;
733 const unsigned StackOffset = 92;
734 bool hasStructRetAttr = false;
735 // Walk the register/memloc assignments, inserting copies/loads.
736 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
739 CCValAssign &VA = ArgLocs[i];
740 SDValue Arg = OutVals[realArgIdx];
742 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
744 // Use local copy if it is a byval arg.
746 Arg = ByValArgs[byvalArgIdx++];
748 // Promote the value if needed.
749 switch (VA.getLocInfo()) {
750 default: llvm_unreachable("Unknown loc info!");
751 case CCValAssign::Full: break;
752 case CCValAssign::SExt:
753 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
755 case CCValAssign::ZExt:
756 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
758 case CCValAssign::AExt:
759 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
761 case CCValAssign::BCvt:
762 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
766 if (Flags.isSRet()) {
767 assert(VA.needsCustom());
768 // store SRet argument in %sp+64
769 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
770 SDValue PtrOff = DAG.getIntPtrConstant(64);
771 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
772 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
773 MachinePointerInfo(),
775 hasStructRetAttr = true;
779 if (VA.needsCustom()) {
780 assert(VA.getLocVT() == MVT::f64);
783 unsigned Offset = VA.getLocMemOffset() + StackOffset;
784 // if it is double-word aligned, just store.
785 if (Offset % 8 == 0) {
786 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
787 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
788 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
789 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
790 MachinePointerInfo(),
796 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
797 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
798 Arg, StackPtr, MachinePointerInfo(),
800 // Sparc is big-endian, so the high part comes first.
801 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
802 MachinePointerInfo(), false, false, false, 0);
803 // Increment the pointer to the other half.
804 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
805 DAG.getIntPtrConstant(4));
806 // Load the low part.
807 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
808 MachinePointerInfo(), false, false, false, 0);
811 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
813 CCValAssign &NextVA = ArgLocs[++i];
814 if (NextVA.isRegLoc()) {
815 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
817 // Store the low part in stack.
818 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
819 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
820 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
821 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
822 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
823 MachinePointerInfo(),
827 unsigned Offset = VA.getLocMemOffset() + StackOffset;
828 // Store the high part.
829 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
830 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
831 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
832 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
833 MachinePointerInfo(),
835 // Store the low part.
836 PtrOff = DAG.getIntPtrConstant(Offset+4);
837 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
838 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
839 MachinePointerInfo(),
845 // Arguments that can be passed on register must be kept at
848 if (VA.getLocVT() != MVT::f32) {
849 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
852 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
853 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
857 assert(VA.isMemLoc());
859 // Create a store off the stack pointer for this argument.
860 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
861 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);
862 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
863 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
864 MachinePointerInfo(),
869 // Emit all stores, make sure the occur before any copies into physregs.
870 if (!MemOpChains.empty())
871 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
872 &MemOpChains[0], MemOpChains.size());
874 // Build a sequence of copy-to-reg nodes chained together with token
875 // chain and flag operands which copy the outgoing args into registers.
876 // The InFlag in necessary since all emitted instructions must be
879 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
880 unsigned Reg = toCallerWindow(RegsToPass[i].first);
881 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
882 InFlag = Chain.getValue(1);
885 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;
886 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
888 // If the callee is a GlobalAddress node (quite common, every direct call is)
889 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
890 // Likewise ExternalSymbol -> TargetExternalSymbol.
891 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
892 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
893 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
894 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
896 // Returns a chain & a flag for retval copy to use
897 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
898 SmallVector<SDValue, 8> Ops;
899 Ops.push_back(Chain);
900 Ops.push_back(Callee);
901 if (hasStructRetAttr)
902 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32));
903 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
904 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
905 RegsToPass[i].second.getValueType()));
907 // Add a register mask operand representing the call-preserved registers.
908 const SparcRegisterInfo *TRI =
909 ((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo();
910 const uint32_t *Mask = ((hasReturnsTwice)
911 ? TRI->getRTCallPreservedMask(CallConv)
912 : TRI->getCallPreservedMask(CallConv));
913 assert(Mask && "Missing call preserved mask for calling convention");
914 Ops.push_back(DAG.getRegisterMask(Mask));
916 if (InFlag.getNode())
917 Ops.push_back(InFlag);
919 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
920 InFlag = Chain.getValue(1);
922 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
923 DAG.getIntPtrConstant(0, true), InFlag, dl);
924 InFlag = Chain.getValue(1);
926 // Assign locations to each value returned by this call.
927 SmallVector<CCValAssign, 16> RVLocs;
928 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(),
929 DAG.getTarget(), RVLocs, *DAG.getContext());
931 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
933 // Copy all of the result registers out of their specified physreg.
934 for (unsigned i = 0; i != RVLocs.size(); ++i) {
935 Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
936 RVLocs[i].getValVT(), InFlag).getValue(1);
937 InFlag = Chain.getValue(2);
938 InVals.push_back(Chain.getValue(0));
944 // This functions returns true if CalleeName is a ABI function that returns
945 // a long double (fp128).
946 static bool isFP128ABICall(const char *CalleeName)
948 static const char *const ABICalls[] =
949 { "_Q_add", "_Q_sub", "_Q_mul", "_Q_div",
951 "_Q_itoq", "_Q_stoq", "_Q_dtoq", "_Q_utoq",
952 "_Q_lltoq", "_Q_ulltoq",
955 for (const char * const *I = ABICalls; *I != 0; ++I)
956 if (strcmp(CalleeName, *I) == 0)
962 SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
964 const Function *CalleeFn = 0;
965 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
966 CalleeFn = dyn_cast<Function>(G->getGlobal());
967 } else if (ExternalSymbolSDNode *E =
968 dyn_cast<ExternalSymbolSDNode>(Callee)) {
969 const Function *Fn = DAG.getMachineFunction().getFunction();
970 const Module *M = Fn->getParent();
971 const char *CalleeName = E->getSymbol();
972 CalleeFn = M->getFunction(CalleeName);
973 if (!CalleeFn && isFP128ABICall(CalleeName))
974 return 16; // Return sizeof(fp128)
980 assert(CalleeFn->hasStructRetAttr() &&
981 "Callee does not have the StructRet attribute.");
983 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType());
984 Type *ElementTy = Ty->getElementType();
985 return getDataLayout()->getTypeAllocSize(ElementTy);
989 // Fixup floating point arguments in the ... part of a varargs call.
991 // The SPARC v9 ABI requires that floating point arguments are treated the same
992 // as integers when calling a varargs function. This does not apply to the
993 // fixed arguments that are part of the function's prototype.
995 // This function post-processes a CCValAssign array created by
996 // AnalyzeCallOperands().
997 static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
998 ArrayRef<ISD::OutputArg> Outs) {
999 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1000 const CCValAssign &VA = ArgLocs[i];
1001 // FIXME: What about f32 arguments? C promotes them to f64 when calling
1002 // varargs functions.
1003 if (!VA.isRegLoc() || VA.getLocVT() != MVT::f64)
1005 // The fixed arguments to a varargs function still go in FP registers.
1006 if (Outs[VA.getValNo()].IsFixed)
1009 // This floating point argument should be reassigned.
1012 // Determine the offset into the argument array.
1013 unsigned Offset = 8 * (VA.getLocReg() - SP::D0);
1014 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1017 // This argument should go in %i0-%i5.
1018 unsigned IReg = SP::I0 + Offset/8;
1019 // Full register, just bitconvert into i64.
1020 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
1021 IReg, MVT::i64, CCValAssign::BCvt);
1023 // This needs to go to memory, we're out of integer registers.
1024 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
1025 Offset, VA.getLocVT(), VA.getLocInfo());
1031 // Lower a call for the 64-bit ABI.
1033 SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
1034 SmallVectorImpl<SDValue> &InVals) const {
1035 SelectionDAG &DAG = CLI.DAG;
1037 SDValue Chain = CLI.Chain;
1039 // Sparc target does not yet support tail call optimization.
1040 CLI.IsTailCall = false;
1042 // Analyze operands of the call, assigning locations to each operand.
1043 SmallVector<CCValAssign, 16> ArgLocs;
1044 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
1045 DAG.getTarget(), ArgLocs, *DAG.getContext());
1046 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
1048 // Get the size of the outgoing arguments stack space requirement.
1049 // The stack offset computed by CC_Sparc64 includes all arguments.
1050 // Called functions expect 6 argument words to exist in the stack frame, used
1052 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset());
1054 // Keep stack frames 16-byte aligned.
1055 ArgsSize = RoundUpToAlignment(ArgsSize, 16);
1057 // Varargs calls require special treatment.
1059 fixupVariableFloatArgs(ArgLocs, CLI.Outs);
1061 // Adjust the stack pointer to make room for the arguments.
1062 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1063 // with more than 6 arguments.
1064 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
1067 // Collect the set of registers to pass to the function and their values.
1068 // This will be emitted as a sequence of CopyToReg nodes glued to the call
1070 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1072 // Collect chains from all the memory opeations that copy arguments to the
1073 // stack. They must follow the stack pointer adjustment above and precede the
1074 // call instruction itself.
1075 SmallVector<SDValue, 8> MemOpChains;
1077 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1078 const CCValAssign &VA = ArgLocs[i];
1079 SDValue Arg = CLI.OutVals[i];
1081 // Promote the value if needed.
1082 switch (VA.getLocInfo()) {
1084 llvm_unreachable("Unknown location info!");
1085 case CCValAssign::Full:
1087 case CCValAssign::SExt:
1088 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1090 case CCValAssign::ZExt:
1091 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1093 case CCValAssign::AExt:
1094 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
1096 case CCValAssign::BCvt:
1097 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1101 if (VA.isRegLoc()) {
1102 // The custom bit on an i32 return value indicates that it should be
1103 // passed in the high bits of the register.
1104 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1105 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1106 DAG.getConstant(32, MVT::i32));
1108 // The next value may go in the low bits of the same register.
1109 // Handle both at once.
1110 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1111 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1112 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
1114 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
1115 // Skip the next value, it's already done.
1119 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg));
1123 assert(VA.isMemLoc());
1125 // Create a store off the stack pointer for this argument.
1126 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
1127 // The argument area starts at %fp+BIAS+128 in the callee frame,
1128 // %sp+BIAS+128 in ours.
1129 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
1130 Subtarget->getStackPointerBias() +
1132 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
1133 MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff,
1134 MachinePointerInfo(),
1138 // Emit all stores, make sure they occur before the call.
1139 if (!MemOpChains.empty())
1140 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1141 &MemOpChains[0], MemOpChains.size());
1143 // Build a sequence of CopyToReg nodes glued together with token chain and
1144 // glue operands which copy the outgoing args into registers. The InGlue is
1145 // necessary since all emitted instructions must be stuck together in order
1146 // to pass the live physical registers.
1148 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1149 Chain = DAG.getCopyToReg(Chain, DL,
1150 RegsToPass[i].first, RegsToPass[i].second, InGlue);
1151 InGlue = Chain.getValue(1);
1154 // If the callee is a GlobalAddress node (quite common, every direct call is)
1155 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1156 // Likewise ExternalSymbol -> TargetExternalSymbol.
1157 SDValue Callee = CLI.Callee;
1158 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
1159 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1160 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy());
1161 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1162 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
1164 // Build the operands for the call instruction itself.
1165 SmallVector<SDValue, 8> Ops;
1166 Ops.push_back(Chain);
1167 Ops.push_back(Callee);
1168 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1169 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1170 RegsToPass[i].second.getValueType()));
1172 // Add a register mask operand representing the call-preserved registers.
1173 const SparcRegisterInfo *TRI =
1174 ((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo();
1175 const uint32_t *Mask = ((hasReturnsTwice)
1176 ? TRI->getRTCallPreservedMask(CLI.CallConv)
1177 : TRI->getCallPreservedMask(CLI.CallConv));
1178 assert(Mask && "Missing call preserved mask for calling convention");
1179 Ops.push_back(DAG.getRegisterMask(Mask));
1181 // Make sure the CopyToReg nodes are glued to the call instruction which
1182 // consumes the registers.
1183 if (InGlue.getNode())
1184 Ops.push_back(InGlue);
1186 // Now the call itself.
1187 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1188 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
1189 InGlue = Chain.getValue(1);
1191 // Revert the stack pointer immediately after the call.
1192 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
1193 DAG.getIntPtrConstant(0, true), InGlue, DL);
1194 InGlue = Chain.getValue(1);
1196 // Now extract the return values. This is more or less the same as
1197 // LowerFormalArguments_64.
1199 // Assign locations to each value returned by this call.
1200 SmallVector<CCValAssign, 16> RVLocs;
1201 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
1202 DAG.getTarget(), RVLocs, *DAG.getContext());
1203 RVInfo.AnalyzeCallResult(CLI.Ins, CC_Sparc64);
1205 // Copy all of the result registers out of their specified physreg.
1206 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1207 CCValAssign &VA = RVLocs[i];
1208 unsigned Reg = toCallerWindow(VA.getLocReg());
1210 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1211 // reside in the same register in the high and low bits. Reuse the
1212 // CopyFromReg previous node to avoid duplicate copies.
1214 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1215 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1216 RV = Chain.getValue(0);
1218 // But usually we'll create a new CopyFromReg for a different register.
1219 if (!RV.getNode()) {
1220 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1221 Chain = RV.getValue(1);
1222 InGlue = Chain.getValue(2);
1225 // Get the high bits for i32 struct elements.
1226 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1227 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
1228 DAG.getConstant(32, MVT::i32));
1230 // The callee promoted the return value, so insert an Assert?ext SDNode so
1231 // we won't promote the value again in this function.
1232 switch (VA.getLocInfo()) {
1233 case CCValAssign::SExt:
1234 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
1235 DAG.getValueType(VA.getValVT()));
1237 case CCValAssign::ZExt:
1238 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
1239 DAG.getValueType(VA.getValVT()));
1245 // Truncate the register down to the return value type.
1246 if (VA.isExtInLoc())
1247 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
1249 InVals.push_back(RV);
1255 //===----------------------------------------------------------------------===//
1256 // TargetLowering Implementation
1257 //===----------------------------------------------------------------------===//
1259 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1261 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1263 default: llvm_unreachable("Unknown integer condition code!");
1264 case ISD::SETEQ: return SPCC::ICC_E;
1265 case ISD::SETNE: return SPCC::ICC_NE;
1266 case ISD::SETLT: return SPCC::ICC_L;
1267 case ISD::SETGT: return SPCC::ICC_G;
1268 case ISD::SETLE: return SPCC::ICC_LE;
1269 case ISD::SETGE: return SPCC::ICC_GE;
1270 case ISD::SETULT: return SPCC::ICC_CS;
1271 case ISD::SETULE: return SPCC::ICC_LEU;
1272 case ISD::SETUGT: return SPCC::ICC_GU;
1273 case ISD::SETUGE: return SPCC::ICC_CC;
1277 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1279 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1281 default: llvm_unreachable("Unknown fp condition code!");
1283 case ISD::SETOEQ: return SPCC::FCC_E;
1285 case ISD::SETUNE: return SPCC::FCC_NE;
1287 case ISD::SETOLT: return SPCC::FCC_L;
1289 case ISD::SETOGT: return SPCC::FCC_G;
1291 case ISD::SETOLE: return SPCC::FCC_LE;
1293 case ISD::SETOGE: return SPCC::FCC_GE;
1294 case ISD::SETULT: return SPCC::FCC_UL;
1295 case ISD::SETULE: return SPCC::FCC_ULE;
1296 case ISD::SETUGT: return SPCC::FCC_UG;
1297 case ISD::SETUGE: return SPCC::FCC_UGE;
1298 case ISD::SETUO: return SPCC::FCC_U;
1299 case ISD::SETO: return SPCC::FCC_O;
1300 case ISD::SETONE: return SPCC::FCC_LG;
1301 case ISD::SETUEQ: return SPCC::FCC_UE;
1305 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
1306 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
1307 Subtarget = &TM.getSubtarget<SparcSubtarget>();
1309 // Set up the register classes.
1310 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1311 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1312 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1313 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1314 if (Subtarget->is64Bit())
1315 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1317 // Turn FP extload into load/fextend
1318 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
1319 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
1321 // Sparc doesn't have i1 sign extending load
1322 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
1324 // Turn FP truncstore into trunc + store.
1325 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1326 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1327 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1329 // Custom legalize GlobalAddress nodes into LO/HI parts.
1330 setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom);
1331 setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom);
1332 setOperationAction(ISD::ConstantPool, getPointerTy(), Custom);
1333 setOperationAction(ISD::BlockAddress, getPointerTy(), Custom);
1335 // Sparc doesn't have sext_inreg, replace them with shl/sra
1336 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1337 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
1338 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1340 // Sparc has no REM or DIVREM operations.
1341 setOperationAction(ISD::UREM, MVT::i32, Expand);
1342 setOperationAction(ISD::SREM, MVT::i32, Expand);
1343 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1344 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1346 // ... nor does SparcV9.
1347 if (Subtarget->is64Bit()) {
1348 setOperationAction(ISD::UREM, MVT::i64, Expand);
1349 setOperationAction(ISD::SREM, MVT::i64, Expand);
1350 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1351 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1354 // Custom expand fp<->sint
1355 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1356 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1357 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
1358 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
1360 // Custom Expand fp<->uint
1361 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1362 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1363 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
1364 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
1366 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
1367 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
1369 // Sparc has no select or setcc: expand to SELECT_CC.
1370 setOperationAction(ISD::SELECT, MVT::i32, Expand);
1371 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1372 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1373 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1375 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1376 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1377 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1378 setOperationAction(ISD::SETCC, MVT::f128, Expand);
1380 // Sparc doesn't have BRCOND either, it has BR_CC.
1381 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
1382 setOperationAction(ISD::BRIND, MVT::Other, Expand);
1383 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1384 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1385 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1386 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1387 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
1389 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1390 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1391 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1392 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1394 if (Subtarget->is64Bit()) {
1395 setOperationAction(ISD::ADDC, MVT::i64, Custom);
1396 setOperationAction(ISD::ADDE, MVT::i64, Custom);
1397 setOperationAction(ISD::SUBC, MVT::i64, Custom);
1398 setOperationAction(ISD::SUBE, MVT::i64, Custom);
1399 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
1400 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
1401 setOperationAction(ISD::SELECT, MVT::i64, Expand);
1402 setOperationAction(ISD::SETCC, MVT::i64, Expand);
1403 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
1404 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1406 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
1407 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1408 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
1409 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
1411 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1414 // FIXME: There are instructions available for ATOMIC_FENCE
1415 // on SparcV8 and later.
1416 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
1418 if (!Subtarget->isV9()) {
1419 // SparcV8 does not have FNEGD and FABSD.
1420 setOperationAction(ISD::FNEG, MVT::f64, Custom);
1421 setOperationAction(ISD::FABS, MVT::f64, Custom);
1424 setOperationAction(ISD::FSIN , MVT::f128, Expand);
1425 setOperationAction(ISD::FCOS , MVT::f128, Expand);
1426 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
1427 setOperationAction(ISD::FREM , MVT::f128, Expand);
1428 setOperationAction(ISD::FMA , MVT::f128, Expand);
1429 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1430 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1431 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1432 setOperationAction(ISD::FREM , MVT::f64, Expand);
1433 setOperationAction(ISD::FMA , MVT::f64, Expand);
1434 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1435 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1436 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1437 setOperationAction(ISD::FREM , MVT::f32, Expand);
1438 setOperationAction(ISD::FMA , MVT::f32, Expand);
1439 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1440 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1441 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1442 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1443 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1444 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1445 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1446 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1447 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1448 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1449 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1450 setOperationAction(ISD::FPOW , MVT::f128, Expand);
1451 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1452 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1454 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1455 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1456 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1458 // FIXME: Sparc provides these multiplies, but we don't have them yet.
1459 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1460 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1462 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1463 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1464 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1465 setOperationAction(ISD::VAARG , MVT::Other, Custom);
1467 // Use the default implementation.
1468 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1469 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1470 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
1471 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
1472 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
1474 setExceptionPointerRegister(SP::I0);
1475 setExceptionSelectorRegister(SP::I1);
1477 setStackPointerRegisterToSaveRestore(SP::O6);
1479 if (Subtarget->isV9())
1480 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
1482 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1483 setOperationAction(ISD::LOAD, MVT::f128, Legal);
1484 setOperationAction(ISD::STORE, MVT::f128, Legal);
1486 setOperationAction(ISD::LOAD, MVT::f128, Custom);
1487 setOperationAction(ISD::STORE, MVT::f128, Custom);
1490 if (Subtarget->hasHardQuad()) {
1491 setOperationAction(ISD::FADD, MVT::f128, Legal);
1492 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1493 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1494 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1495 setOperationAction(ISD::FSQRT, MVT::f128, Legal);
1496 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1497 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1498 if (Subtarget->isV9()) {
1499 setOperationAction(ISD::FNEG, MVT::f128, Legal);
1500 setOperationAction(ISD::FABS, MVT::f128, Legal);
1502 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1503 setOperationAction(ISD::FABS, MVT::f128, Custom);
1506 if (!Subtarget->is64Bit()) {
1507 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1508 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1509 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1510 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1514 // Custom legalize f128 operations.
1516 setOperationAction(ISD::FADD, MVT::f128, Custom);
1517 setOperationAction(ISD::FSUB, MVT::f128, Custom);
1518 setOperationAction(ISD::FMUL, MVT::f128, Custom);
1519 setOperationAction(ISD::FDIV, MVT::f128, Custom);
1520 setOperationAction(ISD::FSQRT, MVT::f128, Custom);
1521 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1522 setOperationAction(ISD::FABS, MVT::f128, Custom);
1524 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
1525 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
1526 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1528 // Setup Runtime library names.
1529 if (Subtarget->is64Bit()) {
1530 setLibcallName(RTLIB::ADD_F128, "_Qp_add");
1531 setLibcallName(RTLIB::SUB_F128, "_Qp_sub");
1532 setLibcallName(RTLIB::MUL_F128, "_Qp_mul");
1533 setLibcallName(RTLIB::DIV_F128, "_Qp_div");
1534 setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt");
1535 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi");
1536 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui");
1537 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq");
1538 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq");
1539 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox");
1540 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux");
1541 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq");
1542 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq");
1543 setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq");
1544 setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq");
1545 setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos");
1546 setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod");
1548 setLibcallName(RTLIB::ADD_F128, "_Q_add");
1549 setLibcallName(RTLIB::SUB_F128, "_Q_sub");
1550 setLibcallName(RTLIB::MUL_F128, "_Q_mul");
1551 setLibcallName(RTLIB::DIV_F128, "_Q_div");
1552 setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt");
1553 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi");
1554 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou");
1555 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq");
1556 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq");
1557 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1558 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1559 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1560 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1561 setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq");
1562 setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq");
1563 setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos");
1564 setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod");
1568 setMinFunctionAlignment(2);
1570 computeRegisterProperties();
1573 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
1576 case SPISD::CMPICC: return "SPISD::CMPICC";
1577 case SPISD::CMPFCC: return "SPISD::CMPFCC";
1578 case SPISD::BRICC: return "SPISD::BRICC";
1579 case SPISD::BRXCC: return "SPISD::BRXCC";
1580 case SPISD::BRFCC: return "SPISD::BRFCC";
1581 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
1582 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC";
1583 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
1584 case SPISD::Hi: return "SPISD::Hi";
1585 case SPISD::Lo: return "SPISD::Lo";
1586 case SPISD::FTOI: return "SPISD::FTOI";
1587 case SPISD::ITOF: return "SPISD::ITOF";
1588 case SPISD::FTOX: return "SPISD::FTOX";
1589 case SPISD::XTOF: return "SPISD::XTOF";
1590 case SPISD::CALL: return "SPISD::CALL";
1591 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
1592 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
1593 case SPISD::FLUSHW: return "SPISD::FLUSHW";
1594 case SPISD::TLS_ADD: return "SPISD::TLS_ADD";
1595 case SPISD::TLS_LD: return "SPISD::TLS_LD";
1596 case SPISD::TLS_CALL: return "SPISD::TLS_CALL";
1600 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
1601 /// be zero. Op is expected to be a target specific node. Used by DAG
1603 void SparcTargetLowering::computeMaskedBitsForTargetNode
1607 const SelectionDAG &DAG,
1608 unsigned Depth) const {
1609 APInt KnownZero2, KnownOne2;
1610 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
1612 switch (Op.getOpcode()) {
1614 case SPISD::SELECT_ICC:
1615 case SPISD::SELECT_XCC:
1616 case SPISD::SELECT_FCC:
1617 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
1618 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
1619 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1620 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1622 // Only known if known in both the LHS and RHS.
1623 KnownOne &= KnownOne2;
1624 KnownZero &= KnownZero2;
1629 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1630 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1631 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1632 ISD::CondCode CC, unsigned &SPCC) {
1633 if (isa<ConstantSDNode>(RHS) &&
1634 cast<ConstantSDNode>(RHS)->isNullValue() &&
1636 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
1637 LHS.getOpcode() == SPISD::SELECT_XCC) &&
1638 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
1639 (LHS.getOpcode() == SPISD::SELECT_FCC &&
1640 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
1641 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1642 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1643 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() &&
1644 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) {
1645 SDValue CMPCC = LHS.getOperand(3);
1646 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1647 LHS = CMPCC.getOperand(0);
1648 RHS = CMPCC.getOperand(1);
1652 // Convert to a target node and set target flags.
1653 SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
1654 SelectionDAG &DAG) const {
1655 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
1656 return DAG.getTargetGlobalAddress(GA->getGlobal(),
1658 GA->getValueType(0),
1659 GA->getOffset(), TF);
1661 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
1662 return DAG.getTargetConstantPool(CP->getConstVal(),
1663 CP->getValueType(0),
1665 CP->getOffset(), TF);
1667 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
1668 return DAG.getTargetBlockAddress(BA->getBlockAddress(),
1673 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
1674 return DAG.getTargetExternalSymbol(ES->getSymbol(),
1675 ES->getValueType(0), TF);
1677 llvm_unreachable("Unhandled address SDNode");
1680 // Split Op into high and low parts according to HiTF and LoTF.
1681 // Return an ADD node combining the parts.
1682 SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
1683 unsigned HiTF, unsigned LoTF,
1684 SelectionDAG &DAG) const {
1686 EVT VT = Op.getValueType();
1687 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
1688 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
1689 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1692 // Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
1693 // or ExternalSymbol SDNode.
1694 SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
1696 EVT VT = getPointerTy();
1698 // Handle PIC mode first.
1699 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1700 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
1701 SDValue HiLo = makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
1702 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
1703 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo);
1704 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1705 // function has calls.
1706 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1707 MFI->setHasCalls(true);
1708 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
1709 MachinePointerInfo::getGOT(), false, false, false, 0);
1712 // This is one of the absolute code models.
1713 switch(getTargetMachine().getCodeModel()) {
1715 llvm_unreachable("Unsupported absolute code model");
1716 case CodeModel::JITDefault:
1717 case CodeModel::Small:
1719 return makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
1720 case CodeModel::Medium: {
1722 SDValue H44 = makeHiLoPair(Op, SPII::MO_H44, SPII::MO_M44, DAG);
1723 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32));
1724 SDValue L44 = withTargetFlags(Op, SPII::MO_L44, DAG);
1725 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
1726 return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
1728 case CodeModel::Large: {
1730 SDValue Hi = makeHiLoPair(Op, SPII::MO_HH, SPII::MO_HM, DAG);
1731 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32));
1732 SDValue Lo = makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
1733 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1738 SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
1739 SelectionDAG &DAG) const {
1740 return makeAddress(Op, DAG);
1743 SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
1744 SelectionDAG &DAG) const {
1745 return makeAddress(Op, DAG);
1748 SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
1749 SelectionDAG &DAG) const {
1750 return makeAddress(Op, DAG);
1753 SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1754 SelectionDAG &DAG) const {
1756 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1758 const GlobalValue *GV = GA->getGlobal();
1759 EVT PtrVT = getPointerTy();
1761 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1763 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1764 unsigned HiTF = ((model == TLSModel::GeneralDynamic)? SPII::MO_TLS_GD_HI22
1765 : SPII::MO_TLS_LDM_HI22);
1766 unsigned LoTF = ((model == TLSModel::GeneralDynamic)? SPII::MO_TLS_GD_LO10
1767 : SPII::MO_TLS_LDM_LO10);
1768 unsigned addTF = ((model == TLSModel::GeneralDynamic)? SPII::MO_TLS_GD_ADD
1769 : SPII::MO_TLS_LDM_ADD);
1770 unsigned callTF = ((model == TLSModel::GeneralDynamic)? SPII::MO_TLS_GD_CALL
1771 : SPII::MO_TLS_LDM_CALL);
1773 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
1774 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
1775 SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo,
1776 withTargetFlags(Op, addTF, DAG));
1778 SDValue Chain = DAG.getEntryNode();
1781 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, true), DL);
1782 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
1783 InFlag = Chain.getValue(1);
1784 SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
1785 SDValue Symbol = withTargetFlags(Op, callTF, DAG);
1787 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1788 SmallVector<SDValue, 4> Ops;
1789 Ops.push_back(Chain);
1790 Ops.push_back(Callee);
1791 Ops.push_back(Symbol);
1792 Ops.push_back(DAG.getRegister(SP::O0, PtrVT));
1793 const uint32_t *Mask = getTargetMachine()
1794 .getRegisterInfo()->getCallPreservedMask(CallingConv::C);
1795 assert(Mask && "Missing call preserved mask for calling convention");
1796 Ops.push_back(DAG.getRegisterMask(Mask));
1797 Ops.push_back(InFlag);
1798 Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, &Ops[0], Ops.size());
1799 InFlag = Chain.getValue(1);
1800 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, true),
1801 DAG.getIntPtrConstant(0, true), InFlag, DL);
1802 InFlag = Chain.getValue(1);
1803 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag);
1805 if (model != TLSModel::LocalDynamic)
1808 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
1809 withTargetFlags(Op, SPII::MO_TLS_LDO_HIX22, DAG));
1810 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
1811 withTargetFlags(Op, SPII::MO_TLS_LDO_LOX10, DAG));
1812 HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
1813 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo,
1814 withTargetFlags(Op, SPII::MO_TLS_LDO_ADD, DAG));
1817 if (model == TLSModel::InitialExec) {
1818 unsigned ldTF = ((PtrVT == MVT::i64)? SPII::MO_TLS_IE_LDX
1819 : SPII::MO_TLS_IE_LD);
1821 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
1823 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1824 // function has calls.
1825 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1826 MFI->setHasCalls(true);
1828 SDValue TGA = makeHiLoPair(Op,
1829 SPII::MO_TLS_IE_HI22, SPII::MO_TLS_IE_LO10, DAG);
1830 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA);
1831 SDValue Offset = DAG.getNode(SPISD::TLS_LD,
1833 withTargetFlags(Op, ldTF, DAG));
1834 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT,
1835 DAG.getRegister(SP::G7, PtrVT), Offset,
1836 withTargetFlags(Op, SPII::MO_TLS_IE_ADD, DAG));
1839 assert(model == TLSModel::LocalExec);
1840 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
1841 withTargetFlags(Op, SPII::MO_TLS_LE_HIX22, DAG));
1842 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
1843 withTargetFlags(Op, SPII::MO_TLS_LE_LOX10, DAG));
1844 SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
1846 return DAG.getNode(ISD::ADD, DL, PtrVT,
1847 DAG.getRegister(SP::G7, PtrVT), Offset);
1851 SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args,
1852 SDValue Arg, SDLoc DL,
1853 SelectionDAG &DAG) const {
1854 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1855 EVT ArgVT = Arg.getValueType();
1856 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1862 if (ArgTy->isFP128Ty()) {
1863 // Create a stack object and pass the pointer to the library function.
1864 int FI = MFI->CreateStackObject(16, 8, false);
1865 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
1866 Chain = DAG.getStore(Chain,
1870 MachinePointerInfo(),
1876 Entry.Ty = PointerType::getUnqual(ArgTy);
1878 Args.push_back(Entry);
1883 SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
1884 const char *LibFuncName,
1885 unsigned numArgs) const {
1889 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1891 SDValue Callee = DAG.getExternalSymbol(LibFuncName, getPointerTy());
1892 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
1893 Type *RetTyABI = RetTy;
1894 SDValue Chain = DAG.getEntryNode();
1897 if (RetTy->isFP128Ty()) {
1898 // Create a Stack Object to receive the return value of type f128.
1900 int RetFI = MFI->CreateStackObject(16, 8, false);
1901 RetPtr = DAG.getFrameIndex(RetFI, getPointerTy());
1902 Entry.Node = RetPtr;
1903 Entry.Ty = PointerType::getUnqual(RetTy);
1904 if (!Subtarget->is64Bit())
1905 Entry.isSRet = true;
1906 Entry.isReturned = false;
1907 Args.push_back(Entry);
1908 RetTyABI = Type::getVoidTy(*DAG.getContext());
1911 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
1912 for (unsigned i = 0, e = numArgs; i != e; ++i) {
1913 Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
1916 CallLoweringInfo CLI(Chain,
1918 false, false, false, false,
1921 Callee, Args, DAG, SDLoc(Op));
1922 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
1924 // chain is in second result.
1925 if (RetTyABI == RetTy)
1926 return CallInfo.first;
1928 assert (RetTy->isFP128Ty() && "Unexpected return type!");
1930 Chain = CallInfo.second;
1932 // Load RetPtr to get the return value.
1933 return DAG.getLoad(Op.getValueType(),
1937 MachinePointerInfo(),
1938 false, false, false, 8);
1942 SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
1945 SelectionDAG &DAG) const {
1947 const char *LibCall = 0;
1948 bool is64Bit = Subtarget->is64Bit();
1950 default: llvm_unreachable("Unhandled conditional code!");
1951 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
1952 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
1953 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
1954 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
1955 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
1956 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
1964 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
1967 SDValue Callee = DAG.getExternalSymbol(LibCall, getPointerTy());
1968 Type *RetTy = Type::getInt32Ty(*DAG.getContext());
1970 SDValue Chain = DAG.getEntryNode();
1971 Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG);
1972 Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG);
1975 CallLoweringInfo CLI(Chain,
1977 false, false, false, false,
1980 Callee, Args, DAG, DL);
1982 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
1984 // result is in first, and chain is in second result.
1985 SDValue Result = CallInfo.first;
1989 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
1990 SPCC = SPCC::ICC_NE;
1991 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
1993 case SPCC::FCC_UL : {
1994 SDValue Mask = DAG.getTargetConstant(1, Result.getValueType());
1995 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
1996 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
1997 SPCC = SPCC::ICC_NE;
1998 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2000 case SPCC::FCC_ULE: {
2001 SDValue RHS = DAG.getTargetConstant(2, Result.getValueType());
2002 SPCC = SPCC::ICC_NE;
2003 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2005 case SPCC::FCC_UG : {
2006 SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
2008 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2010 case SPCC::FCC_UGE: {
2011 SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
2012 SPCC = SPCC::ICC_NE;
2013 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2016 case SPCC::FCC_U : {
2017 SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
2019 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2021 case SPCC::FCC_O : {
2022 SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
2023 SPCC = SPCC::ICC_NE;
2024 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2026 case SPCC::FCC_LG : {
2027 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType());
2028 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2029 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
2030 SPCC = SPCC::ICC_NE;
2031 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2033 case SPCC::FCC_UE : {
2034 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType());
2035 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2036 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
2038 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2044 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
2045 const SparcTargetLowering &TLI) {
2047 if (Op.getOperand(0).getValueType() == MVT::f64)
2048 return TLI.LowerF128Op(Op, DAG,
2049 TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1);
2051 if (Op.getOperand(0).getValueType() == MVT::f32)
2052 return TLI.LowerF128Op(Op, DAG,
2053 TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1);
2055 llvm_unreachable("fpextend with non-float operand!");
2056 return SDValue(0, 0);
2060 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
2061 const SparcTargetLowering &TLI) {
2062 // FP_ROUND on f64 and f32 are legal.
2063 if (Op.getOperand(0).getValueType() != MVT::f128)
2066 if (Op.getValueType() == MVT::f64)
2067 return TLI.LowerF128Op(Op, DAG,
2068 TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1);
2069 if (Op.getValueType() == MVT::f32)
2070 return TLI.LowerF128Op(Op, DAG,
2071 TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1);
2073 llvm_unreachable("fpround to non-float!");
2074 return SDValue(0, 0);
2077 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2078 const SparcTargetLowering &TLI,
2081 EVT VT = Op.getValueType();
2082 assert(VT == MVT::i32 || VT == MVT::i64);
2084 // Expand f128 operations to fp128 abi calls.
2085 if (Op.getOperand(0).getValueType() == MVT::f128
2086 && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2087 const char *libName = TLI.getLibcallName(VT == MVT::i32
2088 ? RTLIB::FPTOSINT_F128_I32
2089 : RTLIB::FPTOSINT_F128_I64);
2090 return TLI.LowerF128Op(Op, DAG, libName, 1);
2093 // Expand if the resulting type is illegal.
2094 if (!TLI.isTypeLegal(VT))
2095 return SDValue(0, 0);
2097 // Otherwise, Convert the fp value to integer in an FP register.
2099 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
2101 Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0));
2103 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
2106 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2107 const SparcTargetLowering &TLI,
2110 EVT OpVT = Op.getOperand(0).getValueType();
2111 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2113 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2115 // Expand f128 operations to fp128 ABI calls.
2116 if (Op.getValueType() == MVT::f128
2117 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) {
2118 const char *libName = TLI.getLibcallName(OpVT == MVT::i32
2119 ? RTLIB::SINTTOFP_I32_F128
2120 : RTLIB::SINTTOFP_I64_F128);
2121 return TLI.LowerF128Op(Op, DAG, libName, 1);
2124 // Expand if the operand type is illegal.
2125 if (!TLI.isTypeLegal(OpVT))
2126 return SDValue(0, 0);
2128 // Otherwise, Convert the int value to FP in an FP register.
2129 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
2130 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2131 return DAG.getNode(opcode, dl, Op.getValueType(), Tmp);
2134 static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
2135 const SparcTargetLowering &TLI,
2138 EVT VT = Op.getValueType();
2140 // Expand if it does not involve f128 or the target has support for
2141 // quad floating point instructions and the resulting type is legal.
2142 if (Op.getOperand(0).getValueType() != MVT::f128 ||
2143 (hasHardQuad && TLI.isTypeLegal(VT)))
2144 return SDValue(0, 0);
2146 assert(VT == MVT::i32 || VT == MVT::i64);
2148 return TLI.LowerF128Op(Op, DAG,
2149 TLI.getLibcallName(VT == MVT::i32
2150 ? RTLIB::FPTOUINT_F128_I32
2151 : RTLIB::FPTOUINT_F128_I64),
2155 static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2156 const SparcTargetLowering &TLI,
2159 EVT OpVT = Op.getOperand(0).getValueType();
2160 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2162 // Expand if it does not involve f128 or the target has support for
2163 // quad floating point instructions and the operand type is legal.
2164 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT)))
2165 return SDValue(0, 0);
2167 return TLI.LowerF128Op(Op, DAG,
2168 TLI.getLibcallName(OpVT == MVT::i32
2169 ? RTLIB::UINTTOFP_I32_F128
2170 : RTLIB::UINTTOFP_I64_F128),
2174 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
2175 const SparcTargetLowering &TLI,
2177 SDValue Chain = Op.getOperand(0);
2178 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2179 SDValue LHS = Op.getOperand(2);
2180 SDValue RHS = Op.getOperand(3);
2181 SDValue Dest = Op.getOperand(4);
2183 unsigned Opc, SPCC = ~0U;
2185 // If this is a br_cc of a "setcc", and if the setcc got lowered into
2186 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2187 LookThroughSetCC(LHS, RHS, CC, SPCC);
2189 // Get the condition flag.
2190 SDValue CompareFlag;
2191 if (LHS.getValueType().isInteger()) {
2192 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2193 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2194 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2195 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
2197 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2198 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2199 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2202 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2203 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2207 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
2208 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
2211 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2212 const SparcTargetLowering &TLI,
2214 SDValue LHS = Op.getOperand(0);
2215 SDValue RHS = Op.getOperand(1);
2216 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2217 SDValue TrueVal = Op.getOperand(2);
2218 SDValue FalseVal = Op.getOperand(3);
2220 unsigned Opc, SPCC = ~0U;
2222 // If this is a select_cc of a "setcc", and if the setcc got lowered into
2223 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2224 LookThroughSetCC(LHS, RHS, CC, SPCC);
2226 SDValue CompareFlag;
2227 if (LHS.getValueType().isInteger()) {
2228 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2229 Opc = LHS.getValueType() == MVT::i32 ?
2230 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
2231 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2233 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2234 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2235 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2236 Opc = SPISD::SELECT_ICC;
2238 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2239 Opc = SPISD::SELECT_FCC;
2240 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2243 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2244 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
2247 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
2248 const SparcTargetLowering &TLI) {
2249 MachineFunction &MF = DAG.getMachineFunction();
2250 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
2252 // Need frame address to find the address of VarArgsFrameIndex.
2253 MF.getFrameInfo()->setFrameAddressIsTaken(true);
2255 // vastart just stores the address of the VarArgsFrameIndex slot into the
2256 // memory location argument.
2259 DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(),
2260 DAG.getRegister(SP::I6, TLI.getPointerTy()),
2261 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset()));
2262 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2263 return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
2264 MachinePointerInfo(SV), false, false, 0);
2267 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
2268 SDNode *Node = Op.getNode();
2269 EVT VT = Node->getValueType(0);
2270 SDValue InChain = Node->getOperand(0);
2271 SDValue VAListPtr = Node->getOperand(1);
2272 EVT PtrVT = VAListPtr.getValueType();
2273 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2275 SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr,
2276 MachinePointerInfo(SV), false, false, false, 0);
2277 // Increment the pointer, VAList, to the next vaarg.
2278 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
2279 DAG.getIntPtrConstant(VT.getSizeInBits()/8));
2280 // Store the incremented VAList to the legalized pointer.
2281 InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr,
2282 VAListPtr, MachinePointerInfo(SV), false, false, 0);
2283 // Load the actual argument out of the pointer VAList.
2284 // We can't count on greater alignment than the word size.
2285 return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
2286 false, false, false,
2287 std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8);
2290 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
2291 SDValue Chain = Op.getOperand(0); // Legalize the chain.
2292 SDValue Size = Op.getOperand(1); // Legalize the size.
2295 unsigned SPReg = SP::O6;
2296 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
2297 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value
2298 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
2300 // The resultant pointer is actually 16 words from the bottom of the stack,
2301 // to provide a register spill area.
2302 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
2303 DAG.getConstant(96, MVT::i32));
2304 SDValue Ops[2] = { NewVal, Chain };
2305 return DAG.getMergeValues(Ops, 2, dl);
2309 static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
2311 SDValue Chain = DAG.getNode(SPISD::FLUSHW,
2312 dl, MVT::Other, DAG.getEntryNode());
2316 static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
2317 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2318 MFI->setFrameAddressIsTaken(true);
2320 EVT VT = Op.getValueType();
2322 unsigned FrameReg = SP::I6;
2324 uint64_t depth = Op.getConstantOperandVal(0);
2328 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2330 // flush first to make sure the windowed registers' values are in stack
2331 SDValue Chain = getFLUSHW(Op, DAG);
2332 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
2334 for (uint64_t i = 0; i != depth; ++i) {
2335 SDValue Ptr = DAG.getNode(ISD::ADD,
2337 FrameAddr, DAG.getIntPtrConstant(56));
2338 FrameAddr = DAG.getLoad(MVT::i32, dl,
2341 MachinePointerInfo(), false, false, false, 0);
2347 static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
2348 const SparcTargetLowering &TLI) {
2349 MachineFunction &MF = DAG.getMachineFunction();
2350 MachineFrameInfo *MFI = MF.getFrameInfo();
2351 MFI->setReturnAddressIsTaken(true);
2353 EVT VT = Op.getValueType();
2355 uint64_t depth = Op.getConstantOperandVal(0);
2359 unsigned RetReg = MF.addLiveIn(SP::I7,
2360 TLI.getRegClassFor(TLI.getPointerTy()));
2361 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
2363 // Need frame address to find return address of the caller.
2364 MFI->setFrameAddressIsTaken(true);
2366 // flush first to make sure the windowed registers' values are in stack
2367 SDValue Chain = getFLUSHW(Op, DAG);
2368 RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT);
2370 for (uint64_t i = 0; i != depth; ++i) {
2371 SDValue Ptr = DAG.getNode(ISD::ADD,
2374 DAG.getIntPtrConstant((i == depth-1)?60:56));
2375 RetAddr = DAG.getLoad(MVT::i32, dl,
2378 MachinePointerInfo(), false, false, false, 0);
2384 static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode)
2388 assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2389 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2391 // Lower fneg/fabs on f64 to fneg/fabs on f32.
2392 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2393 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2395 SDValue SrcReg64 = Op.getOperand(0);
2396 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2398 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2401 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
2403 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2405 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
2407 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
2412 // Lower a f128 load into two f64 loads.
2413 static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
2416 LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
2417 assert(LdNode && LdNode->getOffset().getOpcode() == ISD::UNDEF
2418 && "Unexpected node type");
2420 unsigned alignment = LdNode->getAlignment();
2424 SDValue Hi64 = DAG.getLoad(MVT::f64,
2427 LdNode->getBasePtr(),
2428 LdNode->getPointerInfo(),
2429 false, false, false, alignment);
2430 EVT addrVT = LdNode->getBasePtr().getValueType();
2431 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2432 LdNode->getBasePtr(),
2433 DAG.getConstant(8, addrVT));
2434 SDValue Lo64 = DAG.getLoad(MVT::f64,
2438 LdNode->getPointerInfo(),
2439 false, false, false, alignment);
2441 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
2442 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
2444 SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2446 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2448 SDValue(InFP128, 0),
2451 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2453 SDValue(InFP128, 0),
2456 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
2457 SDValue(Lo64.getNode(), 1) };
2458 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2460 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2461 return DAG.getMergeValues(Ops, 2, dl);
2464 // Lower a f128 store into two f64 stores.
2465 static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
2467 StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
2468 assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF
2469 && "Unexpected node type");
2470 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
2471 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
2473 SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2478 SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2484 unsigned alignment = StNode->getAlignment();
2488 SDValue OutChains[2];
2489 OutChains[0] = DAG.getStore(StNode->getChain(),
2492 StNode->getBasePtr(),
2493 MachinePointerInfo(),
2494 false, false, alignment);
2495 EVT addrVT = StNode->getBasePtr().getValueType();
2496 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2497 StNode->getBasePtr(),
2498 DAG.getConstant(8, addrVT));
2499 OutChains[1] = DAG.getStore(StNode->getChain(),
2503 MachinePointerInfo(),
2504 false, false, alignment);
2505 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2509 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG,
2510 const SparcTargetLowering &TLI,
2512 if (Op.getValueType() == MVT::f64)
2513 return LowerF64Op(Op, DAG, ISD::FNEG);
2514 if (Op.getValueType() == MVT::f128)
2515 return TLI.LowerF128Op(Op, DAG, ((is64Bit) ? "_Qp_neg" : "_Q_neg"), 1);
2519 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
2520 if (Op.getValueType() == MVT::f64)
2521 return LowerF64Op(Op, DAG, ISD::FABS);
2522 if (Op.getValueType() != MVT::f128)
2525 // Lower fabs on f128 to fabs on f64
2526 // fabs f128 => fabs f64:sub_even64, fmov f64:sub_odd64
2529 SDValue SrcReg128 = Op.getOperand(0);
2530 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
2532 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
2535 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
2537 Hi64 = LowerF64Op(Hi64, DAG, ISD::FABS);
2539 SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2541 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
2543 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
2548 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
2550 if (Op.getValueType() != MVT::i64)
2554 SDValue Src1 = Op.getOperand(0);
2555 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
2556 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
2557 DAG.getConstant(32, MVT::i64));
2558 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi);
2560 SDValue Src2 = Op.getOperand(1);
2561 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2);
2562 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
2563 DAG.getConstant(32, MVT::i64));
2564 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi);
2567 bool hasChain = false;
2568 unsigned hiOpc = Op.getOpcode();
2569 switch (Op.getOpcode()) {
2570 default: llvm_unreachable("Invalid opcode");
2571 case ISD::ADDC: hiOpc = ISD::ADDE; break;
2572 case ISD::ADDE: hasChain = true; break;
2573 case ISD::SUBC: hiOpc = ISD::SUBE; break;
2574 case ISD::SUBE: hasChain = true; break;
2577 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue);
2579 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
2582 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
2584 SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1));
2585 SDValue Carry = Hi.getValue(1);
2587 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
2588 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
2589 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
2590 DAG.getConstant(32, MVT::i64));
2592 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
2593 SDValue Ops[2] = { Dst, Carry };
2594 return DAG.getMergeValues(Ops, 2, dl);
2597 SDValue SparcTargetLowering::
2598 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2600 bool hasHardQuad = Subtarget->hasHardQuad();
2601 bool is64Bit = Subtarget->is64Bit();
2602 bool isV9 = Subtarget->isV9();
2604 switch (Op.getOpcode()) {
2605 default: llvm_unreachable("Should not custom lower this!");
2607 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this);
2608 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2609 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2610 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2611 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2612 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2613 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this,
2615 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this,
2617 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this,
2619 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this,
2621 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this,
2623 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this,
2625 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
2626 case ISD::VAARG: return LowerVAARG(Op, DAG);
2627 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2629 case ISD::LOAD: return LowerF128Load(Op, DAG);
2630 case ISD::STORE: return LowerF128Store(Op, DAG);
2631 case ISD::FADD: return LowerF128Op(Op, DAG,
2632 getLibcallName(RTLIB::ADD_F128), 2);
2633 case ISD::FSUB: return LowerF128Op(Op, DAG,
2634 getLibcallName(RTLIB::SUB_F128), 2);
2635 case ISD::FMUL: return LowerF128Op(Op, DAG,
2636 getLibcallName(RTLIB::MUL_F128), 2);
2637 case ISD::FDIV: return LowerF128Op(Op, DAG,
2638 getLibcallName(RTLIB::DIV_F128), 2);
2639 case ISD::FSQRT: return LowerF128Op(Op, DAG,
2640 getLibcallName(RTLIB::SQRT_F128),1);
2641 case ISD::FNEG: return LowerFNEG(Op, DAG, *this, is64Bit);
2642 case ISD::FABS: return LowerFABS(Op, DAG, isV9);
2643 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this);
2644 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
2648 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
2653 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2654 MachineBasicBlock *BB) const {
2655 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
2658 DebugLoc dl = MI->getDebugLoc();
2659 // Figure out the conditional branch opcode to use for this select_cc.
2660 switch (MI->getOpcode()) {
2661 default: llvm_unreachable("Unknown SELECT_CC!");
2662 case SP::SELECT_CC_Int_ICC:
2663 case SP::SELECT_CC_FP_ICC:
2664 case SP::SELECT_CC_DFP_ICC:
2665 case SP::SELECT_CC_QFP_ICC:
2666 BROpcode = SP::BCOND;
2668 case SP::SELECT_CC_Int_FCC:
2669 case SP::SELECT_CC_FP_FCC:
2670 case SP::SELECT_CC_DFP_FCC:
2671 case SP::SELECT_CC_QFP_FCC:
2672 BROpcode = SP::FBCOND;
2676 CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
2678 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2679 // control-flow pattern. The incoming instruction knows the destination vreg
2680 // to set, the condition code register to branch on, the true/false values to
2681 // select between, and a branch opcode to use.
2682 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2683 MachineFunction::iterator It = BB;
2690 // fallthrough --> copy0MBB
2691 MachineBasicBlock *thisMBB = BB;
2692 MachineFunction *F = BB->getParent();
2693 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2694 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
2695 F->insert(It, copy0MBB);
2696 F->insert(It, sinkMBB);
2698 // Transfer the remainder of BB and its successor edges to sinkMBB.
2699 sinkMBB->splice(sinkMBB->begin(), BB,
2700 llvm::next(MachineBasicBlock::iterator(MI)),
2702 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
2704 // Add the true and fallthrough blocks as its successors.
2705 BB->addSuccessor(copy0MBB);
2706 BB->addSuccessor(sinkMBB);
2708 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
2711 // %FalseValue = ...
2712 // # fallthrough to sinkMBB
2715 // Update machine-CFG edges
2716 BB->addSuccessor(sinkMBB);
2719 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2722 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
2723 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
2724 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
2726 MI->eraseFromParent(); // The pseudo instruction is gone now.
2730 //===----------------------------------------------------------------------===//
2731 // Sparc Inline Assembly Support
2732 //===----------------------------------------------------------------------===//
2734 /// getConstraintType - Given a constraint letter, return the type of
2735 /// constraint it is for this target.
2736 SparcTargetLowering::ConstraintType
2737 SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
2738 if (Constraint.size() == 1) {
2739 switch (Constraint[0]) {
2741 case 'r': return C_RegisterClass;
2745 return TargetLowering::getConstraintType(Constraint);
2748 std::pair<unsigned, const TargetRegisterClass*>
2749 SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
2751 if (Constraint.size() == 1) {
2752 switch (Constraint[0]) {
2754 return std::make_pair(0U, &SP::IntRegsRegClass);
2758 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2762 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
2763 // The Sparc target isn't yet aware of offsets.
2767 void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
2768 SmallVectorImpl<SDValue>& Results,
2769 SelectionDAG &DAG) const {
2773 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
2775 switch (N->getOpcode()) {
2777 llvm_unreachable("Do not know how to custom type legalize this operation!");
2779 case ISD::FP_TO_SINT:
2780 case ISD::FP_TO_UINT:
2781 // Custom lower only if it involves f128 or i64.
2782 if (N->getOperand(0).getValueType() != MVT::f128
2783 || N->getValueType(0) != MVT::i64)
2785 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
2786 ? RTLIB::FPTOSINT_F128_I64
2787 : RTLIB::FPTOUINT_F128_I64);
2789 Results.push_back(LowerF128Op(SDValue(N, 0),
2791 getLibcallName(libCall),
2795 case ISD::SINT_TO_FP:
2796 case ISD::UINT_TO_FP:
2797 // Custom lower only if it involves f128 or i64.
2798 if (N->getValueType(0) != MVT::f128
2799 || N->getOperand(0).getValueType() != MVT::i64)
2802 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
2803 ? RTLIB::SINTTOFP_I64_F128
2804 : RTLIB::UINTTOFP_I64_F128);
2806 Results.push_back(LowerF128Op(SDValue(N, 0),
2808 getLibcallName(libCall),