1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "SparcISelLowering.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcRegisterInfo.h"
18 #include "SparcTargetMachine.h"
19 #include "MCTargetDesc/SparcBaseInfo.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Module.h"
30 #include "llvm/Support/ErrorHandling.h"
34 //===----------------------------------------------------------------------===//
35 // Calling Convention Implementation
36 //===----------------------------------------------------------------------===//
38 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
39 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
40 ISD::ArgFlagsTy &ArgFlags, CCState &State)
42 assert (ArgFlags.isSRet());
44 // Assign SRet argument.
45 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
51 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
52 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
53 ISD::ArgFlagsTy &ArgFlags, CCState &State)
55 static const uint16_t RegList[] = {
56 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
58 // Try to get first reg.
59 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
60 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
62 // Assign whole thing in stack.
63 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
64 State.AllocateStack(8,4),
69 // Try to get second reg.
70 if (unsigned Reg = State.AllocateReg(RegList, 6))
71 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
73 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
74 State.AllocateStack(4,4),
79 // Allocate a full-sized argument for the 64-bit ABI.
80 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
81 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
82 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
83 assert((LocVT == MVT::f32 || LocVT.getSizeInBits() == 64) &&
84 "Can't handle non-64 bits locations");
86 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
87 unsigned Offset = State.AllocateStack(8, 8);
90 if (LocVT == MVT::i64 && Offset < 6*8)
91 // Promote integers to %i0-%i5.
92 Reg = SP::I0 + Offset/8;
93 else if (LocVT == MVT::f64 && Offset < 16*8)
94 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
95 Reg = SP::D0 + Offset/8;
96 else if (LocVT == MVT::f32 && Offset < 16*8)
97 // Promote floats to %f1, %f3, ...
98 Reg = SP::F1 + Offset/4;
100 // Promote to register when possible, otherwise use the stack slot.
102 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
106 // This argument goes on the stack in an 8-byte slot.
107 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
108 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
109 if (LocVT == MVT::f32)
112 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
116 // Allocate a half-sized argument for the 64-bit ABI.
118 // This is used when passing { float, int } structs by value in registers.
119 static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT,
120 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
121 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
122 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
123 unsigned Offset = State.AllocateStack(4, 4);
125 if (LocVT == MVT::f32 && Offset < 16*8) {
126 // Promote floats to %f0-%f31.
127 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
132 if (LocVT == MVT::i32 && Offset < 6*8) {
133 // Promote integers to %i0-%i5, using half the register.
134 unsigned Reg = SP::I0 + Offset/8;
136 LocInfo = CCValAssign::AExt;
138 // Set the Custom bit if this i32 goes in the high bits of a register.
140 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
143 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
147 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
151 #include "SparcGenCallingConv.inc"
153 // The calling conventions in SparcCallingConv.td are described in terms of the
154 // callee's register window. This function translates registers to the
155 // corresponding caller window %o register.
156 static unsigned toCallerWindow(unsigned Reg) {
157 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum");
158 if (Reg >= SP::I0 && Reg <= SP::I7)
159 return Reg - SP::I0 + SP::O0;
164 SparcTargetLowering::LowerReturn(SDValue Chain,
165 CallingConv::ID CallConv, bool IsVarArg,
166 const SmallVectorImpl<ISD::OutputArg> &Outs,
167 const SmallVectorImpl<SDValue> &OutVals,
168 SDLoc DL, SelectionDAG &DAG) const {
169 if (Subtarget->is64Bit())
170 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
171 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
175 SparcTargetLowering::LowerReturn_32(SDValue Chain,
176 CallingConv::ID CallConv, bool IsVarArg,
177 const SmallVectorImpl<ISD::OutputArg> &Outs,
178 const SmallVectorImpl<SDValue> &OutVals,
179 SDLoc DL, SelectionDAG &DAG) const {
180 MachineFunction &MF = DAG.getMachineFunction();
182 // CCValAssign - represent the assignment of the return value to locations.
183 SmallVector<CCValAssign, 16> RVLocs;
185 // CCState - Info about the registers and stack slot.
186 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
187 DAG.getTarget(), RVLocs, *DAG.getContext());
189 // Analyze return values.
190 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
193 SmallVector<SDValue, 4> RetOps(1, Chain);
194 // Make room for the return address offset.
195 RetOps.push_back(SDValue());
197 // Copy the result values into the output registers.
198 for (unsigned i = 0; i != RVLocs.size(); ++i) {
199 CCValAssign &VA = RVLocs[i];
200 assert(VA.isRegLoc() && "Can only return in registers!");
202 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(),
205 // Guarantee that all emitted copies are stuck together with flags.
206 Flag = Chain.getValue(1);
207 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
210 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
211 // If the function returns a struct, copy the SRetReturnReg to I0
212 if (MF.getFunction()->hasStructRetAttr()) {
213 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
214 unsigned Reg = SFI->getSRetReturnReg();
216 llvm_unreachable("sret virtual register not created in the entry block");
217 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
218 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
219 Flag = Chain.getValue(1);
220 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy()));
221 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
224 RetOps[0] = Chain; // Update chain.
225 RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);
227 // Add the flag if we have it.
229 RetOps.push_back(Flag);
231 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other,
232 &RetOps[0], RetOps.size());
235 // Lower return values for the 64-bit ABI.
236 // Return values are passed the exactly the same way as function arguments.
238 SparcTargetLowering::LowerReturn_64(SDValue Chain,
239 CallingConv::ID CallConv, bool IsVarArg,
240 const SmallVectorImpl<ISD::OutputArg> &Outs,
241 const SmallVectorImpl<SDValue> &OutVals,
242 SDLoc DL, SelectionDAG &DAG) const {
243 // CCValAssign - represent the assignment of the return value to locations.
244 SmallVector<CCValAssign, 16> RVLocs;
246 // CCState - Info about the registers and stack slot.
247 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
248 DAG.getTarget(), RVLocs, *DAG.getContext());
250 // Analyze return values.
251 CCInfo.AnalyzeReturn(Outs, CC_Sparc64);
254 SmallVector<SDValue, 4> RetOps(1, Chain);
256 // The second operand on the return instruction is the return address offset.
257 // The return address is always %i7+8 with the 64-bit ABI.
258 RetOps.push_back(DAG.getConstant(8, MVT::i32));
260 // Copy the result values into the output registers.
261 for (unsigned i = 0; i != RVLocs.size(); ++i) {
262 CCValAssign &VA = RVLocs[i];
263 assert(VA.isRegLoc() && "Can only return in registers!");
264 SDValue OutVal = OutVals[i];
266 // Integer return values must be sign or zero extended by the callee.
267 switch (VA.getLocInfo()) {
268 case CCValAssign::SExt:
269 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
271 case CCValAssign::ZExt:
272 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
274 case CCValAssign::AExt:
275 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
280 // The custom bit on an i32 return value indicates that it should be passed
281 // in the high bits of the register.
282 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
283 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
284 DAG.getConstant(32, MVT::i32));
286 // The next value may go in the low bits of the same register.
287 // Handle both at once.
288 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
289 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
290 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
291 // Skip the next value, it's already done.
296 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
298 // Guarantee that all emitted copies are stuck together with flags.
299 Flag = Chain.getValue(1);
300 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
303 RetOps[0] = Chain; // Update chain.
305 // Add the flag if we have it.
307 RetOps.push_back(Flag);
309 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other,
310 &RetOps[0], RetOps.size());
313 SDValue SparcTargetLowering::
314 LowerFormalArguments(SDValue Chain,
315 CallingConv::ID CallConv,
317 const SmallVectorImpl<ISD::InputArg> &Ins,
320 SmallVectorImpl<SDValue> &InVals) const {
321 if (Subtarget->is64Bit())
322 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
324 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
328 /// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
329 /// passed in either one or two GPRs, including FP values. TODO: we should
330 /// pass FP values in FP registers for fastcc functions.
331 SDValue SparcTargetLowering::
332 LowerFormalArguments_32(SDValue Chain,
333 CallingConv::ID CallConv,
335 const SmallVectorImpl<ISD::InputArg> &Ins,
338 SmallVectorImpl<SDValue> &InVals) const {
339 MachineFunction &MF = DAG.getMachineFunction();
340 MachineRegisterInfo &RegInfo = MF.getRegInfo();
341 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
343 // Assign locations to all of the incoming arguments.
344 SmallVector<CCValAssign, 16> ArgLocs;
345 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
346 getTargetMachine(), ArgLocs, *DAG.getContext());
347 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
349 const unsigned StackOffset = 92;
351 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
352 CCValAssign &VA = ArgLocs[i];
354 if (i == 0 && Ins[i].Flags.isSRet()) {
355 // Get SRet from [%fp+64].
356 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true);
357 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
358 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
359 MachinePointerInfo(),
360 false, false, false, 0);
361 InVals.push_back(Arg);
366 if (VA.needsCustom()) {
367 assert(VA.getLocVT() == MVT::f64);
368 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
369 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
370 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
373 CCValAssign &NextVA = ArgLocs[++i];
376 if (NextVA.isMemLoc()) {
377 int FrameIdx = MF.getFrameInfo()->
378 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
379 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
380 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
381 MachinePointerInfo(),
382 false, false, false, 0);
384 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
385 &SP::IntRegsRegClass);
386 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
389 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
390 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
391 InVals.push_back(WholeValue);
394 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
395 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
396 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
397 if (VA.getLocVT() == MVT::f32)
398 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
399 else if (VA.getLocVT() != MVT::i32) {
400 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
401 DAG.getValueType(VA.getLocVT()));
402 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
404 InVals.push_back(Arg);
408 assert(VA.isMemLoc());
410 unsigned Offset = VA.getLocMemOffset()+StackOffset;
412 if (VA.needsCustom()) {
413 assert(VA.getValVT() == MVT::f64);
414 // If it is double-word aligned, just load.
415 if (Offset % 8 == 0) {
416 int FI = MF.getFrameInfo()->CreateFixedObject(8,
419 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
420 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
421 MachinePointerInfo(),
422 false,false, false, 0);
423 InVals.push_back(Load);
427 int FI = MF.getFrameInfo()->CreateFixedObject(4,
430 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
431 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
432 MachinePointerInfo(),
433 false, false, false, 0);
434 int FI2 = MF.getFrameInfo()->CreateFixedObject(4,
437 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy());
439 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2,
440 MachinePointerInfo(),
441 false, false, false, 0);
444 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
445 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
446 InVals.push_back(WholeValue);
450 int FI = MF.getFrameInfo()->CreateFixedObject(4,
453 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
455 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
456 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
457 MachinePointerInfo(),
458 false, false, false, 0);
460 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
461 // Sparc is big endian, so add an offset based on the ObjectVT.
462 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
463 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
464 DAG.getConstant(Offset, MVT::i32));
465 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
466 MachinePointerInfo(),
467 VA.getValVT(), false, false,0);
468 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
470 InVals.push_back(Load);
473 if (MF.getFunction()->hasStructRetAttr()) {
474 // Copy the SRet Argument to SRetReturnReg.
475 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
476 unsigned Reg = SFI->getSRetReturnReg();
478 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
479 SFI->setSRetReturnReg(Reg);
481 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
482 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
485 // Store remaining ArgRegs to the stack if this is a varargs function.
487 static const uint16_t ArgRegs[] = {
488 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
490 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6);
491 const uint16_t *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
492 unsigned ArgOffset = CCInfo.getNextStackOffset();
493 if (NumAllocated == 6)
494 ArgOffset += StackOffset;
497 ArgOffset = 68+4*NumAllocated;
500 // Remember the vararg offset for the va_start implementation.
501 FuncInfo->setVarArgsFrameOffset(ArgOffset);
503 std::vector<SDValue> OutChains;
505 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
506 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
507 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
508 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
510 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
512 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
514 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr,
515 MachinePointerInfo(),
520 if (!OutChains.empty()) {
521 OutChains.push_back(Chain);
522 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
523 &OutChains[0], OutChains.size());
530 // Lower formal arguments for the 64 bit ABI.
531 SDValue SparcTargetLowering::
532 LowerFormalArguments_64(SDValue Chain,
533 CallingConv::ID CallConv,
535 const SmallVectorImpl<ISD::InputArg> &Ins,
538 SmallVectorImpl<SDValue> &InVals) const {
539 MachineFunction &MF = DAG.getMachineFunction();
541 // Analyze arguments according to CC_Sparc64.
542 SmallVector<CCValAssign, 16> ArgLocs;
543 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
544 getTargetMachine(), ArgLocs, *DAG.getContext());
545 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
547 // The argument array begins at %fp+BIAS+128, after the register save area.
548 const unsigned ArgArea = 128;
550 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
551 CCValAssign &VA = ArgLocs[i];
553 // This argument is passed in a register.
554 // All integer register arguments are promoted by the caller to i64.
556 // Create a virtual register for the promoted live-in value.
557 unsigned VReg = MF.addLiveIn(VA.getLocReg(),
558 getRegClassFor(VA.getLocVT()));
559 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
561 // Get the high bits for i32 struct elements.
562 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
563 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
564 DAG.getConstant(32, MVT::i32));
566 // The caller promoted the argument, so insert an Assert?ext SDNode so we
567 // won't promote the value again in this function.
568 switch (VA.getLocInfo()) {
569 case CCValAssign::SExt:
570 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
571 DAG.getValueType(VA.getValVT()));
573 case CCValAssign::ZExt:
574 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
575 DAG.getValueType(VA.getValVT()));
581 // Truncate the register down to the argument type.
583 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
585 InVals.push_back(Arg);
589 // The registers are exhausted. This argument was passed on the stack.
590 assert(VA.isMemLoc());
591 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
592 // beginning of the arguments area at %fp+BIAS+128.
593 unsigned Offset = VA.getLocMemOffset() + ArgArea;
594 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
595 // Adjust offset for extended arguments, SPARC is big-endian.
596 // The caller will have written the full slot with extended bytes, but we
597 // prefer our own extending loads.
599 Offset += 8 - ValSize;
600 int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true);
601 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain,
602 DAG.getFrameIndex(FI, getPointerTy()),
603 MachinePointerInfo::getFixedStack(FI),
604 false, false, false, 0));
610 // This function takes variable arguments, some of which may have been passed
611 // in registers %i0-%i5. Variable floating point arguments are never passed
612 // in floating point registers. They go on %i0-%i5 or on the stack like
613 // integer arguments.
615 // The va_start intrinsic needs to know the offset to the first variable
617 unsigned ArgOffset = CCInfo.getNextStackOffset();
618 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
619 // Skip the 128 bytes of register save area.
620 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
621 Subtarget->getStackPointerBias());
623 // Save the variable arguments that were passed in registers.
624 // The caller is required to reserve stack space for 6 arguments regardless
625 // of how many arguments were actually passed.
626 SmallVector<SDValue, 8> OutChains;
627 for (; ArgOffset < 6*8; ArgOffset += 8) {
628 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
629 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
630 int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true);
631 OutChains.push_back(DAG.getStore(Chain, DL, VArg,
632 DAG.getFrameIndex(FI, getPointerTy()),
633 MachinePointerInfo::getFixedStack(FI),
637 if (!OutChains.empty())
638 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
639 &OutChains[0], OutChains.size());
645 SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
646 SmallVectorImpl<SDValue> &InVals) const {
647 if (Subtarget->is64Bit())
648 return LowerCall_64(CLI, InVals);
649 return LowerCall_32(CLI, InVals);
652 static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
653 ImmutableCallSite *CS) {
655 return CS->hasFnAttr(Attribute::ReturnsTwice);
657 const Function *CalleeFn = 0;
658 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
659 CalleeFn = dyn_cast<Function>(G->getGlobal());
660 } else if (ExternalSymbolSDNode *E =
661 dyn_cast<ExternalSymbolSDNode>(Callee)) {
662 const Function *Fn = DAG.getMachineFunction().getFunction();
663 const Module *M = Fn->getParent();
664 const char *CalleeName = E->getSymbol();
665 CalleeFn = M->getFunction(CalleeName);
670 return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
673 // Lower a call for the 32-bit ABI.
675 SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
676 SmallVectorImpl<SDValue> &InVals) const {
677 SelectionDAG &DAG = CLI.DAG;
679 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
680 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
681 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
682 SDValue Chain = CLI.Chain;
683 SDValue Callee = CLI.Callee;
684 bool &isTailCall = CLI.IsTailCall;
685 CallingConv::ID CallConv = CLI.CallConv;
686 bool isVarArg = CLI.IsVarArg;
688 // Sparc target does not yet support tail call optimization.
691 // Analyze operands of the call, assigning locations to each operand.
692 SmallVector<CCValAssign, 16> ArgLocs;
693 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
694 DAG.getTarget(), ArgLocs, *DAG.getContext());
695 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
697 // Get the size of the outgoing arguments stack space requirement.
698 unsigned ArgsSize = CCInfo.getNextStackOffset();
700 // Keep stack frames 8-byte aligned.
701 ArgsSize = (ArgsSize+7) & ~7;
703 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
705 // Create local copies for byval args.
706 SmallVector<SDValue, 8> ByValArgs;
707 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
708 ISD::ArgFlagsTy Flags = Outs[i].Flags;
709 if (!Flags.isByVal())
712 SDValue Arg = OutVals[i];
713 unsigned Size = Flags.getByValSize();
714 unsigned Align = Flags.getByValAlign();
716 int FI = MFI->CreateStackObject(Size, Align, false);
717 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
718 SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
720 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
721 false, // isVolatile,
722 (Size <= 32), // AlwaysInline if size <= 32
723 MachinePointerInfo(), MachinePointerInfo());
724 ByValArgs.push_back(FIPtr);
727 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
730 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
731 SmallVector<SDValue, 8> MemOpChains;
733 const unsigned StackOffset = 92;
734 bool hasStructRetAttr = false;
735 // Walk the register/memloc assignments, inserting copies/loads.
736 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
739 CCValAssign &VA = ArgLocs[i];
740 SDValue Arg = OutVals[realArgIdx];
742 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
744 // Use local copy if it is a byval arg.
746 Arg = ByValArgs[byvalArgIdx++];
748 // Promote the value if needed.
749 switch (VA.getLocInfo()) {
750 default: llvm_unreachable("Unknown loc info!");
751 case CCValAssign::Full: break;
752 case CCValAssign::SExt:
753 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
755 case CCValAssign::ZExt:
756 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
758 case CCValAssign::AExt:
759 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
761 case CCValAssign::BCvt:
762 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
766 if (Flags.isSRet()) {
767 assert(VA.needsCustom());
768 // store SRet argument in %sp+64
769 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
770 SDValue PtrOff = DAG.getIntPtrConstant(64);
771 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
772 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
773 MachinePointerInfo(),
775 hasStructRetAttr = true;
779 if (VA.needsCustom()) {
780 assert(VA.getLocVT() == MVT::f64);
783 unsigned Offset = VA.getLocMemOffset() + StackOffset;
784 // if it is double-word aligned, just store.
785 if (Offset % 8 == 0) {
786 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
787 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
788 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
789 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
790 MachinePointerInfo(),
796 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
797 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
798 Arg, StackPtr, MachinePointerInfo(),
800 // Sparc is big-endian, so the high part comes first.
801 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
802 MachinePointerInfo(), false, false, false, 0);
803 // Increment the pointer to the other half.
804 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
805 DAG.getIntPtrConstant(4));
806 // Load the low part.
807 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
808 MachinePointerInfo(), false, false, false, 0);
811 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
813 CCValAssign &NextVA = ArgLocs[++i];
814 if (NextVA.isRegLoc()) {
815 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
817 // Store the low part in stack.
818 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
819 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
820 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
821 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
822 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
823 MachinePointerInfo(),
827 unsigned Offset = VA.getLocMemOffset() + StackOffset;
828 // Store the high part.
829 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
830 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
831 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
832 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
833 MachinePointerInfo(),
835 // Store the low part.
836 PtrOff = DAG.getIntPtrConstant(Offset+4);
837 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
838 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
839 MachinePointerInfo(),
845 // Arguments that can be passed on register must be kept at
848 if (VA.getLocVT() != MVT::f32) {
849 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
852 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
853 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
857 assert(VA.isMemLoc());
859 // Create a store off the stack pointer for this argument.
860 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
861 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);
862 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
863 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
864 MachinePointerInfo(),
869 // Emit all stores, make sure the occur before any copies into physregs.
870 if (!MemOpChains.empty())
871 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
872 &MemOpChains[0], MemOpChains.size());
874 // Build a sequence of copy-to-reg nodes chained together with token
875 // chain and flag operands which copy the outgoing args into registers.
876 // The InFlag in necessary since all emitted instructions must be
879 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
880 unsigned Reg = toCallerWindow(RegsToPass[i].first);
881 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
882 InFlag = Chain.getValue(1);
885 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;
886 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
888 // If the callee is a GlobalAddress node (quite common, every direct call is)
889 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
890 // Likewise ExternalSymbol -> TargetExternalSymbol.
891 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
892 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
893 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
894 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
896 // Returns a chain & a flag for retval copy to use
897 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
898 SmallVector<SDValue, 8> Ops;
899 Ops.push_back(Chain);
900 Ops.push_back(Callee);
901 if (hasStructRetAttr)
902 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32));
903 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
904 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
905 RegsToPass[i].second.getValueType()));
907 // Add a register mask operand representing the call-preserved registers.
908 const SparcRegisterInfo *TRI =
909 ((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo();
910 const uint32_t *Mask = ((hasReturnsTwice)
911 ? TRI->getRTCallPreservedMask(CallConv)
912 : TRI->getCallPreservedMask(CallConv));
913 assert(Mask && "Missing call preserved mask for calling convention");
914 Ops.push_back(DAG.getRegisterMask(Mask));
916 if (InFlag.getNode())
917 Ops.push_back(InFlag);
919 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
920 InFlag = Chain.getValue(1);
922 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
923 DAG.getIntPtrConstant(0, true), InFlag, dl);
924 InFlag = Chain.getValue(1);
926 // Assign locations to each value returned by this call.
927 SmallVector<CCValAssign, 16> RVLocs;
928 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(),
929 DAG.getTarget(), RVLocs, *DAG.getContext());
931 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
933 // Copy all of the result registers out of their specified physreg.
934 for (unsigned i = 0; i != RVLocs.size(); ++i) {
935 Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
936 RVLocs[i].getValVT(), InFlag).getValue(1);
937 InFlag = Chain.getValue(2);
938 InVals.push_back(Chain.getValue(0));
944 // This functions returns true if CalleeName is a ABI function that returns
945 // a long double (fp128).
946 static bool isFP128ABICall(const char *CalleeName)
948 static const char *const ABICalls[] =
949 { "_Q_add", "_Q_sub", "_Q_mul", "_Q_div",
951 "_Q_itoq", "_Q_stoq", "_Q_dtoq", "_Q_utoq",
954 for (const char * const *I = ABICalls; I != 0; ++I)
955 if (strcmp(CalleeName, *I) == 0)
961 SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
963 const Function *CalleeFn = 0;
964 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
965 CalleeFn = dyn_cast<Function>(G->getGlobal());
966 } else if (ExternalSymbolSDNode *E =
967 dyn_cast<ExternalSymbolSDNode>(Callee)) {
968 const Function *Fn = DAG.getMachineFunction().getFunction();
969 const Module *M = Fn->getParent();
970 const char *CalleeName = E->getSymbol();
971 CalleeFn = M->getFunction(CalleeName);
972 if (!CalleeFn && isFP128ABICall(CalleeName))
973 return 16; // Return sizeof(fp128)
979 assert(CalleeFn->hasStructRetAttr() &&
980 "Callee does not have the StructRet attribute.");
982 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType());
983 Type *ElementTy = Ty->getElementType();
984 return getDataLayout()->getTypeAllocSize(ElementTy);
988 // Fixup floating point arguments in the ... part of a varargs call.
990 // The SPARC v9 ABI requires that floating point arguments are treated the same
991 // as integers when calling a varargs function. This does not apply to the
992 // fixed arguments that are part of the function's prototype.
994 // This function post-processes a CCValAssign array created by
995 // AnalyzeCallOperands().
996 static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
997 ArrayRef<ISD::OutputArg> Outs) {
998 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
999 const CCValAssign &VA = ArgLocs[i];
1000 // FIXME: What about f32 arguments? C promotes them to f64 when calling
1001 // varargs functions.
1002 if (!VA.isRegLoc() || VA.getLocVT() != MVT::f64)
1004 // The fixed arguments to a varargs function still go in FP registers.
1005 if (Outs[VA.getValNo()].IsFixed)
1008 // This floating point argument should be reassigned.
1011 // Determine the offset into the argument array.
1012 unsigned Offset = 8 * (VA.getLocReg() - SP::D0);
1013 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1016 // This argument should go in %i0-%i5.
1017 unsigned IReg = SP::I0 + Offset/8;
1018 // Full register, just bitconvert into i64.
1019 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
1020 IReg, MVT::i64, CCValAssign::BCvt);
1022 // This needs to go to memory, we're out of integer registers.
1023 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
1024 Offset, VA.getLocVT(), VA.getLocInfo());
1030 // Lower a call for the 64-bit ABI.
1032 SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
1033 SmallVectorImpl<SDValue> &InVals) const {
1034 SelectionDAG &DAG = CLI.DAG;
1036 SDValue Chain = CLI.Chain;
1038 // Analyze operands of the call, assigning locations to each operand.
1039 SmallVector<CCValAssign, 16> ArgLocs;
1040 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
1041 DAG.getTarget(), ArgLocs, *DAG.getContext());
1042 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
1044 // Get the size of the outgoing arguments stack space requirement.
1045 // The stack offset computed by CC_Sparc64 includes all arguments.
1046 // Called functions expect 6 argument words to exist in the stack frame, used
1048 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset());
1050 // Keep stack frames 16-byte aligned.
1051 ArgsSize = RoundUpToAlignment(ArgsSize, 16);
1053 // Varargs calls require special treatment.
1055 fixupVariableFloatArgs(ArgLocs, CLI.Outs);
1057 // Adjust the stack pointer to make room for the arguments.
1058 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1059 // with more than 6 arguments.
1060 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
1063 // Collect the set of registers to pass to the function and their values.
1064 // This will be emitted as a sequence of CopyToReg nodes glued to the call
1066 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1068 // Collect chains from all the memory opeations that copy arguments to the
1069 // stack. They must follow the stack pointer adjustment above and precede the
1070 // call instruction itself.
1071 SmallVector<SDValue, 8> MemOpChains;
1073 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1074 const CCValAssign &VA = ArgLocs[i];
1075 SDValue Arg = CLI.OutVals[i];
1077 // Promote the value if needed.
1078 switch (VA.getLocInfo()) {
1080 llvm_unreachable("Unknown location info!");
1081 case CCValAssign::Full:
1083 case CCValAssign::SExt:
1084 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1086 case CCValAssign::ZExt:
1087 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1089 case CCValAssign::AExt:
1090 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
1092 case CCValAssign::BCvt:
1093 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1097 if (VA.isRegLoc()) {
1098 // The custom bit on an i32 return value indicates that it should be
1099 // passed in the high bits of the register.
1100 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1101 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1102 DAG.getConstant(32, MVT::i32));
1104 // The next value may go in the low bits of the same register.
1105 // Handle both at once.
1106 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1107 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1108 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
1110 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
1111 // Skip the next value, it's already done.
1115 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg));
1119 assert(VA.isMemLoc());
1121 // Create a store off the stack pointer for this argument.
1122 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
1123 // The argument area starts at %fp+BIAS+128 in the callee frame,
1124 // %sp+BIAS+128 in ours.
1125 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
1126 Subtarget->getStackPointerBias() +
1128 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
1129 MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff,
1130 MachinePointerInfo(),
1134 // Emit all stores, make sure they occur before the call.
1135 if (!MemOpChains.empty())
1136 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1137 &MemOpChains[0], MemOpChains.size());
1139 // Build a sequence of CopyToReg nodes glued together with token chain and
1140 // glue operands which copy the outgoing args into registers. The InGlue is
1141 // necessary since all emitted instructions must be stuck together in order
1142 // to pass the live physical registers.
1144 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1145 Chain = DAG.getCopyToReg(Chain, DL,
1146 RegsToPass[i].first, RegsToPass[i].second, InGlue);
1147 InGlue = Chain.getValue(1);
1150 // If the callee is a GlobalAddress node (quite common, every direct call is)
1151 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1152 // Likewise ExternalSymbol -> TargetExternalSymbol.
1153 SDValue Callee = CLI.Callee;
1154 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
1155 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1156 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy());
1157 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1158 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
1160 // Build the operands for the call instruction itself.
1161 SmallVector<SDValue, 8> Ops;
1162 Ops.push_back(Chain);
1163 Ops.push_back(Callee);
1164 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1165 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1166 RegsToPass[i].second.getValueType()));
1168 // Add a register mask operand representing the call-preserved registers.
1169 const SparcRegisterInfo *TRI =
1170 ((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo();
1171 const uint32_t *Mask = ((hasReturnsTwice)
1172 ? TRI->getRTCallPreservedMask(CLI.CallConv)
1173 : TRI->getCallPreservedMask(CLI.CallConv));
1174 assert(Mask && "Missing call preserved mask for calling convention");
1175 Ops.push_back(DAG.getRegisterMask(Mask));
1177 // Make sure the CopyToReg nodes are glued to the call instruction which
1178 // consumes the registers.
1179 if (InGlue.getNode())
1180 Ops.push_back(InGlue);
1182 // Now the call itself.
1183 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1184 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
1185 InGlue = Chain.getValue(1);
1187 // Revert the stack pointer immediately after the call.
1188 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
1189 DAG.getIntPtrConstant(0, true), InGlue, DL);
1190 InGlue = Chain.getValue(1);
1192 // Now extract the return values. This is more or less the same as
1193 // LowerFormalArguments_64.
1195 // Assign locations to each value returned by this call.
1196 SmallVector<CCValAssign, 16> RVLocs;
1197 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
1198 DAG.getTarget(), RVLocs, *DAG.getContext());
1199 RVInfo.AnalyzeCallResult(CLI.Ins, CC_Sparc64);
1201 // Copy all of the result registers out of their specified physreg.
1202 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1203 CCValAssign &VA = RVLocs[i];
1204 unsigned Reg = toCallerWindow(VA.getLocReg());
1206 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1207 // reside in the same register in the high and low bits. Reuse the
1208 // CopyFromReg previous node to avoid duplicate copies.
1210 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1211 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1212 RV = Chain.getValue(0);
1214 // But usually we'll create a new CopyFromReg for a different register.
1215 if (!RV.getNode()) {
1216 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1217 Chain = RV.getValue(1);
1218 InGlue = Chain.getValue(2);
1221 // Get the high bits for i32 struct elements.
1222 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1223 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
1224 DAG.getConstant(32, MVT::i32));
1226 // The callee promoted the return value, so insert an Assert?ext SDNode so
1227 // we won't promote the value again in this function.
1228 switch (VA.getLocInfo()) {
1229 case CCValAssign::SExt:
1230 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
1231 DAG.getValueType(VA.getValVT()));
1233 case CCValAssign::ZExt:
1234 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
1235 DAG.getValueType(VA.getValVT()));
1241 // Truncate the register down to the return value type.
1242 if (VA.isExtInLoc())
1243 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
1245 InVals.push_back(RV);
1251 //===----------------------------------------------------------------------===//
1252 // TargetLowering Implementation
1253 //===----------------------------------------------------------------------===//
1255 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1257 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1259 default: llvm_unreachable("Unknown integer condition code!");
1260 case ISD::SETEQ: return SPCC::ICC_E;
1261 case ISD::SETNE: return SPCC::ICC_NE;
1262 case ISD::SETLT: return SPCC::ICC_L;
1263 case ISD::SETGT: return SPCC::ICC_G;
1264 case ISD::SETLE: return SPCC::ICC_LE;
1265 case ISD::SETGE: return SPCC::ICC_GE;
1266 case ISD::SETULT: return SPCC::ICC_CS;
1267 case ISD::SETULE: return SPCC::ICC_LEU;
1268 case ISD::SETUGT: return SPCC::ICC_GU;
1269 case ISD::SETUGE: return SPCC::ICC_CC;
1273 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1275 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1277 default: llvm_unreachable("Unknown fp condition code!");
1279 case ISD::SETOEQ: return SPCC::FCC_E;
1281 case ISD::SETUNE: return SPCC::FCC_NE;
1283 case ISD::SETOLT: return SPCC::FCC_L;
1285 case ISD::SETOGT: return SPCC::FCC_G;
1287 case ISD::SETOLE: return SPCC::FCC_LE;
1289 case ISD::SETOGE: return SPCC::FCC_GE;
1290 case ISD::SETULT: return SPCC::FCC_UL;
1291 case ISD::SETULE: return SPCC::FCC_ULE;
1292 case ISD::SETUGT: return SPCC::FCC_UG;
1293 case ISD::SETUGE: return SPCC::FCC_UGE;
1294 case ISD::SETUO: return SPCC::FCC_U;
1295 case ISD::SETO: return SPCC::FCC_O;
1296 case ISD::SETONE: return SPCC::FCC_LG;
1297 case ISD::SETUEQ: return SPCC::FCC_UE;
1301 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
1302 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
1303 Subtarget = &TM.getSubtarget<SparcSubtarget>();
1305 // Set up the register classes.
1306 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1307 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1308 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1309 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1310 if (Subtarget->is64Bit())
1311 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1313 // Turn FP extload into load/fextend
1314 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
1315 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
1317 // Sparc doesn't have i1 sign extending load
1318 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
1320 // Turn FP truncstore into trunc + store.
1321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1322 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1323 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1325 // Custom legalize GlobalAddress nodes into LO/HI parts.
1326 setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom);
1327 setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom);
1328 setOperationAction(ISD::ConstantPool, getPointerTy(), Custom);
1329 setOperationAction(ISD::BlockAddress, getPointerTy(), Custom);
1331 // Sparc doesn't have sext_inreg, replace them with shl/sra
1332 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1333 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
1334 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1336 // Sparc has no REM or DIVREM operations.
1337 setOperationAction(ISD::UREM, MVT::i32, Expand);
1338 setOperationAction(ISD::SREM, MVT::i32, Expand);
1339 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1340 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1342 // Custom expand fp<->sint
1343 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1344 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1347 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
1348 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
1350 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
1351 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
1353 // Sparc has no select or setcc: expand to SELECT_CC.
1354 setOperationAction(ISD::SELECT, MVT::i32, Expand);
1355 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1356 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1357 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1359 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1360 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1361 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1362 setOperationAction(ISD::SETCC, MVT::f128, Expand);
1364 // Sparc doesn't have BRCOND either, it has BR_CC.
1365 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
1366 setOperationAction(ISD::BRIND, MVT::Other, Expand);
1367 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1368 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1369 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1370 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1371 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
1373 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1374 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1375 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1376 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1378 if (Subtarget->is64Bit()) {
1379 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
1380 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
1381 setOperationAction(ISD::SELECT, MVT::i64, Expand);
1382 setOperationAction(ISD::SETCC, MVT::i64, Expand);
1383 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
1384 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1387 // FIXME: There are instructions available for ATOMIC_FENCE
1388 // on SparcV8 and later.
1389 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
1391 if (!Subtarget->isV9()) {
1392 // SparcV8 does not have FNEGD and FABSD.
1393 setOperationAction(ISD::FNEG, MVT::f64, Custom);
1394 setOperationAction(ISD::FABS, MVT::f64, Custom);
1397 setOperationAction(ISD::FSIN , MVT::f128, Expand);
1398 setOperationAction(ISD::FCOS , MVT::f128, Expand);
1399 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
1400 setOperationAction(ISD::FREM , MVT::f128, Expand);
1401 setOperationAction(ISD::FMA , MVT::f128, Expand);
1402 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1403 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1404 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1405 setOperationAction(ISD::FREM , MVT::f64, Expand);
1406 setOperationAction(ISD::FMA , MVT::f64, Expand);
1407 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1408 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1409 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1410 setOperationAction(ISD::FREM , MVT::f32, Expand);
1411 setOperationAction(ISD::FMA , MVT::f32, Expand);
1412 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1413 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1414 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1415 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1416 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1417 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1418 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1419 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1420 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1421 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1422 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1423 setOperationAction(ISD::FPOW , MVT::f128, Expand);
1424 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1425 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1427 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1428 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1429 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1431 // FIXME: Sparc provides these multiplies, but we don't have them yet.
1432 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1433 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1435 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
1437 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1438 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1439 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1440 setOperationAction(ISD::VAARG , MVT::Other, Custom);
1442 // Use the default implementation.
1443 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1444 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1445 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
1446 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
1447 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
1449 // No debug info support yet.
1450 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
1452 setStackPointerRegisterToSaveRestore(SP::O6);
1454 if (Subtarget->isV9())
1455 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
1457 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1458 setOperationAction(ISD::LOAD, MVT::f128, Legal);
1459 setOperationAction(ISD::STORE, MVT::f128, Legal);
1461 setOperationAction(ISD::LOAD, MVT::f128, Custom);
1462 setOperationAction(ISD::STORE, MVT::f128, Custom);
1465 if (Subtarget->hasHardQuad()) {
1466 setOperationAction(ISD::FADD, MVT::f128, Legal);
1467 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1468 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1469 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1470 setOperationAction(ISD::FSQRT, MVT::f128, Legal);
1471 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1472 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1473 if (Subtarget->isV9()) {
1474 setOperationAction(ISD::FNEG, MVT::f128, Legal);
1475 setOperationAction(ISD::FABS, MVT::f128, Legal);
1477 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1478 setOperationAction(ISD::FABS, MVT::f128, Custom);
1481 // Custom legalize f128 operations.
1483 setOperationAction(ISD::FADD, MVT::f128, Custom);
1484 setOperationAction(ISD::FSUB, MVT::f128, Custom);
1485 setOperationAction(ISD::FMUL, MVT::f128, Custom);
1486 setOperationAction(ISD::FDIV, MVT::f128, Custom);
1487 setOperationAction(ISD::FSQRT, MVT::f128, Custom);
1488 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1489 setOperationAction(ISD::FABS, MVT::f128, Custom);
1491 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
1492 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
1493 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1495 // Setup Runtime library names.
1496 if (Subtarget->is64Bit()) {
1497 setLibcallName(RTLIB::ADD_F128, "_Qp_add");
1498 setLibcallName(RTLIB::SUB_F128, "_Qp_sub");
1499 setLibcallName(RTLIB::MUL_F128, "_Qp_mul");
1500 setLibcallName(RTLIB::DIV_F128, "_Qp_div");
1501 setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt");
1502 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi");
1503 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq");
1504 setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq");
1505 setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq");
1506 setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos");
1507 setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod");
1509 setLibcallName(RTLIB::ADD_F128, "_Q_add");
1510 setLibcallName(RTLIB::SUB_F128, "_Q_sub");
1511 setLibcallName(RTLIB::MUL_F128, "_Q_mul");
1512 setLibcallName(RTLIB::DIV_F128, "_Q_div");
1513 setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt");
1514 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi");
1515 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq");
1516 setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq");
1517 setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq");
1518 setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos");
1519 setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod");
1523 setMinFunctionAlignment(2);
1525 computeRegisterProperties();
1528 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
1531 case SPISD::CMPICC: return "SPISD::CMPICC";
1532 case SPISD::CMPFCC: return "SPISD::CMPFCC";
1533 case SPISD::BRICC: return "SPISD::BRICC";
1534 case SPISD::BRXCC: return "SPISD::BRXCC";
1535 case SPISD::BRFCC: return "SPISD::BRFCC";
1536 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
1537 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC";
1538 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
1539 case SPISD::Hi: return "SPISD::Hi";
1540 case SPISD::Lo: return "SPISD::Lo";
1541 case SPISD::FTOI: return "SPISD::FTOI";
1542 case SPISD::ITOF: return "SPISD::ITOF";
1543 case SPISD::CALL: return "SPISD::CALL";
1544 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
1545 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
1546 case SPISD::FLUSHW: return "SPISD::FLUSHW";
1550 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
1551 /// be zero. Op is expected to be a target specific node. Used by DAG
1553 void SparcTargetLowering::computeMaskedBitsForTargetNode
1557 const SelectionDAG &DAG,
1558 unsigned Depth) const {
1559 APInt KnownZero2, KnownOne2;
1560 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
1562 switch (Op.getOpcode()) {
1564 case SPISD::SELECT_ICC:
1565 case SPISD::SELECT_XCC:
1566 case SPISD::SELECT_FCC:
1567 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
1568 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
1569 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1570 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1572 // Only known if known in both the LHS and RHS.
1573 KnownOne &= KnownOne2;
1574 KnownZero &= KnownZero2;
1579 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1580 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1581 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1582 ISD::CondCode CC, unsigned &SPCC) {
1583 if (isa<ConstantSDNode>(RHS) &&
1584 cast<ConstantSDNode>(RHS)->isNullValue() &&
1586 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
1587 LHS.getOpcode() == SPISD::SELECT_XCC) &&
1588 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
1589 (LHS.getOpcode() == SPISD::SELECT_FCC &&
1590 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
1591 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1592 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1593 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() &&
1594 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) {
1595 SDValue CMPCC = LHS.getOperand(3);
1596 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1597 LHS = CMPCC.getOperand(0);
1598 RHS = CMPCC.getOperand(1);
1602 // Convert to a target node and set target flags.
1603 SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
1604 SelectionDAG &DAG) const {
1605 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
1606 return DAG.getTargetGlobalAddress(GA->getGlobal(),
1608 GA->getValueType(0),
1609 GA->getOffset(), TF);
1611 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
1612 return DAG.getTargetConstantPool(CP->getConstVal(),
1613 CP->getValueType(0),
1615 CP->getOffset(), TF);
1617 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
1618 return DAG.getTargetBlockAddress(BA->getBlockAddress(),
1623 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
1624 return DAG.getTargetExternalSymbol(ES->getSymbol(),
1625 ES->getValueType(0), TF);
1627 llvm_unreachable("Unhandled address SDNode");
1630 // Split Op into high and low parts according to HiTF and LoTF.
1631 // Return an ADD node combining the parts.
1632 SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
1633 unsigned HiTF, unsigned LoTF,
1634 SelectionDAG &DAG) const {
1636 EVT VT = Op.getValueType();
1637 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
1638 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
1639 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1642 // Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
1643 // or ExternalSymbol SDNode.
1644 SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
1646 EVT VT = getPointerTy();
1648 // Handle PIC mode first.
1649 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1650 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
1651 SDValue HiLo = makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
1652 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
1653 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo);
1654 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1655 // function has calls.
1656 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1657 MFI->setHasCalls(true);
1658 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
1659 MachinePointerInfo::getGOT(), false, false, false, 0);
1662 // This is one of the absolute code models.
1663 switch(getTargetMachine().getCodeModel()) {
1665 llvm_unreachable("Unsupported absolute code model");
1666 case CodeModel::Small:
1668 return makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
1669 case CodeModel::Medium: {
1671 SDValue H44 = makeHiLoPair(Op, SPII::MO_H44, SPII::MO_M44, DAG);
1672 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32));
1673 SDValue L44 = withTargetFlags(Op, SPII::MO_L44, DAG);
1674 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
1675 return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
1677 case CodeModel::Large: {
1679 SDValue Hi = makeHiLoPair(Op, SPII::MO_HH, SPII::MO_HM, DAG);
1680 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32));
1681 SDValue Lo = makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
1682 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1687 SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
1688 SelectionDAG &DAG) const {
1689 return makeAddress(Op, DAG);
1692 SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
1693 SelectionDAG &DAG) const {
1694 return makeAddress(Op, DAG);
1697 SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
1698 SelectionDAG &DAG) const {
1699 return makeAddress(Op, DAG);
1703 SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args,
1704 SDValue Arg, SDLoc DL,
1705 SelectionDAG &DAG) const {
1706 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1707 EVT ArgVT = Arg.getValueType();
1708 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1714 if (ArgTy->isFP128Ty()) {
1715 // Create a stack object and pass the pointer to the library function.
1716 int FI = MFI->CreateStackObject(16, 8, false);
1717 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
1718 Chain = DAG.getStore(Chain,
1722 MachinePointerInfo(),
1728 Entry.Ty = PointerType::getUnqual(ArgTy);
1730 Args.push_back(Entry);
1735 SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
1736 const char *LibFuncName,
1737 unsigned numArgs) const {
1741 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1743 SDValue Callee = DAG.getExternalSymbol(LibFuncName, getPointerTy());
1744 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
1745 Type *RetTyABI = RetTy;
1746 SDValue Chain = DAG.getEntryNode();
1749 if (RetTy->isFP128Ty()) {
1750 // Create a Stack Object to receive the return value of type f128.
1752 int RetFI = MFI->CreateStackObject(16, 8, false);
1753 RetPtr = DAG.getFrameIndex(RetFI, getPointerTy());
1754 Entry.Node = RetPtr;
1755 Entry.Ty = PointerType::getUnqual(RetTy);
1756 if (!Subtarget->is64Bit())
1757 Entry.isSRet = true;
1758 Entry.isReturned = false;
1759 Args.push_back(Entry);
1760 RetTyABI = Type::getVoidTy(*DAG.getContext());
1763 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
1764 for (unsigned i = 0, e = numArgs; i != e; ++i) {
1765 Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
1768 CallLoweringInfo CLI(Chain,
1770 false, false, false, false,
1773 Callee, Args, DAG, SDLoc(Op));
1774 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
1776 // chain is in second result.
1777 if (RetTyABI == RetTy)
1778 return CallInfo.first;
1780 assert (RetTy->isFP128Ty() && "Unexpected return type!");
1782 Chain = CallInfo.second;
1784 // Load RetPtr to get the return value.
1785 return DAG.getLoad(Op.getValueType(),
1789 MachinePointerInfo(),
1790 false, false, false, 8);
1794 SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
1797 SelectionDAG &DAG) const {
1799 const char *LibCall = 0;
1800 bool is64Bit = Subtarget->is64Bit();
1802 default: llvm_unreachable("Unhandled conditional code!");
1803 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
1804 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
1805 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
1806 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
1807 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
1808 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
1816 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
1819 SDValue Callee = DAG.getExternalSymbol(LibCall, getPointerTy());
1820 Type *RetTy = Type::getInt32Ty(*DAG.getContext());
1822 SDValue Chain = DAG.getEntryNode();
1823 Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG);
1824 Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG);
1827 CallLoweringInfo CLI(Chain,
1829 false, false, false, false,
1832 Callee, Args, DAG, DL);
1834 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
1836 // result is in first, and chain is in second result.
1837 SDValue Result = CallInfo.first;
1841 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
1842 SPCC = SPCC::ICC_NE;
1843 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
1845 case SPCC::FCC_UL : {
1846 SDValue Mask = DAG.getTargetConstant(1, Result.getValueType());
1847 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
1848 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
1849 SPCC = SPCC::ICC_NE;
1850 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
1852 case SPCC::FCC_ULE: {
1853 SDValue RHS = DAG.getTargetConstant(2, Result.getValueType());
1854 SPCC = SPCC::ICC_NE;
1855 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
1857 case SPCC::FCC_UG : {
1858 SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
1860 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
1862 case SPCC::FCC_UGE: {
1863 SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
1864 SPCC = SPCC::ICC_NE;
1865 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
1868 case SPCC::FCC_U : {
1869 SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
1871 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
1873 case SPCC::FCC_O : {
1874 SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
1875 SPCC = SPCC::ICC_NE;
1876 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
1878 case SPCC::FCC_LG : {
1879 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType());
1880 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
1881 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
1882 SPCC = SPCC::ICC_NE;
1883 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
1885 case SPCC::FCC_UE : {
1886 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType());
1887 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
1888 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
1890 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
1896 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
1897 const SparcTargetLowering &TLI) {
1899 if (Op.getOperand(0).getValueType() == MVT::f64)
1900 return TLI.LowerF128Op(Op, DAG,
1901 TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1);
1903 if (Op.getOperand(0).getValueType() == MVT::f32)
1904 return TLI.LowerF128Op(Op, DAG,
1905 TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1);
1907 llvm_unreachable("fpextend with non-float operand!");
1908 return SDValue(0, 0);
1912 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
1913 const SparcTargetLowering &TLI) {
1914 // FP_ROUND on f64 and f32 are legal.
1915 if (Op.getOperand(0).getValueType() != MVT::f128)
1918 if (Op.getValueType() == MVT::f64)
1919 return TLI.LowerF128Op(Op, DAG,
1920 TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1);
1921 if (Op.getValueType() == MVT::f32)
1922 return TLI.LowerF128Op(Op, DAG,
1923 TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1);
1925 llvm_unreachable("fpround to non-float!");
1926 return SDValue(0, 0);
1929 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
1930 const SparcTargetLowering &TLI,
1933 // Convert the fp value to integer in an FP register.
1934 assert(Op.getValueType() == MVT::i32);
1936 if (Op.getOperand(0).getValueType() == MVT::f128 && !hasHardQuad)
1937 return TLI.LowerF128Op(Op, DAG,
1938 TLI.getLibcallName(RTLIB::FPTOSINT_F128_I32), 1);
1940 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
1941 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
1944 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
1945 const SparcTargetLowering &TLI,
1948 assert(Op.getOperand(0).getValueType() == MVT::i32);
1949 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
1950 // Convert the int value to FP in an FP register.
1951 if (Op.getValueType() == MVT::f128 && hasHardQuad)
1952 return TLI.LowerF128Op(Op, DAG,
1953 TLI.getLibcallName(RTLIB::SINTTOFP_I32_F128), 1);
1954 return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
1957 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1958 const SparcTargetLowering &TLI,
1960 SDValue Chain = Op.getOperand(0);
1961 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1962 SDValue LHS = Op.getOperand(2);
1963 SDValue RHS = Op.getOperand(3);
1964 SDValue Dest = Op.getOperand(4);
1966 unsigned Opc, SPCC = ~0U;
1968 // If this is a br_cc of a "setcc", and if the setcc got lowered into
1969 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1970 LookThroughSetCC(LHS, RHS, CC, SPCC);
1972 // Get the condition flag.
1973 SDValue CompareFlag;
1974 if (LHS.getValueType().isInteger()) {
1975 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
1976 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
1977 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
1978 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
1980 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
1981 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
1982 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
1985 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
1986 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
1990 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
1991 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
1994 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1995 const SparcTargetLowering &TLI,
1997 SDValue LHS = Op.getOperand(0);
1998 SDValue RHS = Op.getOperand(1);
1999 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2000 SDValue TrueVal = Op.getOperand(2);
2001 SDValue FalseVal = Op.getOperand(3);
2003 unsigned Opc, SPCC = ~0U;
2005 // If this is a select_cc of a "setcc", and if the setcc got lowered into
2006 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2007 LookThroughSetCC(LHS, RHS, CC, SPCC);
2009 SDValue CompareFlag;
2010 if (LHS.getValueType().isInteger()) {
2011 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2012 Opc = LHS.getValueType() == MVT::i32 ?
2013 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
2014 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2016 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2017 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2018 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2019 Opc = SPISD::SELECT_ICC;
2021 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2022 Opc = SPISD::SELECT_FCC;
2023 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2026 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2027 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
2030 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
2031 const SparcTargetLowering &TLI) {
2032 MachineFunction &MF = DAG.getMachineFunction();
2033 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
2035 // Need frame address to find the address of VarArgsFrameIndex.
2036 MF.getFrameInfo()->setFrameAddressIsTaken(true);
2038 // vastart just stores the address of the VarArgsFrameIndex slot into the
2039 // memory location argument.
2042 DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(),
2043 DAG.getRegister(SP::I6, TLI.getPointerTy()),
2044 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset()));
2045 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2046 return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
2047 MachinePointerInfo(SV), false, false, 0);
2050 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
2051 SDNode *Node = Op.getNode();
2052 EVT VT = Node->getValueType(0);
2053 SDValue InChain = Node->getOperand(0);
2054 SDValue VAListPtr = Node->getOperand(1);
2055 EVT PtrVT = VAListPtr.getValueType();
2056 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2058 SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr,
2059 MachinePointerInfo(SV), false, false, false, 0);
2060 // Increment the pointer, VAList, to the next vaarg.
2061 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
2062 DAG.getIntPtrConstant(VT.getSizeInBits()/8));
2063 // Store the incremented VAList to the legalized pointer.
2064 InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr,
2065 VAListPtr, MachinePointerInfo(SV), false, false, 0);
2066 // Load the actual argument out of the pointer VAList.
2067 // We can't count on greater alignment than the word size.
2068 return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
2069 false, false, false,
2070 std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8);
2073 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
2074 SDValue Chain = Op.getOperand(0); // Legalize the chain.
2075 SDValue Size = Op.getOperand(1); // Legalize the size.
2078 unsigned SPReg = SP::O6;
2079 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
2080 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value
2081 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
2083 // The resultant pointer is actually 16 words from the bottom of the stack,
2084 // to provide a register spill area.
2085 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
2086 DAG.getConstant(96, MVT::i32));
2087 SDValue Ops[2] = { NewVal, Chain };
2088 return DAG.getMergeValues(Ops, 2, dl);
2092 static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
2094 SDValue Chain = DAG.getNode(SPISD::FLUSHW,
2095 dl, MVT::Other, DAG.getEntryNode());
2099 static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
2100 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2101 MFI->setFrameAddressIsTaken(true);
2103 EVT VT = Op.getValueType();
2105 unsigned FrameReg = SP::I6;
2107 uint64_t depth = Op.getConstantOperandVal(0);
2111 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2113 // flush first to make sure the windowed registers' values are in stack
2114 SDValue Chain = getFLUSHW(Op, DAG);
2115 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
2117 for (uint64_t i = 0; i != depth; ++i) {
2118 SDValue Ptr = DAG.getNode(ISD::ADD,
2120 FrameAddr, DAG.getIntPtrConstant(56));
2121 FrameAddr = DAG.getLoad(MVT::i32, dl,
2124 MachinePointerInfo(), false, false, false, 0);
2130 static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
2131 const SparcTargetLowering &TLI) {
2132 MachineFunction &MF = DAG.getMachineFunction();
2133 MachineFrameInfo *MFI = MF.getFrameInfo();
2134 MFI->setReturnAddressIsTaken(true);
2136 EVT VT = Op.getValueType();
2138 uint64_t depth = Op.getConstantOperandVal(0);
2142 unsigned RetReg = MF.addLiveIn(SP::I7,
2143 TLI.getRegClassFor(TLI.getPointerTy()));
2144 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
2146 // Need frame address to find return address of the caller.
2147 MFI->setFrameAddressIsTaken(true);
2149 // flush first to make sure the windowed registers' values are in stack
2150 SDValue Chain = getFLUSHW(Op, DAG);
2151 RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT);
2153 for (uint64_t i = 0; i != depth; ++i) {
2154 SDValue Ptr = DAG.getNode(ISD::ADD,
2157 DAG.getIntPtrConstant((i == depth-1)?60:56));
2158 RetAddr = DAG.getLoad(MVT::i32, dl,
2161 MachinePointerInfo(), false, false, false, 0);
2167 static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode)
2171 assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2172 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2174 // Lower fneg/fabs on f64 to fneg/fabs on f32.
2175 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2176 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2178 SDValue SrcReg64 = Op.getOperand(0);
2179 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2181 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2184 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
2186 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2188 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
2190 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
2195 // Lower a f128 load into two f64 loads.
2196 static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
2199 LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
2200 assert(LdNode && LdNode->getOffset().getOpcode() == ISD::UNDEF
2201 && "Unexpected node type");
2203 SDValue Hi64 = DAG.getLoad(MVT::f64,
2206 LdNode->getBasePtr(),
2207 LdNode->getPointerInfo(),
2208 false, false, false, 8);
2209 EVT addrVT = LdNode->getBasePtr().getValueType();
2210 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2211 LdNode->getBasePtr(),
2212 DAG.getConstant(8, addrVT));
2213 SDValue Lo64 = DAG.getLoad(MVT::f64,
2217 LdNode->getPointerInfo(),
2218 false, false, false, 8);
2220 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
2221 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
2223 SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2225 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2227 SDValue(InFP128, 0),
2230 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2232 SDValue(InFP128, 0),
2235 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
2236 SDValue(Lo64.getNode(), 1) };
2237 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2239 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2240 return DAG.getMergeValues(Ops, 2, dl);
2243 // Lower a f128 store into two f64 stores.
2244 static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
2246 StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
2247 assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF
2248 && "Unexpected node type");
2249 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
2250 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
2252 SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2257 SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2262 SDValue OutChains[2];
2263 OutChains[0] = DAG.getStore(StNode->getChain(),
2266 StNode->getBasePtr(),
2267 MachinePointerInfo(),
2269 EVT addrVT = StNode->getBasePtr().getValueType();
2270 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2271 StNode->getBasePtr(),
2272 DAG.getConstant(8, addrVT));
2273 OutChains[1] = DAG.getStore(StNode->getChain(),
2277 MachinePointerInfo(),
2279 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2283 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG,
2284 const SparcTargetLowering &TLI,
2286 if (Op.getValueType() == MVT::f64)
2287 return LowerF64Op(Op, DAG, ISD::FNEG);
2288 if (Op.getValueType() == MVT::f128)
2289 return TLI.LowerF128Op(Op, DAG, ((is64Bit) ? "_Qp_neg" : "_Q_neg"), 1);
2293 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
2294 if (Op.getValueType() == MVT::f64)
2295 return LowerF64Op(Op, DAG, ISD::FABS);
2296 if (Op.getValueType() != MVT::f128)
2299 // Lower fabs on f128 to fabs on f64
2300 // fabs f128 => fabs f64:sub_even64, fmov f64:sub_odd64
2303 SDValue SrcReg128 = Op.getOperand(0);
2304 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
2306 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
2309 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
2311 Hi64 = LowerF64Op(Hi64, DAG, ISD::FABS);
2313 SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2315 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
2317 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
2324 SDValue SparcTargetLowering::
2325 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2327 bool hasHardQuad = Subtarget->hasHardQuad();
2328 bool is64Bit = Subtarget->is64Bit();
2329 bool isV9 = Subtarget->isV9();
2331 switch (Op.getOpcode()) {
2332 default: llvm_unreachable("Should not custom lower this!");
2334 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this);
2335 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2336 case ISD::GlobalTLSAddress:
2337 llvm_unreachable("TLS not implemented for Sparc.");
2338 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2339 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2340 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2341 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this,
2343 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this,
2345 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this,
2347 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this,
2349 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
2350 case ISD::VAARG: return LowerVAARG(Op, DAG);
2351 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2353 case ISD::LOAD: return LowerF128Load(Op, DAG);
2354 case ISD::STORE: return LowerF128Store(Op, DAG);
2355 case ISD::FADD: return LowerF128Op(Op, DAG,
2356 getLibcallName(RTLIB::ADD_F128), 2);
2357 case ISD::FSUB: return LowerF128Op(Op, DAG,
2358 getLibcallName(RTLIB::SUB_F128), 2);
2359 case ISD::FMUL: return LowerF128Op(Op, DAG,
2360 getLibcallName(RTLIB::MUL_F128), 2);
2361 case ISD::FDIV: return LowerF128Op(Op, DAG,
2362 getLibcallName(RTLIB::DIV_F128), 2);
2363 case ISD::FSQRT: return LowerF128Op(Op, DAG,
2364 getLibcallName(RTLIB::SQRT_F128),1);
2365 case ISD::FNEG: return LowerFNEG(Op, DAG, *this, is64Bit);
2366 case ISD::FABS: return LowerFABS(Op, DAG, isV9);
2367 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this);
2368 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
2373 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2374 MachineBasicBlock *BB) const {
2375 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
2378 DebugLoc dl = MI->getDebugLoc();
2379 // Figure out the conditional branch opcode to use for this select_cc.
2380 switch (MI->getOpcode()) {
2381 default: llvm_unreachable("Unknown SELECT_CC!");
2382 case SP::SELECT_CC_Int_ICC:
2383 case SP::SELECT_CC_FP_ICC:
2384 case SP::SELECT_CC_DFP_ICC:
2385 case SP::SELECT_CC_QFP_ICC:
2386 BROpcode = SP::BCOND;
2388 case SP::SELECT_CC_Int_FCC:
2389 case SP::SELECT_CC_FP_FCC:
2390 case SP::SELECT_CC_DFP_FCC:
2391 case SP::SELECT_CC_QFP_FCC:
2392 BROpcode = SP::FBCOND;
2396 CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
2398 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2399 // control-flow pattern. The incoming instruction knows the destination vreg
2400 // to set, the condition code register to branch on, the true/false values to
2401 // select between, and a branch opcode to use.
2402 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2403 MachineFunction::iterator It = BB;
2410 // fallthrough --> copy0MBB
2411 MachineBasicBlock *thisMBB = BB;
2412 MachineFunction *F = BB->getParent();
2413 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2414 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
2415 F->insert(It, copy0MBB);
2416 F->insert(It, sinkMBB);
2418 // Transfer the remainder of BB and its successor edges to sinkMBB.
2419 sinkMBB->splice(sinkMBB->begin(), BB,
2420 llvm::next(MachineBasicBlock::iterator(MI)),
2422 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
2424 // Add the true and fallthrough blocks as its successors.
2425 BB->addSuccessor(copy0MBB);
2426 BB->addSuccessor(sinkMBB);
2428 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
2431 // %FalseValue = ...
2432 // # fallthrough to sinkMBB
2435 // Update machine-CFG edges
2436 BB->addSuccessor(sinkMBB);
2439 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2442 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
2443 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
2444 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
2446 MI->eraseFromParent(); // The pseudo instruction is gone now.
2450 //===----------------------------------------------------------------------===//
2451 // Sparc Inline Assembly Support
2452 //===----------------------------------------------------------------------===//
2454 /// getConstraintType - Given a constraint letter, return the type of
2455 /// constraint it is for this target.
2456 SparcTargetLowering::ConstraintType
2457 SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
2458 if (Constraint.size() == 1) {
2459 switch (Constraint[0]) {
2461 case 'r': return C_RegisterClass;
2465 return TargetLowering::getConstraintType(Constraint);
2468 std::pair<unsigned, const TargetRegisterClass*>
2469 SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
2471 if (Constraint.size() == 1) {
2472 switch (Constraint[0]) {
2474 return std::make_pair(0U, &SP::IntRegsRegClass);
2478 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2482 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
2483 // The Sparc target isn't yet aware of offsets.