1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "SparcISelLowering.h"
16 #include "MCTargetDesc/SparcMCExpr.h"
17 #include "SparcMachineFunctionInfo.h"
18 #include "SparcRegisterInfo.h"
19 #include "SparcTargetMachine.h"
20 #include "SparcTargetObjectFile.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/Support/ErrorHandling.h"
35 //===----------------------------------------------------------------------===//
36 // Calling Convention Implementation
37 //===----------------------------------------------------------------------===//
39 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
40 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
41 ISD::ArgFlagsTy &ArgFlags, CCState &State)
43 assert (ArgFlags.isSRet());
45 // Assign SRet argument.
46 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
52 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
53 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
54 ISD::ArgFlagsTy &ArgFlags, CCState &State)
56 static const MCPhysReg RegList[] = {
57 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
59 // Try to get first reg.
60 if (unsigned Reg = State.AllocateReg(RegList)) {
61 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
63 // Assign whole thing in stack.
64 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
65 State.AllocateStack(8,4),
70 // Try to get second reg.
71 if (unsigned Reg = State.AllocateReg(RegList))
72 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
74 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
75 State.AllocateStack(4,4),
80 // Allocate a full-sized argument for the 64-bit ABI.
81 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
82 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
83 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
84 assert((LocVT == MVT::f32 || LocVT == MVT::f128
85 || LocVT.getSizeInBits() == 64) &&
86 "Can't handle non-64 bits locations");
88 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
89 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
90 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8;
91 unsigned Offset = State.AllocateStack(size, alignment);
94 if (LocVT == MVT::i64 && Offset < 6*8)
95 // Promote integers to %i0-%i5.
96 Reg = SP::I0 + Offset/8;
97 else if (LocVT == MVT::f64 && Offset < 16*8)
98 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
99 Reg = SP::D0 + Offset/8;
100 else if (LocVT == MVT::f32 && Offset < 16*8)
101 // Promote floats to %f1, %f3, ...
102 Reg = SP::F1 + Offset/4;
103 else if (LocVT == MVT::f128 && Offset < 16*8)
104 // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
105 Reg = SP::Q0 + Offset/16;
107 // Promote to register when possible, otherwise use the stack slot.
109 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
113 // This argument goes on the stack in an 8-byte slot.
114 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
115 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
116 if (LocVT == MVT::f32)
119 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
123 // Allocate a half-sized argument for the 64-bit ABI.
125 // This is used when passing { float, int } structs by value in registers.
126 static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT,
127 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
128 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
129 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
130 unsigned Offset = State.AllocateStack(4, 4);
132 if (LocVT == MVT::f32 && Offset < 16*8) {
133 // Promote floats to %f0-%f31.
134 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
139 if (LocVT == MVT::i32 && Offset < 6*8) {
140 // Promote integers to %i0-%i5, using half the register.
141 unsigned Reg = SP::I0 + Offset/8;
143 LocInfo = CCValAssign::AExt;
145 // Set the Custom bit if this i32 goes in the high bits of a register.
147 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
150 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
154 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
158 #include "SparcGenCallingConv.inc"
160 // The calling conventions in SparcCallingConv.td are described in terms of the
161 // callee's register window. This function translates registers to the
162 // corresponding caller window %o register.
163 static unsigned toCallerWindow(unsigned Reg) {
164 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum");
165 if (Reg >= SP::I0 && Reg <= SP::I7)
166 return Reg - SP::I0 + SP::O0;
171 SparcTargetLowering::LowerReturn(SDValue Chain,
172 CallingConv::ID CallConv, bool IsVarArg,
173 const SmallVectorImpl<ISD::OutputArg> &Outs,
174 const SmallVectorImpl<SDValue> &OutVals,
175 SDLoc DL, SelectionDAG &DAG) const {
176 if (Subtarget->is64Bit())
177 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
178 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
182 SparcTargetLowering::LowerReturn_32(SDValue Chain,
183 CallingConv::ID CallConv, bool IsVarArg,
184 const SmallVectorImpl<ISD::OutputArg> &Outs,
185 const SmallVectorImpl<SDValue> &OutVals,
186 SDLoc DL, SelectionDAG &DAG) const {
187 MachineFunction &MF = DAG.getMachineFunction();
189 // CCValAssign - represent the assignment of the return value to locations.
190 SmallVector<CCValAssign, 16> RVLocs;
192 // CCState - Info about the registers and stack slot.
193 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
196 // Analyze return values.
197 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
200 SmallVector<SDValue, 4> RetOps(1, Chain);
201 // Make room for the return address offset.
202 RetOps.push_back(SDValue());
204 // Copy the result values into the output registers.
205 for (unsigned i = 0; i != RVLocs.size(); ++i) {
206 CCValAssign &VA = RVLocs[i];
207 assert(VA.isRegLoc() && "Can only return in registers!");
209 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(),
212 // Guarantee that all emitted copies are stuck together with flags.
213 Flag = Chain.getValue(1);
214 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
217 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
218 // If the function returns a struct, copy the SRetReturnReg to I0
219 if (MF.getFunction()->hasStructRetAttr()) {
220 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
221 unsigned Reg = SFI->getSRetReturnReg();
223 llvm_unreachable("sret virtual register not created in the entry block");
224 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
225 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
226 Flag = Chain.getValue(1);
227 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy()));
228 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
231 RetOps[0] = Chain; // Update chain.
232 RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);
234 // Add the flag if we have it.
236 RetOps.push_back(Flag);
238 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
241 // Lower return values for the 64-bit ABI.
242 // Return values are passed the exactly the same way as function arguments.
244 SparcTargetLowering::LowerReturn_64(SDValue Chain,
245 CallingConv::ID CallConv, bool IsVarArg,
246 const SmallVectorImpl<ISD::OutputArg> &Outs,
247 const SmallVectorImpl<SDValue> &OutVals,
248 SDLoc DL, SelectionDAG &DAG) const {
249 // CCValAssign - represent the assignment of the return value to locations.
250 SmallVector<CCValAssign, 16> RVLocs;
252 // CCState - Info about the registers and stack slot.
253 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
256 // Analyze return values.
257 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
260 SmallVector<SDValue, 4> RetOps(1, Chain);
262 // The second operand on the return instruction is the return address offset.
263 // The return address is always %i7+8 with the 64-bit ABI.
264 RetOps.push_back(DAG.getConstant(8, MVT::i32));
266 // Copy the result values into the output registers.
267 for (unsigned i = 0; i != RVLocs.size(); ++i) {
268 CCValAssign &VA = RVLocs[i];
269 assert(VA.isRegLoc() && "Can only return in registers!");
270 SDValue OutVal = OutVals[i];
272 // Integer return values must be sign or zero extended by the callee.
273 switch (VA.getLocInfo()) {
274 case CCValAssign::Full: break;
275 case CCValAssign::SExt:
276 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
278 case CCValAssign::ZExt:
279 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
281 case CCValAssign::AExt:
282 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
285 llvm_unreachable("Unknown loc info!");
288 // The custom bit on an i32 return value indicates that it should be passed
289 // in the high bits of the register.
290 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
291 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
292 DAG.getConstant(32, MVT::i32));
294 // The next value may go in the low bits of the same register.
295 // Handle both at once.
296 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
297 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
298 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
299 // Skip the next value, it's already done.
304 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
306 // Guarantee that all emitted copies are stuck together with flags.
307 Flag = Chain.getValue(1);
308 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
311 RetOps[0] = Chain; // Update chain.
313 // Add the flag if we have it.
315 RetOps.push_back(Flag);
317 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
320 SDValue SparcTargetLowering::
321 LowerFormalArguments(SDValue Chain,
322 CallingConv::ID CallConv,
324 const SmallVectorImpl<ISD::InputArg> &Ins,
327 SmallVectorImpl<SDValue> &InVals) const {
328 if (Subtarget->is64Bit())
329 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
331 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
335 /// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
336 /// passed in either one or two GPRs, including FP values. TODO: we should
337 /// pass FP values in FP registers for fastcc functions.
338 SDValue SparcTargetLowering::
339 LowerFormalArguments_32(SDValue Chain,
340 CallingConv::ID CallConv,
342 const SmallVectorImpl<ISD::InputArg> &Ins,
345 SmallVectorImpl<SDValue> &InVals) const {
346 MachineFunction &MF = DAG.getMachineFunction();
347 MachineRegisterInfo &RegInfo = MF.getRegInfo();
348 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
350 // Assign locations to all of the incoming arguments.
351 SmallVector<CCValAssign, 16> ArgLocs;
352 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
354 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
356 const unsigned StackOffset = 92;
359 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
360 CCValAssign &VA = ArgLocs[i];
362 if (Ins[InIdx].Flags.isSRet()) {
364 report_fatal_error("sparc only supports sret on the first parameter");
365 // Get SRet from [%fp+64].
366 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true);
367 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
368 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
369 MachinePointerInfo(),
370 false, false, false, 0);
371 InVals.push_back(Arg);
376 if (VA.needsCustom()) {
377 assert(VA.getLocVT() == MVT::f64);
378 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
379 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
380 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
383 CCValAssign &NextVA = ArgLocs[++i];
386 if (NextVA.isMemLoc()) {
387 int FrameIdx = MF.getFrameInfo()->
388 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
389 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
390 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
391 MachinePointerInfo(),
392 false, false, false, 0);
394 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
395 &SP::IntRegsRegClass);
396 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
399 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
400 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
401 InVals.push_back(WholeValue);
404 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
405 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
406 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
407 if (VA.getLocVT() == MVT::f32)
408 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
409 else if (VA.getLocVT() != MVT::i32) {
410 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
411 DAG.getValueType(VA.getLocVT()));
412 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
414 InVals.push_back(Arg);
418 assert(VA.isMemLoc());
420 unsigned Offset = VA.getLocMemOffset()+StackOffset;
422 if (VA.needsCustom()) {
423 assert(VA.getValVT() == MVT::f64);
424 // If it is double-word aligned, just load.
425 if (Offset % 8 == 0) {
426 int FI = MF.getFrameInfo()->CreateFixedObject(8,
429 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
430 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
431 MachinePointerInfo(),
432 false,false, false, 0);
433 InVals.push_back(Load);
437 int FI = MF.getFrameInfo()->CreateFixedObject(4,
440 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
441 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
442 MachinePointerInfo(),
443 false, false, false, 0);
444 int FI2 = MF.getFrameInfo()->CreateFixedObject(4,
447 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy());
449 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2,
450 MachinePointerInfo(),
451 false, false, false, 0);
454 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
455 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
456 InVals.push_back(WholeValue);
460 int FI = MF.getFrameInfo()->CreateFixedObject(4,
463 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
465 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
466 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
467 MachinePointerInfo(),
468 false, false, false, 0);
470 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
471 // Sparc is big endian, so add an offset based on the ObjectVT.
472 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
473 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
474 DAG.getConstant(Offset, MVT::i32));
475 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
476 MachinePointerInfo(),
477 VA.getValVT(), false, false, false,0);
478 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
480 InVals.push_back(Load);
483 if (MF.getFunction()->hasStructRetAttr()) {
484 // Copy the SRet Argument to SRetReturnReg.
485 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
486 unsigned Reg = SFI->getSRetReturnReg();
488 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
489 SFI->setSRetReturnReg(Reg);
491 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
492 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
495 // Store remaining ArgRegs to the stack if this is a varargs function.
497 static const MCPhysReg ArgRegs[] = {
498 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
500 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs);
501 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
502 unsigned ArgOffset = CCInfo.getNextStackOffset();
503 if (NumAllocated == 6)
504 ArgOffset += StackOffset;
507 ArgOffset = 68+4*NumAllocated;
510 // Remember the vararg offset for the va_start implementation.
511 FuncInfo->setVarArgsFrameOffset(ArgOffset);
513 std::vector<SDValue> OutChains;
515 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
516 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
517 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
518 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
520 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
522 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
524 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr,
525 MachinePointerInfo(),
530 if (!OutChains.empty()) {
531 OutChains.push_back(Chain);
532 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
539 // Lower formal arguments for the 64 bit ABI.
540 SDValue SparcTargetLowering::
541 LowerFormalArguments_64(SDValue Chain,
542 CallingConv::ID CallConv,
544 const SmallVectorImpl<ISD::InputArg> &Ins,
547 SmallVectorImpl<SDValue> &InVals) const {
548 MachineFunction &MF = DAG.getMachineFunction();
550 // Analyze arguments according to CC_Sparc64.
551 SmallVector<CCValAssign, 16> ArgLocs;
552 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
554 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
556 // The argument array begins at %fp+BIAS+128, after the register save area.
557 const unsigned ArgArea = 128;
559 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
560 CCValAssign &VA = ArgLocs[i];
562 // This argument is passed in a register.
563 // All integer register arguments are promoted by the caller to i64.
565 // Create a virtual register for the promoted live-in value.
566 unsigned VReg = MF.addLiveIn(VA.getLocReg(),
567 getRegClassFor(VA.getLocVT()));
568 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
570 // Get the high bits for i32 struct elements.
571 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
572 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
573 DAG.getConstant(32, MVT::i32));
575 // The caller promoted the argument, so insert an Assert?ext SDNode so we
576 // won't promote the value again in this function.
577 switch (VA.getLocInfo()) {
578 case CCValAssign::SExt:
579 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
580 DAG.getValueType(VA.getValVT()));
582 case CCValAssign::ZExt:
583 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
584 DAG.getValueType(VA.getValVT()));
590 // Truncate the register down to the argument type.
592 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
594 InVals.push_back(Arg);
598 // The registers are exhausted. This argument was passed on the stack.
599 assert(VA.isMemLoc());
600 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
601 // beginning of the arguments area at %fp+BIAS+128.
602 unsigned Offset = VA.getLocMemOffset() + ArgArea;
603 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
604 // Adjust offset for extended arguments, SPARC is big-endian.
605 // The caller will have written the full slot with extended bytes, but we
606 // prefer our own extending loads.
608 Offset += 8 - ValSize;
609 int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true);
610 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain,
611 DAG.getFrameIndex(FI, getPointerTy()),
612 MachinePointerInfo::getFixedStack(FI),
613 false, false, false, 0));
619 // This function takes variable arguments, some of which may have been passed
620 // in registers %i0-%i5. Variable floating point arguments are never passed
621 // in floating point registers. They go on %i0-%i5 or on the stack like
622 // integer arguments.
624 // The va_start intrinsic needs to know the offset to the first variable
626 unsigned ArgOffset = CCInfo.getNextStackOffset();
627 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
628 // Skip the 128 bytes of register save area.
629 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
630 Subtarget->getStackPointerBias());
632 // Save the variable arguments that were passed in registers.
633 // The caller is required to reserve stack space for 6 arguments regardless
634 // of how many arguments were actually passed.
635 SmallVector<SDValue, 8> OutChains;
636 for (; ArgOffset < 6*8; ArgOffset += 8) {
637 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
638 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
639 int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true);
640 OutChains.push_back(DAG.getStore(Chain, DL, VArg,
641 DAG.getFrameIndex(FI, getPointerTy()),
642 MachinePointerInfo::getFixedStack(FI),
646 if (!OutChains.empty())
647 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
653 SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
654 SmallVectorImpl<SDValue> &InVals) const {
655 if (Subtarget->is64Bit())
656 return LowerCall_64(CLI, InVals);
657 return LowerCall_32(CLI, InVals);
660 static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
661 ImmutableCallSite *CS) {
663 return CS->hasFnAttr(Attribute::ReturnsTwice);
665 const Function *CalleeFn = nullptr;
666 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
667 CalleeFn = dyn_cast<Function>(G->getGlobal());
668 } else if (ExternalSymbolSDNode *E =
669 dyn_cast<ExternalSymbolSDNode>(Callee)) {
670 const Function *Fn = DAG.getMachineFunction().getFunction();
671 const Module *M = Fn->getParent();
672 const char *CalleeName = E->getSymbol();
673 CalleeFn = M->getFunction(CalleeName);
678 return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
681 // Lower a call for the 32-bit ABI.
683 SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
684 SmallVectorImpl<SDValue> &InVals) const {
685 SelectionDAG &DAG = CLI.DAG;
687 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
688 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
689 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
690 SDValue Chain = CLI.Chain;
691 SDValue Callee = CLI.Callee;
692 bool &isTailCall = CLI.IsTailCall;
693 CallingConv::ID CallConv = CLI.CallConv;
694 bool isVarArg = CLI.IsVarArg;
696 // Sparc target does not yet support tail call optimization.
699 // Analyze operands of the call, assigning locations to each operand.
700 SmallVector<CCValAssign, 16> ArgLocs;
701 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
703 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
705 // Get the size of the outgoing arguments stack space requirement.
706 unsigned ArgsSize = CCInfo.getNextStackOffset();
708 // Keep stack frames 8-byte aligned.
709 ArgsSize = (ArgsSize+7) & ~7;
711 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
713 // Create local copies for byval args.
714 SmallVector<SDValue, 8> ByValArgs;
715 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
716 ISD::ArgFlagsTy Flags = Outs[i].Flags;
717 if (!Flags.isByVal())
720 SDValue Arg = OutVals[i];
721 unsigned Size = Flags.getByValSize();
722 unsigned Align = Flags.getByValAlign();
724 int FI = MFI->CreateStackObject(Size, Align, false);
725 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
726 SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
728 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
729 false, // isVolatile,
730 (Size <= 32), // AlwaysInline if size <= 32
731 MachinePointerInfo(), MachinePointerInfo());
732 ByValArgs.push_back(FIPtr);
735 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
738 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
739 SmallVector<SDValue, 8> MemOpChains;
741 const unsigned StackOffset = 92;
742 bool hasStructRetAttr = false;
743 // Walk the register/memloc assignments, inserting copies/loads.
744 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
747 CCValAssign &VA = ArgLocs[i];
748 SDValue Arg = OutVals[realArgIdx];
750 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
752 // Use local copy if it is a byval arg.
754 Arg = ByValArgs[byvalArgIdx++];
756 // Promote the value if needed.
757 switch (VA.getLocInfo()) {
758 default: llvm_unreachable("Unknown loc info!");
759 case CCValAssign::Full: break;
760 case CCValAssign::SExt:
761 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
763 case CCValAssign::ZExt:
764 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
766 case CCValAssign::AExt:
767 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
769 case CCValAssign::BCvt:
770 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
774 if (Flags.isSRet()) {
775 assert(VA.needsCustom());
776 // store SRet argument in %sp+64
777 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
778 SDValue PtrOff = DAG.getIntPtrConstant(64);
779 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
780 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
781 MachinePointerInfo(),
783 hasStructRetAttr = true;
787 if (VA.needsCustom()) {
788 assert(VA.getLocVT() == MVT::f64);
791 unsigned Offset = VA.getLocMemOffset() + StackOffset;
792 // if it is double-word aligned, just store.
793 if (Offset % 8 == 0) {
794 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
795 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
796 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
797 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
798 MachinePointerInfo(),
804 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
805 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
806 Arg, StackPtr, MachinePointerInfo(),
808 // Sparc is big-endian, so the high part comes first.
809 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
810 MachinePointerInfo(), false, false, false, 0);
811 // Increment the pointer to the other half.
812 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
813 DAG.getIntPtrConstant(4));
814 // Load the low part.
815 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
816 MachinePointerInfo(), false, false, false, 0);
819 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
821 CCValAssign &NextVA = ArgLocs[++i];
822 if (NextVA.isRegLoc()) {
823 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
825 // Store the low part in stack.
826 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
827 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
828 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
829 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
830 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
831 MachinePointerInfo(),
835 unsigned Offset = VA.getLocMemOffset() + StackOffset;
836 // Store the high part.
837 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
838 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
839 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
840 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
841 MachinePointerInfo(),
843 // Store the low part.
844 PtrOff = DAG.getIntPtrConstant(Offset+4);
845 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
846 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
847 MachinePointerInfo(),
853 // Arguments that can be passed on register must be kept at
856 if (VA.getLocVT() != MVT::f32) {
857 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
860 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
861 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
865 assert(VA.isMemLoc());
867 // Create a store off the stack pointer for this argument.
868 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
869 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);
870 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
871 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
872 MachinePointerInfo(),
877 // Emit all stores, make sure the occur before any copies into physregs.
878 if (!MemOpChains.empty())
879 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
881 // Build a sequence of copy-to-reg nodes chained together with token
882 // chain and flag operands which copy the outgoing args into registers.
883 // The InFlag in necessary since all emitted instructions must be
886 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
887 unsigned Reg = toCallerWindow(RegsToPass[i].first);
888 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
889 InFlag = Chain.getValue(1);
892 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;
893 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
895 // If the callee is a GlobalAddress node (quite common, every direct call is)
896 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
897 // Likewise ExternalSymbol -> TargetExternalSymbol.
898 unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_)
899 ? SparcMCExpr::VK_Sparc_WPLT30 : 0);
900 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
901 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF);
902 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
903 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF);
905 // Returns a chain & a flag for retval copy to use
906 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
907 SmallVector<SDValue, 8> Ops;
908 Ops.push_back(Chain);
909 Ops.push_back(Callee);
910 if (hasStructRetAttr)
911 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32));
912 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
913 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
914 RegsToPass[i].second.getValueType()));
916 // Add a register mask operand representing the call-preserved registers.
917 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
918 const uint32_t *Mask =
920 ? TRI->getRTCallPreservedMask(CallConv)
921 : TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv));
922 assert(Mask && "Missing call preserved mask for calling convention");
923 Ops.push_back(DAG.getRegisterMask(Mask));
925 if (InFlag.getNode())
926 Ops.push_back(InFlag);
928 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
929 InFlag = Chain.getValue(1);
931 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
932 DAG.getIntPtrConstant(0, true), InFlag, dl);
933 InFlag = Chain.getValue(1);
935 // Assign locations to each value returned by this call.
936 SmallVector<CCValAssign, 16> RVLocs;
937 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
940 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
942 // Copy all of the result registers out of their specified physreg.
943 for (unsigned i = 0; i != RVLocs.size(); ++i) {
944 Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
945 RVLocs[i].getValVT(), InFlag).getValue(1);
946 InFlag = Chain.getValue(2);
947 InVals.push_back(Chain.getValue(0));
953 // This functions returns true if CalleeName is a ABI function that returns
954 // a long double (fp128).
955 static bool isFP128ABICall(const char *CalleeName)
957 static const char *const ABICalls[] =
958 { "_Q_add", "_Q_sub", "_Q_mul", "_Q_div",
960 "_Q_itoq", "_Q_stoq", "_Q_dtoq", "_Q_utoq",
961 "_Q_lltoq", "_Q_ulltoq",
964 for (const char * const *I = ABICalls; *I != nullptr; ++I)
965 if (strcmp(CalleeName, *I) == 0)
971 SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
973 const Function *CalleeFn = nullptr;
974 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
975 CalleeFn = dyn_cast<Function>(G->getGlobal());
976 } else if (ExternalSymbolSDNode *E =
977 dyn_cast<ExternalSymbolSDNode>(Callee)) {
978 const Function *Fn = DAG.getMachineFunction().getFunction();
979 const Module *M = Fn->getParent();
980 const char *CalleeName = E->getSymbol();
981 CalleeFn = M->getFunction(CalleeName);
982 if (!CalleeFn && isFP128ABICall(CalleeName))
983 return 16; // Return sizeof(fp128)
989 assert(CalleeFn->hasStructRetAttr() &&
990 "Callee does not have the StructRet attribute.");
992 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType());
993 Type *ElementTy = Ty->getElementType();
994 return getDataLayout()->getTypeAllocSize(ElementTy);
998 // Fixup floating point arguments in the ... part of a varargs call.
1000 // The SPARC v9 ABI requires that floating point arguments are treated the same
1001 // as integers when calling a varargs function. This does not apply to the
1002 // fixed arguments that are part of the function's prototype.
1004 // This function post-processes a CCValAssign array created by
1005 // AnalyzeCallOperands().
1006 static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
1007 ArrayRef<ISD::OutputArg> Outs) {
1008 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1009 const CCValAssign &VA = ArgLocs[i];
1010 MVT ValTy = VA.getLocVT();
1011 // FIXME: What about f32 arguments? C promotes them to f64 when calling
1012 // varargs functions.
1013 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1015 // The fixed arguments to a varargs function still go in FP registers.
1016 if (Outs[VA.getValNo()].IsFixed)
1019 // This floating point argument should be reassigned.
1022 // Determine the offset into the argument array.
1023 unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1024 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1025 unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1026 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1029 // This argument should go in %i0-%i5.
1030 unsigned IReg = SP::I0 + Offset/8;
1031 if (ValTy == MVT::f64)
1032 // Full register, just bitconvert into i64.
1033 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
1034 IReg, MVT::i64, CCValAssign::BCvt);
1036 assert(ValTy == MVT::f128 && "Unexpected type!");
1037 // Full register, just bitconvert into i128 -- We will lower this into
1038 // two i64s in LowerCall_64.
1039 NewVA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(),
1040 IReg, MVT::i128, CCValAssign::BCvt);
1043 // This needs to go to memory, we're out of integer registers.
1044 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
1045 Offset, VA.getLocVT(), VA.getLocInfo());
1051 // Lower a call for the 64-bit ABI.
1053 SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
1054 SmallVectorImpl<SDValue> &InVals) const {
1055 SelectionDAG &DAG = CLI.DAG;
1057 SDValue Chain = CLI.Chain;
1059 // Sparc target does not yet support tail call optimization.
1060 CLI.IsTailCall = false;
1062 // Analyze operands of the call, assigning locations to each operand.
1063 SmallVector<CCValAssign, 16> ArgLocs;
1064 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
1066 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
1068 // Get the size of the outgoing arguments stack space requirement.
1069 // The stack offset computed by CC_Sparc64 includes all arguments.
1070 // Called functions expect 6 argument words to exist in the stack frame, used
1072 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset());
1074 // Keep stack frames 16-byte aligned.
1075 ArgsSize = RoundUpToAlignment(ArgsSize, 16);
1077 // Varargs calls require special treatment.
1079 fixupVariableFloatArgs(ArgLocs, CLI.Outs);
1081 // Adjust the stack pointer to make room for the arguments.
1082 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1083 // with more than 6 arguments.
1084 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
1087 // Collect the set of registers to pass to the function and their values.
1088 // This will be emitted as a sequence of CopyToReg nodes glued to the call
1090 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1092 // Collect chains from all the memory opeations that copy arguments to the
1093 // stack. They must follow the stack pointer adjustment above and precede the
1094 // call instruction itself.
1095 SmallVector<SDValue, 8> MemOpChains;
1097 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1098 const CCValAssign &VA = ArgLocs[i];
1099 SDValue Arg = CLI.OutVals[i];
1101 // Promote the value if needed.
1102 switch (VA.getLocInfo()) {
1104 llvm_unreachable("Unknown location info!");
1105 case CCValAssign::Full:
1107 case CCValAssign::SExt:
1108 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1110 case CCValAssign::ZExt:
1111 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1113 case CCValAssign::AExt:
1114 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
1116 case CCValAssign::BCvt:
1117 // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
1118 // SPARC does not support i128 natively. Lower it into two i64, see below.
1119 if (!VA.needsCustom() || VA.getValVT() != MVT::f128
1120 || VA.getLocVT() != MVT::i128)
1121 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1125 if (VA.isRegLoc()) {
1126 if (VA.needsCustom() && VA.getValVT() == MVT::f128
1127 && VA.getLocVT() == MVT::i128) {
1128 // Store and reload into the interger register reg and reg+1.
1129 unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1130 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1131 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
1132 SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset);
1133 HiPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
1135 SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8);
1136 LoPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
1139 // Store to %sp+BIAS+128+Offset
1140 SDValue Store = DAG.getStore(Chain, DL, Arg, HiPtrOff,
1141 MachinePointerInfo(),
1143 // Load into Reg and Reg+1
1144 SDValue Hi64 = DAG.getLoad(MVT::i64, DL, Store, HiPtrOff,
1145 MachinePointerInfo(),
1146 false, false, false, 0);
1147 SDValue Lo64 = DAG.getLoad(MVT::i64, DL, Store, LoPtrOff,
1148 MachinePointerInfo(),
1149 false, false, false, 0);
1150 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()),
1152 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1),
1157 // The custom bit on an i32 return value indicates that it should be
1158 // passed in the high bits of the register.
1159 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1160 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1161 DAG.getConstant(32, MVT::i32));
1163 // The next value may go in the low bits of the same register.
1164 // Handle both at once.
1165 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1166 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1167 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
1169 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
1170 // Skip the next value, it's already done.
1174 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg));
1178 assert(VA.isMemLoc());
1180 // Create a store off the stack pointer for this argument.
1181 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
1182 // The argument area starts at %fp+BIAS+128 in the callee frame,
1183 // %sp+BIAS+128 in ours.
1184 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
1185 Subtarget->getStackPointerBias() +
1187 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
1188 MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff,
1189 MachinePointerInfo(),
1193 // Emit all stores, make sure they occur before the call.
1194 if (!MemOpChains.empty())
1195 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1197 // Build a sequence of CopyToReg nodes glued together with token chain and
1198 // glue operands which copy the outgoing args into registers. The InGlue is
1199 // necessary since all emitted instructions must be stuck together in order
1200 // to pass the live physical registers.
1202 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1203 Chain = DAG.getCopyToReg(Chain, DL,
1204 RegsToPass[i].first, RegsToPass[i].second, InGlue);
1205 InGlue = Chain.getValue(1);
1208 // If the callee is a GlobalAddress node (quite common, every direct call is)
1209 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1210 // Likewise ExternalSymbol -> TargetExternalSymbol.
1211 SDValue Callee = CLI.Callee;
1212 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
1213 unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_)
1214 ? SparcMCExpr::VK_Sparc_WPLT30 : 0);
1215 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1216 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0,
1218 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1219 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy(), TF);
1221 // Build the operands for the call instruction itself.
1222 SmallVector<SDValue, 8> Ops;
1223 Ops.push_back(Chain);
1224 Ops.push_back(Callee);
1225 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1226 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1227 RegsToPass[i].second.getValueType()));
1229 // Add a register mask operand representing the call-preserved registers.
1230 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1231 const uint32_t *Mask =
1232 ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CLI.CallConv)
1233 : TRI->getCallPreservedMask(DAG.getMachineFunction(),
1235 assert(Mask && "Missing call preserved mask for calling convention");
1236 Ops.push_back(DAG.getRegisterMask(Mask));
1238 // Make sure the CopyToReg nodes are glued to the call instruction which
1239 // consumes the registers.
1240 if (InGlue.getNode())
1241 Ops.push_back(InGlue);
1243 // Now the call itself.
1244 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1245 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, Ops);
1246 InGlue = Chain.getValue(1);
1248 // Revert the stack pointer immediately after the call.
1249 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
1250 DAG.getIntPtrConstant(0, true), InGlue, DL);
1251 InGlue = Chain.getValue(1);
1253 // Now extract the return values. This is more or less the same as
1254 // LowerFormalArguments_64.
1256 // Assign locations to each value returned by this call.
1257 SmallVector<CCValAssign, 16> RVLocs;
1258 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
1261 // Set inreg flag manually for codegen generated library calls that
1263 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == nullptr)
1264 CLI.Ins[0].Flags.setInReg();
1266 RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64);
1268 // Copy all of the result registers out of their specified physreg.
1269 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1270 CCValAssign &VA = RVLocs[i];
1271 unsigned Reg = toCallerWindow(VA.getLocReg());
1273 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1274 // reside in the same register in the high and low bits. Reuse the
1275 // CopyFromReg previous node to avoid duplicate copies.
1277 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1278 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1279 RV = Chain.getValue(0);
1281 // But usually we'll create a new CopyFromReg for a different register.
1282 if (!RV.getNode()) {
1283 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1284 Chain = RV.getValue(1);
1285 InGlue = Chain.getValue(2);
1288 // Get the high bits for i32 struct elements.
1289 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1290 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
1291 DAG.getConstant(32, MVT::i32));
1293 // The callee promoted the return value, so insert an Assert?ext SDNode so
1294 // we won't promote the value again in this function.
1295 switch (VA.getLocInfo()) {
1296 case CCValAssign::SExt:
1297 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
1298 DAG.getValueType(VA.getValVT()));
1300 case CCValAssign::ZExt:
1301 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
1302 DAG.getValueType(VA.getValVT()));
1308 // Truncate the register down to the return value type.
1309 if (VA.isExtInLoc())
1310 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
1312 InVals.push_back(RV);
1318 //===----------------------------------------------------------------------===//
1319 // TargetLowering Implementation
1320 //===----------------------------------------------------------------------===//
1322 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1324 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1326 default: llvm_unreachable("Unknown integer condition code!");
1327 case ISD::SETEQ: return SPCC::ICC_E;
1328 case ISD::SETNE: return SPCC::ICC_NE;
1329 case ISD::SETLT: return SPCC::ICC_L;
1330 case ISD::SETGT: return SPCC::ICC_G;
1331 case ISD::SETLE: return SPCC::ICC_LE;
1332 case ISD::SETGE: return SPCC::ICC_GE;
1333 case ISD::SETULT: return SPCC::ICC_CS;
1334 case ISD::SETULE: return SPCC::ICC_LEU;
1335 case ISD::SETUGT: return SPCC::ICC_GU;
1336 case ISD::SETUGE: return SPCC::ICC_CC;
1340 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1342 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1344 default: llvm_unreachable("Unknown fp condition code!");
1346 case ISD::SETOEQ: return SPCC::FCC_E;
1348 case ISD::SETUNE: return SPCC::FCC_NE;
1350 case ISD::SETOLT: return SPCC::FCC_L;
1352 case ISD::SETOGT: return SPCC::FCC_G;
1354 case ISD::SETOLE: return SPCC::FCC_LE;
1356 case ISD::SETOGE: return SPCC::FCC_GE;
1357 case ISD::SETULT: return SPCC::FCC_UL;
1358 case ISD::SETULE: return SPCC::FCC_ULE;
1359 case ISD::SETUGT: return SPCC::FCC_UG;
1360 case ISD::SETUGE: return SPCC::FCC_UGE;
1361 case ISD::SETUO: return SPCC::FCC_U;
1362 case ISD::SETO: return SPCC::FCC_O;
1363 case ISD::SETONE: return SPCC::FCC_LG;
1364 case ISD::SETUEQ: return SPCC::FCC_UE;
1368 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM,
1369 const SparcSubtarget &STI)
1370 : TargetLowering(TM), Subtarget(&STI) {
1371 // Set up the register classes.
1372 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1373 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1374 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1375 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1376 if (Subtarget->is64Bit())
1377 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1379 // Turn FP extload into load/fextend
1380 for (MVT VT : MVT::fp_valuetypes()) {
1381 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1382 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
1385 // Sparc doesn't have i1 sign extending load
1386 for (MVT VT : MVT::integer_valuetypes())
1387 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1389 // Turn FP truncstore into trunc + store.
1390 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1391 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1392 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1394 // Custom legalize GlobalAddress nodes into LO/HI parts.
1395 setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom);
1396 setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom);
1397 setOperationAction(ISD::ConstantPool, getPointerTy(), Custom);
1398 setOperationAction(ISD::BlockAddress, getPointerTy(), Custom);
1400 // Sparc doesn't have sext_inreg, replace them with shl/sra
1401 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1402 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
1403 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1405 // Sparc has no REM or DIVREM operations.
1406 setOperationAction(ISD::UREM, MVT::i32, Expand);
1407 setOperationAction(ISD::SREM, MVT::i32, Expand);
1408 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1409 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1411 // ... nor does SparcV9.
1412 if (Subtarget->is64Bit()) {
1413 setOperationAction(ISD::UREM, MVT::i64, Expand);
1414 setOperationAction(ISD::SREM, MVT::i64, Expand);
1415 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1416 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1419 // Custom expand fp<->sint
1420 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1421 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1422 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
1425 // Custom Expand fp<->uint
1426 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1427 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1428 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
1429 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
1431 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
1432 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
1434 // Sparc has no select or setcc: expand to SELECT_CC.
1435 setOperationAction(ISD::SELECT, MVT::i32, Expand);
1436 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1437 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1438 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1440 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1441 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1442 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1443 setOperationAction(ISD::SETCC, MVT::f128, Expand);
1445 // Sparc doesn't have BRCOND either, it has BR_CC.
1446 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
1447 setOperationAction(ISD::BRIND, MVT::Other, Expand);
1448 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1449 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1450 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1451 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1452 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
1454 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1455 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1456 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1457 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1459 if (Subtarget->is64Bit()) {
1460 setOperationAction(ISD::ADDC, MVT::i64, Custom);
1461 setOperationAction(ISD::ADDE, MVT::i64, Custom);
1462 setOperationAction(ISD::SUBC, MVT::i64, Custom);
1463 setOperationAction(ISD::SUBE, MVT::i64, Custom);
1464 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
1465 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
1466 setOperationAction(ISD::SELECT, MVT::i64, Expand);
1467 setOperationAction(ISD::SETCC, MVT::i64, Expand);
1468 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
1469 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1471 setOperationAction(ISD::CTPOP, MVT::i64,
1472 Subtarget->usePopc() ? Legal : Expand);
1473 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
1475 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1476 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
1477 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1478 setOperationAction(ISD::ROTL , MVT::i64, Expand);
1479 setOperationAction(ISD::ROTR , MVT::i64, Expand);
1480 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
1484 // FIXME: We insert fences for each atomics and generate sub-optimal code
1485 // for PSO/TSO. Also, implement other atomicrmw operations.
1487 setInsertFencesForAtomic(true);
1489 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal);
1490 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32,
1491 (Subtarget->isV9() ? Legal: Expand));
1494 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal);
1496 // Custom Lower Atomic LOAD/STORE
1497 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1498 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1500 if (Subtarget->is64Bit()) {
1501 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal);
1502 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal);
1503 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
1504 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom);
1507 if (!Subtarget->isV9()) {
1508 // SparcV8 does not have FNEGD and FABSD.
1509 setOperationAction(ISD::FNEG, MVT::f64, Custom);
1510 setOperationAction(ISD::FABS, MVT::f64, Custom);
1513 setOperationAction(ISD::FSIN , MVT::f128, Expand);
1514 setOperationAction(ISD::FCOS , MVT::f128, Expand);
1515 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
1516 setOperationAction(ISD::FREM , MVT::f128, Expand);
1517 setOperationAction(ISD::FMA , MVT::f128, Expand);
1518 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1519 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1520 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1521 setOperationAction(ISD::FREM , MVT::f64, Expand);
1522 setOperationAction(ISD::FMA , MVT::f64, Expand);
1523 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1524 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1525 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1526 setOperationAction(ISD::FREM , MVT::f32, Expand);
1527 setOperationAction(ISD::FMA , MVT::f32, Expand);
1528 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1529 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1530 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1531 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1532 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1533 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1534 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1535 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1536 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1537 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1538 setOperationAction(ISD::FPOW , MVT::f128, Expand);
1539 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1540 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1542 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1543 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1544 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1546 // FIXME: Sparc provides these multiplies, but we don't have them yet.
1547 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1548 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1550 if (Subtarget->is64Bit()) {
1551 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
1552 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1553 setOperationAction(ISD::MULHU, MVT::i64, Expand);
1554 setOperationAction(ISD::MULHS, MVT::i64, Expand);
1556 setOperationAction(ISD::UMULO, MVT::i64, Custom);
1557 setOperationAction(ISD::SMULO, MVT::i64, Custom);
1559 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
1560 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
1561 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
1564 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1565 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1566 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1567 setOperationAction(ISD::VAARG , MVT::Other, Custom);
1569 setOperationAction(ISD::TRAP , MVT::Other, Legal);
1571 // Use the default implementation.
1572 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1573 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1574 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
1575 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
1576 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
1578 setExceptionPointerRegister(SP::I0);
1579 setExceptionSelectorRegister(SP::I1);
1581 setStackPointerRegisterToSaveRestore(SP::O6);
1583 setOperationAction(ISD::CTPOP, MVT::i32,
1584 Subtarget->usePopc() ? Legal : Expand);
1586 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1587 setOperationAction(ISD::LOAD, MVT::f128, Legal);
1588 setOperationAction(ISD::STORE, MVT::f128, Legal);
1590 setOperationAction(ISD::LOAD, MVT::f128, Custom);
1591 setOperationAction(ISD::STORE, MVT::f128, Custom);
1594 if (Subtarget->hasHardQuad()) {
1595 setOperationAction(ISD::FADD, MVT::f128, Legal);
1596 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1597 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1598 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1599 setOperationAction(ISD::FSQRT, MVT::f128, Legal);
1600 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1601 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1602 if (Subtarget->isV9()) {
1603 setOperationAction(ISD::FNEG, MVT::f128, Legal);
1604 setOperationAction(ISD::FABS, MVT::f128, Legal);
1606 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1607 setOperationAction(ISD::FABS, MVT::f128, Custom);
1610 if (!Subtarget->is64Bit()) {
1611 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1612 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1613 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1614 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1618 // Custom legalize f128 operations.
1620 setOperationAction(ISD::FADD, MVT::f128, Custom);
1621 setOperationAction(ISD::FSUB, MVT::f128, Custom);
1622 setOperationAction(ISD::FMUL, MVT::f128, Custom);
1623 setOperationAction(ISD::FDIV, MVT::f128, Custom);
1624 setOperationAction(ISD::FSQRT, MVT::f128, Custom);
1625 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1626 setOperationAction(ISD::FABS, MVT::f128, Custom);
1628 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
1629 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
1630 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1632 // Setup Runtime library names.
1633 if (Subtarget->is64Bit()) {
1634 setLibcallName(RTLIB::ADD_F128, "_Qp_add");
1635 setLibcallName(RTLIB::SUB_F128, "_Qp_sub");
1636 setLibcallName(RTLIB::MUL_F128, "_Qp_mul");
1637 setLibcallName(RTLIB::DIV_F128, "_Qp_div");
1638 setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt");
1639 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi");
1640 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui");
1641 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq");
1642 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq");
1643 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox");
1644 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux");
1645 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq");
1646 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq");
1647 setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq");
1648 setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq");
1649 setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos");
1650 setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod");
1652 setLibcallName(RTLIB::ADD_F128, "_Q_add");
1653 setLibcallName(RTLIB::SUB_F128, "_Q_sub");
1654 setLibcallName(RTLIB::MUL_F128, "_Q_mul");
1655 setLibcallName(RTLIB::DIV_F128, "_Q_div");
1656 setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt");
1657 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi");
1658 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou");
1659 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq");
1660 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq");
1661 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1662 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1663 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1664 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1665 setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq");
1666 setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq");
1667 setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos");
1668 setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod");
1672 setMinFunctionAlignment(2);
1674 computeRegisterProperties(Subtarget->getRegisterInfo());
1677 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
1679 default: return nullptr;
1680 case SPISD::CMPICC: return "SPISD::CMPICC";
1681 case SPISD::CMPFCC: return "SPISD::CMPFCC";
1682 case SPISD::BRICC: return "SPISD::BRICC";
1683 case SPISD::BRXCC: return "SPISD::BRXCC";
1684 case SPISD::BRFCC: return "SPISD::BRFCC";
1685 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
1686 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC";
1687 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
1688 case SPISD::Hi: return "SPISD::Hi";
1689 case SPISD::Lo: return "SPISD::Lo";
1690 case SPISD::FTOI: return "SPISD::FTOI";
1691 case SPISD::ITOF: return "SPISD::ITOF";
1692 case SPISD::FTOX: return "SPISD::FTOX";
1693 case SPISD::XTOF: return "SPISD::XTOF";
1694 case SPISD::CALL: return "SPISD::CALL";
1695 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
1696 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
1697 case SPISD::FLUSHW: return "SPISD::FLUSHW";
1698 case SPISD::TLS_ADD: return "SPISD::TLS_ADD";
1699 case SPISD::TLS_LD: return "SPISD::TLS_LD";
1700 case SPISD::TLS_CALL: return "SPISD::TLS_CALL";
1704 EVT SparcTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1707 return VT.changeVectorElementTypeToInteger();
1710 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
1711 /// be zero. Op is expected to be a target specific node. Used by DAG
1713 void SparcTargetLowering::computeKnownBitsForTargetNode
1717 const SelectionDAG &DAG,
1718 unsigned Depth) const {
1719 APInt KnownZero2, KnownOne2;
1720 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
1722 switch (Op.getOpcode()) {
1724 case SPISD::SELECT_ICC:
1725 case SPISD::SELECT_XCC:
1726 case SPISD::SELECT_FCC:
1727 DAG.computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
1728 DAG.computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
1730 // Only known if known in both the LHS and RHS.
1731 KnownOne &= KnownOne2;
1732 KnownZero &= KnownZero2;
1737 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1738 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1739 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1740 ISD::CondCode CC, unsigned &SPCC) {
1741 if (isa<ConstantSDNode>(RHS) &&
1742 cast<ConstantSDNode>(RHS)->isNullValue() &&
1744 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
1745 LHS.getOpcode() == SPISD::SELECT_XCC) &&
1746 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
1747 (LHS.getOpcode() == SPISD::SELECT_FCC &&
1748 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
1749 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1750 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1751 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() &&
1752 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) {
1753 SDValue CMPCC = LHS.getOperand(3);
1754 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1755 LHS = CMPCC.getOperand(0);
1756 RHS = CMPCC.getOperand(1);
1760 // Convert to a target node and set target flags.
1761 SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
1762 SelectionDAG &DAG) const {
1763 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
1764 return DAG.getTargetGlobalAddress(GA->getGlobal(),
1766 GA->getValueType(0),
1767 GA->getOffset(), TF);
1769 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
1770 return DAG.getTargetConstantPool(CP->getConstVal(),
1771 CP->getValueType(0),
1773 CP->getOffset(), TF);
1775 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
1776 return DAG.getTargetBlockAddress(BA->getBlockAddress(),
1781 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
1782 return DAG.getTargetExternalSymbol(ES->getSymbol(),
1783 ES->getValueType(0), TF);
1785 llvm_unreachable("Unhandled address SDNode");
1788 // Split Op into high and low parts according to HiTF and LoTF.
1789 // Return an ADD node combining the parts.
1790 SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
1791 unsigned HiTF, unsigned LoTF,
1792 SelectionDAG &DAG) const {
1794 EVT VT = Op.getValueType();
1795 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
1796 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
1797 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1800 // Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
1801 // or ExternalSymbol SDNode.
1802 SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
1804 EVT VT = getPointerTy();
1806 // Handle PIC mode first.
1807 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1808 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
1809 SDValue HiLo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_GOT22,
1810 SparcMCExpr::VK_Sparc_GOT10, DAG);
1811 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
1812 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo);
1813 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1814 // function has calls.
1815 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1816 MFI->setHasCalls(true);
1817 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
1818 MachinePointerInfo::getGOT(), false, false, false, 0);
1821 // This is one of the absolute code models.
1822 switch(getTargetMachine().getCodeModel()) {
1824 llvm_unreachable("Unsupported absolute code model");
1825 case CodeModel::Small:
1827 return makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
1828 SparcMCExpr::VK_Sparc_LO, DAG);
1829 case CodeModel::Medium: {
1831 SDValue H44 = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_H44,
1832 SparcMCExpr::VK_Sparc_M44, DAG);
1833 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32));
1834 SDValue L44 = withTargetFlags(Op, SparcMCExpr::VK_Sparc_L44, DAG);
1835 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
1836 return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
1838 case CodeModel::Large: {
1840 SDValue Hi = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HH,
1841 SparcMCExpr::VK_Sparc_HM, DAG);
1842 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32));
1843 SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
1844 SparcMCExpr::VK_Sparc_LO, DAG);
1845 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1850 SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
1851 SelectionDAG &DAG) const {
1852 return makeAddress(Op, DAG);
1855 SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
1856 SelectionDAG &DAG) const {
1857 return makeAddress(Op, DAG);
1860 SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
1861 SelectionDAG &DAG) const {
1862 return makeAddress(Op, DAG);
1865 SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1866 SelectionDAG &DAG) const {
1868 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1870 const GlobalValue *GV = GA->getGlobal();
1871 EVT PtrVT = getPointerTy();
1873 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1875 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1876 unsigned HiTF = ((model == TLSModel::GeneralDynamic)
1877 ? SparcMCExpr::VK_Sparc_TLS_GD_HI22
1878 : SparcMCExpr::VK_Sparc_TLS_LDM_HI22);
1879 unsigned LoTF = ((model == TLSModel::GeneralDynamic)
1880 ? SparcMCExpr::VK_Sparc_TLS_GD_LO10
1881 : SparcMCExpr::VK_Sparc_TLS_LDM_LO10);
1882 unsigned addTF = ((model == TLSModel::GeneralDynamic)
1883 ? SparcMCExpr::VK_Sparc_TLS_GD_ADD
1884 : SparcMCExpr::VK_Sparc_TLS_LDM_ADD);
1885 unsigned callTF = ((model == TLSModel::GeneralDynamic)
1886 ? SparcMCExpr::VK_Sparc_TLS_GD_CALL
1887 : SparcMCExpr::VK_Sparc_TLS_LDM_CALL);
1889 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
1890 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
1891 SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo,
1892 withTargetFlags(Op, addTF, DAG));
1894 SDValue Chain = DAG.getEntryNode();
1897 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, true), DL);
1898 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
1899 InFlag = Chain.getValue(1);
1900 SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
1901 SDValue Symbol = withTargetFlags(Op, callTF, DAG);
1903 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1904 SmallVector<SDValue, 4> Ops;
1905 Ops.push_back(Chain);
1906 Ops.push_back(Callee);
1907 Ops.push_back(Symbol);
1908 Ops.push_back(DAG.getRegister(SP::O0, PtrVT));
1909 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
1910 DAG.getMachineFunction(), CallingConv::C);
1911 assert(Mask && "Missing call preserved mask for calling convention");
1912 Ops.push_back(DAG.getRegisterMask(Mask));
1913 Ops.push_back(InFlag);
1914 Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops);
1915 InFlag = Chain.getValue(1);
1916 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, true),
1917 DAG.getIntPtrConstant(0, true), InFlag, DL);
1918 InFlag = Chain.getValue(1);
1919 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag);
1921 if (model != TLSModel::LocalDynamic)
1924 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
1925 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_HIX22, DAG));
1926 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
1927 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_LOX10, DAG));
1928 HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
1929 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo,
1930 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_ADD, DAG));
1933 if (model == TLSModel::InitialExec) {
1934 unsigned ldTF = ((PtrVT == MVT::i64)? SparcMCExpr::VK_Sparc_TLS_IE_LDX
1935 : SparcMCExpr::VK_Sparc_TLS_IE_LD);
1937 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
1939 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1940 // function has calls.
1941 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1942 MFI->setHasCalls(true);
1944 SDValue TGA = makeHiLoPair(Op,
1945 SparcMCExpr::VK_Sparc_TLS_IE_HI22,
1946 SparcMCExpr::VK_Sparc_TLS_IE_LO10, DAG);
1947 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA);
1948 SDValue Offset = DAG.getNode(SPISD::TLS_LD,
1950 withTargetFlags(Op, ldTF, DAG));
1951 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT,
1952 DAG.getRegister(SP::G7, PtrVT), Offset,
1954 SparcMCExpr::VK_Sparc_TLS_IE_ADD, DAG));
1957 assert(model == TLSModel::LocalExec);
1958 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
1959 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_HIX22, DAG));
1960 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
1961 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_LOX10, DAG));
1962 SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
1964 return DAG.getNode(ISD::ADD, DL, PtrVT,
1965 DAG.getRegister(SP::G7, PtrVT), Offset);
1969 SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args,
1970 SDValue Arg, SDLoc DL,
1971 SelectionDAG &DAG) const {
1972 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1973 EVT ArgVT = Arg.getValueType();
1974 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1980 if (ArgTy->isFP128Ty()) {
1981 // Create a stack object and pass the pointer to the library function.
1982 int FI = MFI->CreateStackObject(16, 8, false);
1983 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
1984 Chain = DAG.getStore(Chain,
1988 MachinePointerInfo(),
1994 Entry.Ty = PointerType::getUnqual(ArgTy);
1996 Args.push_back(Entry);
2001 SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
2002 const char *LibFuncName,
2003 unsigned numArgs) const {
2007 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2009 SDValue Callee = DAG.getExternalSymbol(LibFuncName, getPointerTy());
2010 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
2011 Type *RetTyABI = RetTy;
2012 SDValue Chain = DAG.getEntryNode();
2015 if (RetTy->isFP128Ty()) {
2016 // Create a Stack Object to receive the return value of type f128.
2018 int RetFI = MFI->CreateStackObject(16, 8, false);
2019 RetPtr = DAG.getFrameIndex(RetFI, getPointerTy());
2020 Entry.Node = RetPtr;
2021 Entry.Ty = PointerType::getUnqual(RetTy);
2022 if (!Subtarget->is64Bit())
2023 Entry.isSRet = true;
2024 Entry.isReturned = false;
2025 Args.push_back(Entry);
2026 RetTyABI = Type::getVoidTy(*DAG.getContext());
2029 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2030 for (unsigned i = 0, e = numArgs; i != e; ++i) {
2031 Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
2033 TargetLowering::CallLoweringInfo CLI(DAG);
2034 CLI.setDebugLoc(SDLoc(Op)).setChain(Chain)
2035 .setCallee(CallingConv::C, RetTyABI, Callee, std::move(Args), 0);
2037 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2039 // chain is in second result.
2040 if (RetTyABI == RetTy)
2041 return CallInfo.first;
2043 assert (RetTy->isFP128Ty() && "Unexpected return type!");
2045 Chain = CallInfo.second;
2047 // Load RetPtr to get the return value.
2048 return DAG.getLoad(Op.getValueType(),
2052 MachinePointerInfo(),
2053 false, false, false, 8);
2057 SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
2060 SelectionDAG &DAG) const {
2062 const char *LibCall = nullptr;
2063 bool is64Bit = Subtarget->is64Bit();
2065 default: llvm_unreachable("Unhandled conditional code!");
2066 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
2067 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
2068 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
2069 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
2070 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
2071 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
2079 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
2082 SDValue Callee = DAG.getExternalSymbol(LibCall, getPointerTy());
2083 Type *RetTy = Type::getInt32Ty(*DAG.getContext());
2085 SDValue Chain = DAG.getEntryNode();
2086 Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG);
2087 Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG);
2089 TargetLowering::CallLoweringInfo CLI(DAG);
2090 CLI.setDebugLoc(DL).setChain(Chain)
2091 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
2093 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2095 // result is in first, and chain is in second result.
2096 SDValue Result = CallInfo.first;
2100 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
2101 SPCC = SPCC::ICC_NE;
2102 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2104 case SPCC::FCC_UL : {
2105 SDValue Mask = DAG.getTargetConstant(1, Result.getValueType());
2106 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2107 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
2108 SPCC = SPCC::ICC_NE;
2109 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2111 case SPCC::FCC_ULE: {
2112 SDValue RHS = DAG.getTargetConstant(2, Result.getValueType());
2113 SPCC = SPCC::ICC_NE;
2114 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2116 case SPCC::FCC_UG : {
2117 SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
2119 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2121 case SPCC::FCC_UGE: {
2122 SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
2123 SPCC = SPCC::ICC_NE;
2124 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2127 case SPCC::FCC_U : {
2128 SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
2130 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2132 case SPCC::FCC_O : {
2133 SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
2134 SPCC = SPCC::ICC_NE;
2135 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2137 case SPCC::FCC_LG : {
2138 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType());
2139 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2140 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
2141 SPCC = SPCC::ICC_NE;
2142 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2144 case SPCC::FCC_UE : {
2145 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType());
2146 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2147 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
2149 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2155 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
2156 const SparcTargetLowering &TLI) {
2158 if (Op.getOperand(0).getValueType() == MVT::f64)
2159 return TLI.LowerF128Op(Op, DAG,
2160 TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1);
2162 if (Op.getOperand(0).getValueType() == MVT::f32)
2163 return TLI.LowerF128Op(Op, DAG,
2164 TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1);
2166 llvm_unreachable("fpextend with non-float operand!");
2171 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
2172 const SparcTargetLowering &TLI) {
2173 // FP_ROUND on f64 and f32 are legal.
2174 if (Op.getOperand(0).getValueType() != MVT::f128)
2177 if (Op.getValueType() == MVT::f64)
2178 return TLI.LowerF128Op(Op, DAG,
2179 TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1);
2180 if (Op.getValueType() == MVT::f32)
2181 return TLI.LowerF128Op(Op, DAG,
2182 TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1);
2184 llvm_unreachable("fpround to non-float!");
2188 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2189 const SparcTargetLowering &TLI,
2192 EVT VT = Op.getValueType();
2193 assert(VT == MVT::i32 || VT == MVT::i64);
2195 // Expand f128 operations to fp128 abi calls.
2196 if (Op.getOperand(0).getValueType() == MVT::f128
2197 && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2198 const char *libName = TLI.getLibcallName(VT == MVT::i32
2199 ? RTLIB::FPTOSINT_F128_I32
2200 : RTLIB::FPTOSINT_F128_I64);
2201 return TLI.LowerF128Op(Op, DAG, libName, 1);
2204 // Expand if the resulting type is illegal.
2205 if (!TLI.isTypeLegal(VT))
2208 // Otherwise, Convert the fp value to integer in an FP register.
2210 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
2212 Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0));
2214 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
2217 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2218 const SparcTargetLowering &TLI,
2221 EVT OpVT = Op.getOperand(0).getValueType();
2222 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2224 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2226 // Expand f128 operations to fp128 ABI calls.
2227 if (Op.getValueType() == MVT::f128
2228 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) {
2229 const char *libName = TLI.getLibcallName(OpVT == MVT::i32
2230 ? RTLIB::SINTTOFP_I32_F128
2231 : RTLIB::SINTTOFP_I64_F128);
2232 return TLI.LowerF128Op(Op, DAG, libName, 1);
2235 // Expand if the operand type is illegal.
2236 if (!TLI.isTypeLegal(OpVT))
2239 // Otherwise, Convert the int value to FP in an FP register.
2240 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
2241 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2242 return DAG.getNode(opcode, dl, Op.getValueType(), Tmp);
2245 static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
2246 const SparcTargetLowering &TLI,
2249 EVT VT = Op.getValueType();
2251 // Expand if it does not involve f128 or the target has support for
2252 // quad floating point instructions and the resulting type is legal.
2253 if (Op.getOperand(0).getValueType() != MVT::f128 ||
2254 (hasHardQuad && TLI.isTypeLegal(VT)))
2257 assert(VT == MVT::i32 || VT == MVT::i64);
2259 return TLI.LowerF128Op(Op, DAG,
2260 TLI.getLibcallName(VT == MVT::i32
2261 ? RTLIB::FPTOUINT_F128_I32
2262 : RTLIB::FPTOUINT_F128_I64),
2266 static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2267 const SparcTargetLowering &TLI,
2270 EVT OpVT = Op.getOperand(0).getValueType();
2271 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2273 // Expand if it does not involve f128 or the target has support for
2274 // quad floating point instructions and the operand type is legal.
2275 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT)))
2278 return TLI.LowerF128Op(Op, DAG,
2279 TLI.getLibcallName(OpVT == MVT::i32
2280 ? RTLIB::UINTTOFP_I32_F128
2281 : RTLIB::UINTTOFP_I64_F128),
2285 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
2286 const SparcTargetLowering &TLI,
2288 SDValue Chain = Op.getOperand(0);
2289 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2290 SDValue LHS = Op.getOperand(2);
2291 SDValue RHS = Op.getOperand(3);
2292 SDValue Dest = Op.getOperand(4);
2294 unsigned Opc, SPCC = ~0U;
2296 // If this is a br_cc of a "setcc", and if the setcc got lowered into
2297 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2298 LookThroughSetCC(LHS, RHS, CC, SPCC);
2300 // Get the condition flag.
2301 SDValue CompareFlag;
2302 if (LHS.getValueType().isInteger()) {
2303 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2304 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2305 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2306 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
2308 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2309 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2310 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2313 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2314 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2318 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
2319 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
2322 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2323 const SparcTargetLowering &TLI,
2325 SDValue LHS = Op.getOperand(0);
2326 SDValue RHS = Op.getOperand(1);
2327 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2328 SDValue TrueVal = Op.getOperand(2);
2329 SDValue FalseVal = Op.getOperand(3);
2331 unsigned Opc, SPCC = ~0U;
2333 // If this is a select_cc of a "setcc", and if the setcc got lowered into
2334 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2335 LookThroughSetCC(LHS, RHS, CC, SPCC);
2337 SDValue CompareFlag;
2338 if (LHS.getValueType().isInteger()) {
2339 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2340 Opc = LHS.getValueType() == MVT::i32 ?
2341 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
2342 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2344 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2345 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2346 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2347 Opc = SPISD::SELECT_ICC;
2349 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2350 Opc = SPISD::SELECT_FCC;
2351 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2354 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2355 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
2358 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
2359 const SparcTargetLowering &TLI) {
2360 MachineFunction &MF = DAG.getMachineFunction();
2361 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
2363 // Need frame address to find the address of VarArgsFrameIndex.
2364 MF.getFrameInfo()->setFrameAddressIsTaken(true);
2366 // vastart just stores the address of the VarArgsFrameIndex slot into the
2367 // memory location argument.
2370 DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(),
2371 DAG.getRegister(SP::I6, TLI.getPointerTy()),
2372 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset()));
2373 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2374 return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
2375 MachinePointerInfo(SV), false, false, 0);
2378 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
2379 SDNode *Node = Op.getNode();
2380 EVT VT = Node->getValueType(0);
2381 SDValue InChain = Node->getOperand(0);
2382 SDValue VAListPtr = Node->getOperand(1);
2383 EVT PtrVT = VAListPtr.getValueType();
2384 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2386 SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr,
2387 MachinePointerInfo(SV), false, false, false, 0);
2388 // Increment the pointer, VAList, to the next vaarg.
2389 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
2390 DAG.getIntPtrConstant(VT.getSizeInBits()/8));
2391 // Store the incremented VAList to the legalized pointer.
2392 InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr,
2393 VAListPtr, MachinePointerInfo(SV), false, false, 0);
2394 // Load the actual argument out of the pointer VAList.
2395 // We can't count on greater alignment than the word size.
2396 return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
2397 false, false, false,
2398 std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8);
2401 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
2402 const SparcSubtarget *Subtarget) {
2403 SDValue Chain = Op.getOperand(0); // Legalize the chain.
2404 SDValue Size = Op.getOperand(1); // Legalize the size.
2405 EVT VT = Size->getValueType(0);
2408 unsigned SPReg = SP::O6;
2409 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
2410 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
2411 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
2413 // The resultant pointer is actually 16 words from the bottom of the stack,
2414 // to provide a register spill area.
2415 unsigned regSpillArea = Subtarget->is64Bit() ? 128 : 96;
2416 regSpillArea += Subtarget->getStackPointerBias();
2418 SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP,
2419 DAG.getConstant(regSpillArea, VT));
2420 SDValue Ops[2] = { NewVal, Chain };
2421 return DAG.getMergeValues(Ops, dl);
2425 static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
2427 SDValue Chain = DAG.getNode(SPISD::FLUSHW,
2428 dl, MVT::Other, DAG.getEntryNode());
2432 static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
2433 const SparcSubtarget *Subtarget) {
2434 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2435 MFI->setFrameAddressIsTaken(true);
2437 EVT VT = Op.getValueType();
2439 unsigned FrameReg = SP::I6;
2440 unsigned stackBias = Subtarget->getStackPointerBias();
2445 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2446 if (Subtarget->is64Bit())
2447 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2448 DAG.getIntPtrConstant(stackBias));
2452 // flush first to make sure the windowed registers' values are in stack
2453 SDValue Chain = getFLUSHW(Op, DAG);
2454 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
2456 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56;
2459 SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2460 DAG.getIntPtrConstant(Offset));
2461 FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo(),
2462 false, false, false, 0);
2464 if (Subtarget->is64Bit())
2465 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2466 DAG.getIntPtrConstant(stackBias));
2471 static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
2472 const SparcSubtarget *Subtarget) {
2474 uint64_t depth = Op.getConstantOperandVal(0);
2476 return getFRAMEADDR(depth, Op, DAG, Subtarget);
2480 static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
2481 const SparcTargetLowering &TLI,
2482 const SparcSubtarget *Subtarget) {
2483 MachineFunction &MF = DAG.getMachineFunction();
2484 MachineFrameInfo *MFI = MF.getFrameInfo();
2485 MFI->setReturnAddressIsTaken(true);
2487 if (TLI.verifyReturnAddressArgumentIsConstant(Op, DAG))
2490 EVT VT = Op.getValueType();
2492 uint64_t depth = Op.getConstantOperandVal(0);
2496 unsigned RetReg = MF.addLiveIn(SP::I7,
2497 TLI.getRegClassFor(TLI.getPointerTy()));
2498 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
2502 // Need frame address to find return address of the caller.
2503 SDValue FrameAddr = getFRAMEADDR(depth - 1, Op, DAG, Subtarget);
2505 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60;
2506 SDValue Ptr = DAG.getNode(ISD::ADD,
2509 DAG.getIntPtrConstant(Offset));
2510 RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr,
2511 MachinePointerInfo(), false, false, false, 0);
2516 static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode)
2520 assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2521 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2523 // Lower fneg/fabs on f64 to fneg/fabs on f32.
2524 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2525 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2527 SDValue SrcReg64 = Op.getOperand(0);
2528 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2530 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2533 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
2535 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2537 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
2539 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
2544 // Lower a f128 load into two f64 loads.
2545 static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
2548 LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
2549 assert(LdNode && LdNode->getOffset().getOpcode() == ISD::UNDEF
2550 && "Unexpected node type");
2552 unsigned alignment = LdNode->getAlignment();
2556 SDValue Hi64 = DAG.getLoad(MVT::f64,
2559 LdNode->getBasePtr(),
2560 LdNode->getPointerInfo(),
2561 false, false, false, alignment);
2562 EVT addrVT = LdNode->getBasePtr().getValueType();
2563 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2564 LdNode->getBasePtr(),
2565 DAG.getConstant(8, addrVT));
2566 SDValue Lo64 = DAG.getLoad(MVT::f64,
2570 LdNode->getPointerInfo(),
2571 false, false, false, alignment);
2573 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
2574 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
2576 SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2578 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2580 SDValue(InFP128, 0),
2583 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2585 SDValue(InFP128, 0),
2588 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
2589 SDValue(Lo64.getNode(), 1) };
2590 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2591 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2592 return DAG.getMergeValues(Ops, dl);
2595 // Lower a f128 store into two f64 stores.
2596 static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
2598 StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
2599 assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF
2600 && "Unexpected node type");
2601 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
2602 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
2604 SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2609 SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2615 unsigned alignment = StNode->getAlignment();
2619 SDValue OutChains[2];
2620 OutChains[0] = DAG.getStore(StNode->getChain(),
2623 StNode->getBasePtr(),
2624 MachinePointerInfo(),
2625 false, false, alignment);
2626 EVT addrVT = StNode->getBasePtr().getValueType();
2627 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2628 StNode->getBasePtr(),
2629 DAG.getConstant(8, addrVT));
2630 OutChains[1] = DAG.getStore(StNode->getChain(),
2634 MachinePointerInfo(),
2635 false, false, alignment);
2636 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2639 static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
2640 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
2641 && "invalid opcode");
2643 if (Op.getValueType() == MVT::f64)
2644 return LowerF64Op(Op, DAG, Op.getOpcode());
2645 if (Op.getValueType() != MVT::f128)
2648 // Lower fabs/fneg on f128 to fabs/fneg on f64
2649 // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
2652 SDValue SrcReg128 = Op.getOperand(0);
2653 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
2655 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
2658 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
2660 Hi64 = LowerF64Op(Hi64, DAG, Op.getOpcode());
2662 SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2664 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
2666 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
2671 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
2673 if (Op.getValueType() != MVT::i64)
2677 SDValue Src1 = Op.getOperand(0);
2678 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
2679 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
2680 DAG.getConstant(32, MVT::i64));
2681 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi);
2683 SDValue Src2 = Op.getOperand(1);
2684 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2);
2685 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
2686 DAG.getConstant(32, MVT::i64));
2687 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi);
2690 bool hasChain = false;
2691 unsigned hiOpc = Op.getOpcode();
2692 switch (Op.getOpcode()) {
2693 default: llvm_unreachable("Invalid opcode");
2694 case ISD::ADDC: hiOpc = ISD::ADDE; break;
2695 case ISD::ADDE: hasChain = true; break;
2696 case ISD::SUBC: hiOpc = ISD::SUBE; break;
2697 case ISD::SUBE: hasChain = true; break;
2700 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue);
2702 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
2705 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
2707 SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1));
2708 SDValue Carry = Hi.getValue(1);
2710 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
2711 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
2712 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
2713 DAG.getConstant(32, MVT::i64));
2715 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
2716 SDValue Ops[2] = { Dst, Carry };
2717 return DAG.getMergeValues(Ops, dl);
2720 // Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
2721 // in LegalizeDAG.cpp except the order of arguments to the library function.
2722 static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG,
2723 const SparcTargetLowering &TLI)
2725 unsigned opcode = Op.getOpcode();
2726 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode.");
2728 bool isSigned = (opcode == ISD::SMULO);
2730 EVT WideVT = MVT::i128;
2732 SDValue LHS = Op.getOperand(0);
2734 if (LHS.getValueType() != VT)
2737 SDValue ShiftAmt = DAG.getConstant(63, VT);
2739 SDValue RHS = Op.getOperand(1);
2740 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
2741 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt);
2742 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
2744 SDValue MulResult = TLI.makeLibCall(DAG,
2745 RTLIB::MUL_I128, WideVT,
2746 Args, 4, isSigned, dl).first;
2747 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2748 MulResult, DAG.getIntPtrConstant(0));
2749 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2750 MulResult, DAG.getIntPtrConstant(1));
2752 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
2753 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
2755 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, VT),
2758 // MulResult is a node with an illegal type. Because such things are not
2759 // generally permitted during this phase of legalization, ensure that
2760 // nothing is left using the node. The above EXTRACT_ELEMENT nodes should have
2762 assert(MulResult->use_empty() && "Illegally typed node still in use!");
2764 SDValue Ops[2] = { BottomHalf, TopHalf } ;
2765 return DAG.getMergeValues(Ops, dl);
2768 static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
2769 // Monotonic load/stores are legal.
2770 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
2773 // Otherwise, expand with a fence.
2778 SDValue SparcTargetLowering::
2779 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2781 bool hasHardQuad = Subtarget->hasHardQuad();
2782 bool isV9 = Subtarget->isV9();
2784 switch (Op.getOpcode()) {
2785 default: llvm_unreachable("Should not custom lower this!");
2787 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this,
2789 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG,
2791 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2792 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2793 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2794 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2795 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this,
2797 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this,
2799 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this,
2801 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this,
2803 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this,
2805 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this,
2807 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
2808 case ISD::VAARG: return LowerVAARG(Op, DAG);
2809 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
2812 case ISD::LOAD: return LowerF128Load(Op, DAG);
2813 case ISD::STORE: return LowerF128Store(Op, DAG);
2814 case ISD::FADD: return LowerF128Op(Op, DAG,
2815 getLibcallName(RTLIB::ADD_F128), 2);
2816 case ISD::FSUB: return LowerF128Op(Op, DAG,
2817 getLibcallName(RTLIB::SUB_F128), 2);
2818 case ISD::FMUL: return LowerF128Op(Op, DAG,
2819 getLibcallName(RTLIB::MUL_F128), 2);
2820 case ISD::FDIV: return LowerF128Op(Op, DAG,
2821 getLibcallName(RTLIB::DIV_F128), 2);
2822 case ISD::FSQRT: return LowerF128Op(Op, DAG,
2823 getLibcallName(RTLIB::SQRT_F128),1);
2825 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
2826 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this);
2827 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
2831 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
2833 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this);
2834 case ISD::ATOMIC_LOAD:
2835 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
2840 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2841 MachineBasicBlock *BB) const {
2842 switch (MI->getOpcode()) {
2843 default: llvm_unreachable("Unknown SELECT_CC!");
2844 case SP::SELECT_CC_Int_ICC:
2845 case SP::SELECT_CC_FP_ICC:
2846 case SP::SELECT_CC_DFP_ICC:
2847 case SP::SELECT_CC_QFP_ICC:
2848 return expandSelectCC(MI, BB, SP::BCOND);
2849 case SP::SELECT_CC_Int_FCC:
2850 case SP::SELECT_CC_FP_FCC:
2851 case SP::SELECT_CC_DFP_FCC:
2852 case SP::SELECT_CC_QFP_FCC:
2853 return expandSelectCC(MI, BB, SP::FBCOND);
2855 case SP::ATOMIC_LOAD_ADD_32:
2856 return expandAtomicRMW(MI, BB, SP::ADDrr);
2857 case SP::ATOMIC_LOAD_ADD_64:
2858 return expandAtomicRMW(MI, BB, SP::ADDXrr);
2859 case SP::ATOMIC_LOAD_SUB_32:
2860 return expandAtomicRMW(MI, BB, SP::SUBrr);
2861 case SP::ATOMIC_LOAD_SUB_64:
2862 return expandAtomicRMW(MI, BB, SP::SUBXrr);
2863 case SP::ATOMIC_LOAD_AND_32:
2864 return expandAtomicRMW(MI, BB, SP::ANDrr);
2865 case SP::ATOMIC_LOAD_AND_64:
2866 return expandAtomicRMW(MI, BB, SP::ANDXrr);
2867 case SP::ATOMIC_LOAD_OR_32:
2868 return expandAtomicRMW(MI, BB, SP::ORrr);
2869 case SP::ATOMIC_LOAD_OR_64:
2870 return expandAtomicRMW(MI, BB, SP::ORXrr);
2871 case SP::ATOMIC_LOAD_XOR_32:
2872 return expandAtomicRMW(MI, BB, SP::XORrr);
2873 case SP::ATOMIC_LOAD_XOR_64:
2874 return expandAtomicRMW(MI, BB, SP::XORXrr);
2875 case SP::ATOMIC_LOAD_NAND_32:
2876 return expandAtomicRMW(MI, BB, SP::ANDrr);
2877 case SP::ATOMIC_LOAD_NAND_64:
2878 return expandAtomicRMW(MI, BB, SP::ANDXrr);
2880 case SP::ATOMIC_SWAP_64:
2881 return expandAtomicRMW(MI, BB, 0);
2883 case SP::ATOMIC_LOAD_MAX_32:
2884 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_G);
2885 case SP::ATOMIC_LOAD_MAX_64:
2886 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_G);
2887 case SP::ATOMIC_LOAD_MIN_32:
2888 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LE);
2889 case SP::ATOMIC_LOAD_MIN_64:
2890 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LE);
2891 case SP::ATOMIC_LOAD_UMAX_32:
2892 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_GU);
2893 case SP::ATOMIC_LOAD_UMAX_64:
2894 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_GU);
2895 case SP::ATOMIC_LOAD_UMIN_32:
2896 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LEU);
2897 case SP::ATOMIC_LOAD_UMIN_64:
2898 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LEU);
2903 SparcTargetLowering::expandSelectCC(MachineInstr *MI,
2904 MachineBasicBlock *BB,
2905 unsigned BROpcode) const {
2906 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
2907 DebugLoc dl = MI->getDebugLoc();
2908 unsigned CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
2910 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2911 // control-flow pattern. The incoming instruction knows the destination vreg
2912 // to set, the condition code register to branch on, the true/false values to
2913 // select between, and a branch opcode to use.
2914 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2915 MachineFunction::iterator It = BB;
2922 // fallthrough --> copy0MBB
2923 MachineBasicBlock *thisMBB = BB;
2924 MachineFunction *F = BB->getParent();
2925 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2926 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
2927 F->insert(It, copy0MBB);
2928 F->insert(It, sinkMBB);
2930 // Transfer the remainder of BB and its successor edges to sinkMBB.
2931 sinkMBB->splice(sinkMBB->begin(), BB,
2932 std::next(MachineBasicBlock::iterator(MI)),
2934 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
2936 // Add the true and fallthrough blocks as its successors.
2937 BB->addSuccessor(copy0MBB);
2938 BB->addSuccessor(sinkMBB);
2940 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
2943 // %FalseValue = ...
2944 // # fallthrough to sinkMBB
2947 // Update machine-CFG edges
2948 BB->addSuccessor(sinkMBB);
2951 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2954 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
2955 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
2956 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
2958 MI->eraseFromParent(); // The pseudo instruction is gone now.
2963 SparcTargetLowering::expandAtomicRMW(MachineInstr *MI,
2964 MachineBasicBlock *MBB,
2966 unsigned CondCode) const {
2967 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
2968 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2969 DebugLoc DL = MI->getDebugLoc();
2971 // MI is an atomic read-modify-write instruction of the form:
2973 // rd = atomicrmw<op> addr, rs2
2975 // All three operands are registers.
2976 unsigned DestReg = MI->getOperand(0).getReg();
2977 unsigned AddrReg = MI->getOperand(1).getReg();
2978 unsigned Rs2Reg = MI->getOperand(2).getReg();
2980 // SelectionDAG has already inserted memory barriers before and after MI, so
2981 // we simply have to implement the operatiuon in terms of compare-and-swap.
2983 // %val0 = load %addr
2985 // %val = phi %val0, %dest
2986 // %upd = op %val, %rs2
2987 // %dest = cas %addr, %val, %upd
2992 bool is64Bit = SP::I64RegsRegClass.hasSubClassEq(MRI.getRegClass(DestReg));
2993 const TargetRegisterClass *ValueRC =
2994 is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
2995 unsigned Val0Reg = MRI.createVirtualRegister(ValueRC);
2997 BuildMI(*MBB, MI, DL, TII.get(is64Bit ? SP::LDXri : SP::LDri), Val0Reg)
2998 .addReg(AddrReg).addImm(0);
3000 // Split the basic block MBB before MI and insert the loop block in the hole.
3001 MachineFunction::iterator MFI = MBB;
3002 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
3003 MachineFunction *MF = MBB->getParent();
3004 MachineBasicBlock *LoopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3005 MachineBasicBlock *DoneMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3007 MF->insert(MFI, LoopMBB);
3008 MF->insert(MFI, DoneMBB);
3010 // Move MI and following instructions to DoneMBB.
3011 DoneMBB->splice(DoneMBB->begin(), MBB, MI, MBB->end());
3012 DoneMBB->transferSuccessorsAndUpdatePHIs(MBB);
3014 // Connect the CFG again.
3015 MBB->addSuccessor(LoopMBB);
3016 LoopMBB->addSuccessor(LoopMBB);
3017 LoopMBB->addSuccessor(DoneMBB);
3019 // Build the loop block.
3020 unsigned ValReg = MRI.createVirtualRegister(ValueRC);
3021 // Opcode == 0 means try to write Rs2Reg directly (ATOMIC_SWAP).
3022 unsigned UpdReg = (Opcode ? MRI.createVirtualRegister(ValueRC) : Rs2Reg);
3024 BuildMI(LoopMBB, DL, TII.get(SP::PHI), ValReg)
3025 .addReg(Val0Reg).addMBB(MBB)
3026 .addReg(DestReg).addMBB(LoopMBB);
3029 // This is one of the min/max operations. We need a CMPrr followed by a
3031 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(Rs2Reg);
3032 BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg)
3033 .addReg(ValReg).addReg(Rs2Reg).addImm(CondCode);
3034 } else if (Opcode) {
3035 BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg)
3036 .addReg(ValReg).addReg(Rs2Reg);
3039 if (MI->getOpcode() == SP::ATOMIC_LOAD_NAND_32 ||
3040 MI->getOpcode() == SP::ATOMIC_LOAD_NAND_64) {
3041 unsigned TmpReg = UpdReg;
3042 UpdReg = MRI.createVirtualRegister(ValueRC);
3043 BuildMI(LoopMBB, DL, TII.get(SP::XORri), UpdReg).addReg(TmpReg).addImm(-1);
3046 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg)
3047 .addReg(AddrReg).addReg(ValReg).addReg(UpdReg)
3048 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
3049 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg);
3050 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND))
3051 .addMBB(LoopMBB).addImm(SPCC::ICC_NE);
3053 MI->eraseFromParent();
3057 //===----------------------------------------------------------------------===//
3058 // Sparc Inline Assembly Support
3059 //===----------------------------------------------------------------------===//
3061 /// getConstraintType - Given a constraint letter, return the type of
3062 /// constraint it is for this target.
3063 SparcTargetLowering::ConstraintType
3064 SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
3065 if (Constraint.size() == 1) {
3066 switch (Constraint[0]) {
3068 case 'r': return C_RegisterClass;
3074 return TargetLowering::getConstraintType(Constraint);
3077 TargetLowering::ConstraintWeight SparcTargetLowering::
3078 getSingleConstraintMatchWeight(AsmOperandInfo &info,
3079 const char *constraint) const {
3080 ConstraintWeight weight = CW_Invalid;
3081 Value *CallOperandVal = info.CallOperandVal;
3082 // If we don't have a value, we can't do a match,
3083 // but allow it at the lowest weight.
3084 if (!CallOperandVal)
3087 // Look at the constraint type.
3088 switch (*constraint) {
3090 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3093 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
3094 if (isInt<13>(C->getSExtValue()))
3095 weight = CW_Constant;
3102 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3103 /// vector. If it is invalid, don't add anything to Ops.
3104 void SparcTargetLowering::
3105 LowerAsmOperandForConstraint(SDValue Op,
3106 std::string &Constraint,
3107 std::vector<SDValue> &Ops,
3108 SelectionDAG &DAG) const {
3109 SDValue Result(nullptr, 0);
3111 // Only support length 1 constraints for now.
3112 if (Constraint.length() > 1)
3115 char ConstraintLetter = Constraint[0];
3116 switch (ConstraintLetter) {
3119 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3120 if (isInt<13>(C->getSExtValue())) {
3121 Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType());
3128 if (Result.getNode()) {
3129 Ops.push_back(Result);
3132 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3135 std::pair<unsigned, const TargetRegisterClass *>
3136 SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3137 const std::string &Constraint,
3139 if (Constraint.size() == 1) {
3140 switch (Constraint[0]) {
3142 return std::make_pair(0U, &SP::IntRegsRegClass);
3144 } else if (!Constraint.empty() && Constraint.size() <= 5
3145 && Constraint[0] == '{' && *(Constraint.end()-1) == '}') {
3146 // constraint = '{r<d>}'
3147 // Remove the braces from around the name.
3148 StringRef name(Constraint.data()+1, Constraint.size()-2);
3149 // Handle register aliases:
3154 uint64_t intVal = 0;
3155 if (name.substr(0, 1).equals("r")
3156 && !name.substr(1).getAsInteger(10, intVal) && intVal <= 31) {
3157 const char regTypes[] = { 'g', 'o', 'l', 'i' };
3158 char regType = regTypes[intVal/8];
3159 char regIdx = '0' + (intVal % 8);
3160 char tmp[] = { '{', regType, regIdx, '}', 0 };
3161 std::string newConstraint = std::string(tmp);
3162 return TargetLowering::getRegForInlineAsmConstraint(TRI, newConstraint,
3167 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3171 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3172 // The Sparc target isn't yet aware of offsets.
3176 void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
3177 SmallVectorImpl<SDValue>& Results,
3178 SelectionDAG &DAG) const {
3182 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
3184 switch (N->getOpcode()) {
3186 llvm_unreachable("Do not know how to custom type legalize this operation!");
3188 case ISD::FP_TO_SINT:
3189 case ISD::FP_TO_UINT:
3190 // Custom lower only if it involves f128 or i64.
3191 if (N->getOperand(0).getValueType() != MVT::f128
3192 || N->getValueType(0) != MVT::i64)
3194 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3195 ? RTLIB::FPTOSINT_F128_I64
3196 : RTLIB::FPTOUINT_F128_I64);
3198 Results.push_back(LowerF128Op(SDValue(N, 0),
3200 getLibcallName(libCall),
3204 case ISD::SINT_TO_FP:
3205 case ISD::UINT_TO_FP:
3206 // Custom lower only if it involves f128 or i64.
3207 if (N->getValueType(0) != MVT::f128
3208 || N->getOperand(0).getValueType() != MVT::i64)
3211 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
3212 ? RTLIB::SINTTOFP_I64_F128
3213 : RTLIB::UINTTOFP_I64_F128);
3215 Results.push_back(LowerF128Op(SDValue(N, 0),
3217 getLibcallName(libCall),