1 //===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8TargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Support/Debug.h"
29 //===----------------------------------------------------------------------===//
30 // TargetLowering Implementation
31 //===----------------------------------------------------------------------===//
35 FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END,
36 CMPICC, // Compare two GPR operands, set icc.
37 CMPFCC, // Compare two FP operands, set fcc.
38 BRICC, // Branch to dest on icc condition
39 BRFCC, // Branch to dest on fcc condition
41 Hi, Lo, // Hi/Lo operations, typically on a global address.
43 FTOI, // FP to Int within a FP register.
44 ITOF, // Int to FP within a FP register.
46 SELECT_ICC, // Select between two values using the current ICC flags.
47 SELECT_FCC, // Select between two values using the current FCC flags.
49 RET_FLAG, // Return with a flag operand.
54 class SparcV8TargetLowering : public TargetLowering {
55 int VarArgsFrameOffset; // Frame offset to start of varargs area.
57 SparcV8TargetLowering(TargetMachine &TM);
58 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
59 virtual std::vector<SDOperand>
60 LowerArguments(Function &F, SelectionDAG &DAG);
61 virtual std::pair<SDOperand, SDOperand>
62 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
64 bool isTailCall, SDOperand Callee, ArgListTy &Args,
67 virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
69 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
70 Value *VAListV, SelectionDAG &DAG);
71 virtual std::pair<SDOperand,SDOperand>
72 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
73 const Type *ArgTy, SelectionDAG &DAG);
74 virtual std::pair<SDOperand, SDOperand>
75 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
77 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
78 MachineBasicBlock *MBB);
82 SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
83 : TargetLowering(TM) {
85 // Set up the register classes.
86 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
87 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
88 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
90 // Custom legalize GlobalAddress nodes into LO/HI parts.
91 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
92 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
94 // Sparc doesn't have sext_inreg, replace them with shl/sra
95 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
96 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
97 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
99 // Sparc has no REM operation.
100 setOperationAction(ISD::UREM, MVT::i32, Expand);
101 setOperationAction(ISD::SREM, MVT::i32, Expand);
103 // Custom expand fp<->sint
104 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
105 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
108 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
109 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
111 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
112 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
114 // Turn FP extload into load/fextend
115 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
117 // Sparc has no select or setcc: expand to SELECT_CC.
118 setOperationAction(ISD::SELECT, MVT::i32, Expand);
119 setOperationAction(ISD::SELECT, MVT::f32, Expand);
120 setOperationAction(ISD::SELECT, MVT::f64, Expand);
121 setOperationAction(ISD::SETCC, MVT::i32, Expand);
122 setOperationAction(ISD::SETCC, MVT::f32, Expand);
123 setOperationAction(ISD::SETCC, MVT::f64, Expand);
125 // Sparc doesn't have BRCOND either, it has BR_CC.
126 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
127 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
128 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
129 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
130 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
131 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
133 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
134 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
135 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
137 // V8 has no intrinsics for these particular operations.
138 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
139 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
140 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
142 setOperationAction(ISD::FSIN , MVT::f64, Expand);
143 setOperationAction(ISD::FCOS , MVT::f64, Expand);
144 setOperationAction(ISD::FSIN , MVT::f32, Expand);
145 setOperationAction(ISD::FCOS , MVT::f32, Expand);
146 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
147 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
148 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
150 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
151 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
152 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
154 // We don't have line number support yet.
155 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
156 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
158 computeRegisterProperties();
161 /// LowerArguments - V8 uses a very simple ABI, where all values are passed in
162 /// either one or two GPRs, including FP values. TODO: we should pass FP values
163 /// in FP registers for fastcc functions.
164 std::vector<SDOperand>
165 SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
166 MachineFunction &MF = DAG.getMachineFunction();
167 SSARegMap *RegMap = MF.getSSARegMap();
168 std::vector<SDOperand> ArgValues;
170 static const unsigned ArgRegs[] = {
171 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
174 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
175 unsigned ArgOffset = 68;
177 SDOperand Root = DAG.getRoot();
178 std::vector<SDOperand> OutChains;
180 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
181 MVT::ValueType ObjectVT = getValueType(I->getType());
184 default: assert(0 && "Unhandled argument type!");
189 if (I->use_empty()) { // Argument is dead.
190 if (CurArgReg < ArgRegEnd) ++CurArgReg;
191 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
192 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
193 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
194 MF.addLiveIn(*CurArgReg++, VReg);
195 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
196 if (ObjectVT != MVT::i32) {
197 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
199 Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
200 DAG.getValueType(ObjectVT));
201 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
203 ArgValues.push_back(Arg);
205 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
206 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
208 if (ObjectVT == MVT::i32) {
209 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
212 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
214 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
215 DAG.getSrcValue(0), ObjectVT);
217 ArgValues.push_back(Load);
223 if (I->use_empty()) { // Argument is dead.
224 if (CurArgReg < ArgRegEnd) ++CurArgReg;
225 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
226 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
227 // FP value is passed in an integer register.
228 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
229 MF.addLiveIn(*CurArgReg++, VReg);
230 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
232 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
233 ArgValues.push_back(Arg);
240 if (I->use_empty()) { // Argument is dead.
241 if (CurArgReg < ArgRegEnd) ++CurArgReg;
242 if (CurArgReg < ArgRegEnd) ++CurArgReg;
243 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
244 } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
245 ((CurArgReg-ArgRegs) & 1) == 0) {
246 // If this is a double argument and the whole thing lives on the stack,
247 // and the argument is aligned, load the double straight from the stack.
248 // We can't do a load in cases like void foo([6ints], int,double),
249 // because the double wouldn't be aligned!
250 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
251 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
252 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
253 DAG.getSrcValue(0)));
256 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
257 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
258 MF.addLiveIn(*CurArgReg++, VRegHi);
259 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
261 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
262 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
263 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
267 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
268 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
269 MF.addLiveIn(*CurArgReg++, VRegLo);
270 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
272 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
273 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
274 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
277 // Compose the two halves together into an i64 unit.
278 SDOperand WholeValue =
279 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
281 // If we want a double, do a bit convert.
282 if (ObjectVT == MVT::f64)
283 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
285 ArgValues.push_back(WholeValue);
292 // Store remaining ArgRegs to the stack if this is a varargs function.
293 if (F.getFunctionType()->isVarArg()) {
294 // Remember the vararg offset for the va_start implementation.
295 VarArgsFrameOffset = ArgOffset;
297 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
298 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
299 MF.addLiveIn(*CurArgReg, VReg);
300 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
302 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
303 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
305 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
306 Arg, FIPtr, DAG.getSrcValue(0)));
311 if (!OutChains.empty())
312 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
314 // Finally, inform the code generator which regs we return values in.
315 switch (getValueType(F.getReturnType())) {
316 default: assert(0 && "Unknown type!");
317 case MVT::isVoid: break;
322 MF.addLiveOut(V8::I0);
325 MF.addLiveOut(V8::I0);
326 MF.addLiveOut(V8::I1);
329 MF.addLiveOut(V8::F0);
332 MF.addLiveOut(V8::D0);
339 std::pair<SDOperand, SDOperand>
340 SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
341 bool isVarArg, unsigned CC,
342 bool isTailCall, SDOperand Callee,
343 ArgListTy &Args, SelectionDAG &DAG) {
344 MachineFunction &MF = DAG.getMachineFunction();
345 // Count the size of the outgoing arguments.
346 unsigned ArgsSize = 0;
347 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
348 switch (getValueType(Args[i].second)) {
349 default: assert(0 && "Unknown value type!");
364 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
368 // Keep stack frames 8-byte aligned.
369 ArgsSize = (ArgsSize+7) & ~7;
371 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
372 DAG.getConstant(ArgsSize, getPointerTy()));
374 SDOperand StackPtr, NullSV;
375 std::vector<SDOperand> Stores;
376 std::vector<SDOperand> RegValuesToPass;
377 unsigned ArgOffset = 68;
378 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
379 SDOperand Val = Args[i].first;
380 MVT::ValueType ObjectVT = Val.getValueType();
381 SDOperand ValToStore;
384 default: assert(0 && "Unhandled argument type!");
388 // Promote the integer to 32-bits. If the input type is signed, use a
389 // sign extend, otherwise use a zero extend.
390 if (Args[i].second->isSigned())
391 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
393 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
398 if (RegValuesToPass.size() >= 6) {
401 RegValuesToPass.push_back(Val);
406 if (RegValuesToPass.size() >= 6) {
409 // Convert this to a FP value in an int reg.
410 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
411 RegValuesToPass.push_back(Val);
416 // If we can store this directly into the outgoing slot, do so. We can
417 // do this when all ArgRegs are used and if the outgoing slot is aligned.
418 if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
423 // Otherwise, convert this to a FP value in int regs.
424 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
428 if (RegValuesToPass.size() >= 6) {
429 ValToStore = Val; // Whole thing is passed in memory.
433 // Split the value into top and bottom part. Top part goes in a reg.
434 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
435 DAG.getConstant(1, MVT::i32));
436 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
437 DAG.getConstant(0, MVT::i32));
438 RegValuesToPass.push_back(Hi);
440 if (RegValuesToPass.size() >= 6) {
445 RegValuesToPass.push_back(Lo);
450 if (ValToStore.Val) {
452 StackPtr = DAG.getRegister(V8::O6, MVT::i32);
453 NullSV = DAG.getSrcValue(NULL);
455 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
456 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
457 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
458 ValToStore, PtrOff, NullSV));
460 ArgOffset += ObjSize;
463 // Emit all stores, make sure the occur before any copies into physregs.
465 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
467 static const unsigned ArgRegs[] = {
468 V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5
471 // Build a sequence of copy-to-reg nodes chained together with token chain
472 // and flag operands which copy the outgoing args into O[0-5].
474 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
475 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
476 InFlag = Chain.getValue(1);
479 std::vector<MVT::ValueType> RetVals;
480 RetVals.push_back(MVT::Other);
481 RetVals.push_back(MVT::Flag);
483 // If the callee is a GlobalAddress node (quite common, every direct call is)
484 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
485 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
486 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
488 std::vector<MVT::ValueType> NodeTys;
489 NodeTys.push_back(MVT::Other); // Returns a chain
490 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
492 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0);
494 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0);
495 InFlag = Chain.getValue(1);
497 MVT::ValueType RetTyVT = getValueType(RetTy);
499 if (RetTyVT != MVT::isVoid) {
501 default: assert(0 && "Unknown value type to return!");
505 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
506 Chain = RetVal.getValue(1);
508 // Add a note to keep track of whether it is sign or zero extended.
509 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
510 MVT::i32, RetVal, DAG.getValueType(RetTyVT));
511 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
514 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
515 Chain = RetVal.getValue(1);
518 RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag);
519 Chain = RetVal.getValue(1);
522 RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag);
523 Chain = RetVal.getValue(1);
526 SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag);
527 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32,
529 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
530 Chain = Hi.getValue(1);
535 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
536 DAG.getConstant(ArgsSize, getPointerTy()));
538 return std::make_pair(RetVal, Chain);
541 SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
544 switch (Op.getValueType()) {
545 default: assert(0 && "Unknown type to return!");
547 Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand());
550 Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand());
553 Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand());
556 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
557 DAG.getConstant(1, MVT::i32));
558 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
559 DAG.getConstant(0, MVT::i32));
560 Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand());
561 Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1));
564 return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
567 SDOperand SparcV8TargetLowering::
568 LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV,
571 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
572 DAG.getRegister(V8::I6, MVT::i32),
573 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
574 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Offset,
575 VAListP, DAG.getSrcValue(VAListV));
578 std::pair<SDOperand,SDOperand> SparcV8TargetLowering::
579 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
580 const Type *ArgTy, SelectionDAG &DAG) {
581 assert(0 && "Unimp");
585 std::pair<SDOperand, SDOperand> SparcV8TargetLowering::
586 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
588 assert(0 && "Unimp");
592 SDOperand SparcV8TargetLowering::
593 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
594 switch (Op.getOpcode()) {
595 default: assert(0 && "Should not custom lower this!");
596 case ISD::GlobalAddress: {
597 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
598 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
599 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
600 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
601 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
603 case ISD::ConstantPool: {
604 Constant *C = cast<ConstantPoolSDNode>(Op)->get();
605 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32);
606 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP);
607 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
608 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
610 case ISD::FP_TO_SINT:
611 // Convert the fp value to integer in an FP register.
612 assert(Op.getValueType() == MVT::i32);
613 Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0));
614 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
615 case ISD::SINT_TO_FP: {
616 assert(Op.getOperand(0).getValueType() == MVT::i32);
617 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op);
618 // Convert the int value to FP in an FP register.
619 return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Op);
622 SDOperand Chain = Op.getOperand(0);
623 SDOperand CC = Op.getOperand(1);
624 SDOperand LHS = Op.getOperand(2);
625 SDOperand RHS = Op.getOperand(3);
626 SDOperand Dest = Op.getOperand(4);
628 // Get the condition flag.
629 if (LHS.getValueType() == MVT::i32) {
630 SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS);
631 return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
633 SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
634 return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
637 case ISD::SELECT_CC: {
638 SDOperand LHS = Op.getOperand(0);
639 SDOperand RHS = Op.getOperand(1);
640 unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
641 SDOperand TrueVal = Op.getOperand(2);
642 SDOperand FalseVal = Op.getOperand(3);
645 Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC;
646 SDOperand CompareFlag = DAG.getNode(Opc, MVT::Flag, LHS, RHS);
648 Opc = LHS.getValueType() == MVT::i32 ?
649 V8ISD::SELECT_ICC : V8ISD::SELECT_FCC;
650 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
651 DAG.getConstant(CC, MVT::i32), CompareFlag);
657 SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
658 MachineBasicBlock *BB) {
660 // Figure out the conditional branch opcode to use for this select_cc.
661 switch (MI->getOpcode()) {
662 default: assert(0 && "Unknown SELECT_CC!");
663 case V8::SELECT_CC_Int_ICC:
664 case V8::SELECT_CC_FP_ICC:
665 case V8::SELECT_CC_DFP_ICC:
667 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
668 default: assert(0 && "Unknown integer condition code!");
669 case ISD::SETEQ: BROpcode = V8::BE; break;
670 case ISD::SETNE: BROpcode = V8::BNE; break;
671 case ISD::SETLT: BROpcode = V8::BL; break;
672 case ISD::SETGT: BROpcode = V8::BG; break;
673 case ISD::SETLE: BROpcode = V8::BLE; break;
674 case ISD::SETGE: BROpcode = V8::BGE; break;
675 case ISD::SETULT: BROpcode = V8::BCS; break;
676 case ISD::SETULE: BROpcode = V8::BLEU; break;
677 case ISD::SETUGT: BROpcode = V8::BGU; break;
678 case ISD::SETUGE: BROpcode = V8::BCC; break;
681 case V8::SELECT_CC_Int_FCC:
682 case V8::SELECT_CC_FP_FCC:
683 case V8::SELECT_CC_DFP_FCC:
685 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
686 default: assert(0 && "Unknown fp condition code!");
687 case ISD::SETEQ: BROpcode = V8::FBE; break;
688 case ISD::SETNE: BROpcode = V8::FBNE; break;
689 case ISD::SETLT: BROpcode = V8::FBL; break;
690 case ISD::SETGT: BROpcode = V8::FBG; break;
691 case ISD::SETLE: BROpcode = V8::FBLE; break;
692 case ISD::SETGE: BROpcode = V8::FBGE; break;
693 case ISD::SETULT: BROpcode = V8::FBUL; break;
694 case ISD::SETULE: BROpcode = V8::FBULE; break;
695 case ISD::SETUGT: BROpcode = V8::FBUG; break;
696 case ISD::SETUGE: BROpcode = V8::FBUGE; break;
697 case ISD::SETUO: BROpcode = V8::FBU; break;
698 case ISD::SETO: BROpcode = V8::FBO; break;
699 case ISD::SETONE: BROpcode = V8::FBLG; break;
700 case ISD::SETUEQ: BROpcode = V8::FBUE; break;
705 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
706 // control-flow pattern. The incoming instruction knows the destination vreg
707 // to set, the condition code register to branch on, the true/false values to
708 // select between, and a branch opcode to use.
709 const BasicBlock *LLVM_BB = BB->getBasicBlock();
710 ilist<MachineBasicBlock>::iterator It = BB;
717 // fallthrough --> copy0MBB
718 MachineBasicBlock *thisMBB = BB;
719 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
720 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
721 BuildMI(BB, BROpcode, 1).addMBB(sinkMBB);
722 MachineFunction *F = BB->getParent();
723 F->getBasicBlockList().insert(It, copy0MBB);
724 F->getBasicBlockList().insert(It, sinkMBB);
725 // Update machine-CFG edges
726 BB->addSuccessor(copy0MBB);
727 BB->addSuccessor(sinkMBB);
731 // # fallthrough to sinkMBB
734 // Update machine-CFG edges
735 BB->addSuccessor(sinkMBB);
738 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
741 BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg())
742 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
743 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
745 delete MI; // The pseudo instruction is gone now.
749 //===----------------------------------------------------------------------===//
750 // Instruction Selector Implementation
751 //===----------------------------------------------------------------------===//
753 //===--------------------------------------------------------------------===//
754 /// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
755 /// instructions for SelectionDAG operations.
758 class SparcV8DAGToDAGISel : public SelectionDAGISel {
759 SparcV8TargetLowering V8Lowering;
761 SparcV8DAGToDAGISel(TargetMachine &TM)
762 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
764 SDOperand Select(SDOperand Op);
766 // Complex Pattern Selectors.
767 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
768 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
770 /// InstructionSelectBasicBlock - This callback is invoked by
771 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
772 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
774 virtual const char *getPassName() const {
775 return "PowerPC DAG->DAG Pattern Instruction Selection";
778 // Include the pieces autogenerated from the target description.
779 #include "SparcV8GenDAGISel.inc"
781 } // end anonymous namespace
783 /// InstructionSelectBasicBlock - This callback is invoked by
784 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
785 void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
788 // Select target instructions for the DAG.
789 DAG.setRoot(Select(DAG.getRoot()));
791 DAG.RemoveDeadNodes();
793 // Emit machine code to BB.
794 ScheduleAndEmitDAG(DAG);
797 bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
799 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
800 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
801 Offset = CurDAG->getTargetConstant(0, MVT::i32);
805 if (Addr.getOpcode() == ISD::ADD) {
806 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
807 if (Predicate_simm13(CN)) {
808 if (FrameIndexSDNode *FIN =
809 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
810 // Constant offset from frame ref.
811 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
813 Base = Select(Addr.getOperand(0));
815 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
819 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
820 Base = Select(Addr.getOperand(1));
821 Offset = Addr.getOperand(0).getOperand(0);
824 if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
825 Base = Select(Addr.getOperand(0));
826 Offset = Addr.getOperand(1).getOperand(0);
831 Offset = CurDAG->getTargetConstant(0, MVT::i32);
835 bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
837 if (Addr.getOpcode() == ISD::FrameIndex) return false;
838 if (Addr.getOpcode() == ISD::ADD) {
839 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
840 Predicate_simm13(Addr.getOperand(1).Val))
841 return false; // Let the reg+imm pattern catch this!
842 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
843 Addr.getOperand(1).getOpcode() == V8ISD::Lo)
844 return false; // Let the reg+imm pattern catch this!
845 R1 = Select(Addr.getOperand(0));
846 R2 = Select(Addr.getOperand(1));
851 R2 = CurDAG->getRegister(V8::G0, MVT::i32);
855 SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
857 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
858 N->getOpcode() < V8ISD::FIRST_NUMBER)
859 return Op; // Already selected.
860 // If this has already been converted, use it.
861 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
862 if (CGMI != CodeGenMap.end()) return CGMI->second;
864 switch (N->getOpcode()) {
866 case ISD::Register: return Op;
867 case ISD::FrameIndex: {
868 int FI = cast<FrameIndexSDNode>(N)->getIndex();
870 return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32,
871 CurDAG->getTargetFrameIndex(FI, MVT::i32),
872 CurDAG->getTargetConstant(0, MVT::i32));
873 return CodeGenMap[Op] =
874 CurDAG->getTargetNode(V8::ADDri, MVT::i32,
875 CurDAG->getTargetFrameIndex(FI, MVT::i32),
876 CurDAG->getTargetConstant(0, MVT::i32));
878 case V8ISD::CMPICC: {
879 // FIXME: Handle compare with immediate.
880 SDOperand LHS = Select(N->getOperand(0));
881 SDOperand RHS = Select(N->getOperand(1));
882 SDOperand Result = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
884 return CodeGenMap[Op] = Result.getValue(1);
886 case ISD::ADD_PARTS: {
887 SDOperand LHSL = Select(N->getOperand(0));
888 SDOperand LHSH = Select(N->getOperand(1));
889 SDOperand RHSL = Select(N->getOperand(2));
890 SDOperand RHSH = Select(N->getOperand(3));
891 // FIXME, handle immediate RHS.
892 SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag,
894 SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH,
896 CodeGenMap[SDOperand(N, 0)] = Low;
897 CodeGenMap[SDOperand(N, 1)] = Hi;
898 return Op.ResNo ? Hi : Low;
900 case ISD::SUB_PARTS: {
901 SDOperand LHSL = Select(N->getOperand(0));
902 SDOperand LHSH = Select(N->getOperand(1));
903 SDOperand RHSL = Select(N->getOperand(2));
904 SDOperand RHSH = Select(N->getOperand(3));
905 // FIXME, handle immediate RHS.
906 SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
908 SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH,
910 CodeGenMap[SDOperand(N, 0)] = Low;
911 CodeGenMap[SDOperand(N, 1)] = Hi;
912 return Op.ResNo ? Hi : Low;
916 // FIXME: should use a custom expander to expose the SRA to the dag.
917 SDOperand DivLHS = Select(N->getOperand(0));
918 SDOperand DivRHS = Select(N->getOperand(1));
920 // Set the Y register to the high-part.
922 if (N->getOpcode() == ISD::SDIV) {
923 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
924 CurDAG->getTargetConstant(31, MVT::i32));
926 TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
928 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
929 CurDAG->getRegister(V8::G0, MVT::i32));
931 // FIXME: Handle div by immediate.
932 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
933 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
937 // FIXME: Handle mul by immediate.
938 SDOperand MulLHS = Select(N->getOperand(0));
939 SDOperand MulRHS = Select(N->getOperand(1));
940 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
941 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
943 // The high part is in the Y register.
944 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
947 // FIXME: This is a workaround for a bug in tblgen.
948 { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
949 // Emits: (CALL:void (tglobaladdr:i32):$dst)
950 // Pattern complexity = 2 cost = 1
951 SDOperand N1 = N->getOperand(1);
952 if (N1.getOpcode() != ISD::TargetGlobalAddress &&
953 N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail;
954 SDOperand InFlag = SDOperand(0, 0);
955 SDOperand Chain = N->getOperand(0);
957 Chain = Select(Chain);
959 if (N->getNumOperands() == 3) {
960 InFlag = Select(N->getOperand(2));
961 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
964 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
967 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0);
968 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1);
969 return Result.getValue(Op.ResNo);
975 return SelectCode(Op);
979 /// createPPCISelDag - This pass converts a legalized DAG into a
980 /// PowerPC-specific DAG, ready for instruction scheduling.
982 FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
983 return new SparcV8DAGToDAGISel(TM);