1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SPARC target.
12 //===----------------------------------------------------------------------===//
15 #include "SparcTargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Support/Debug.h"
30 //===----------------------------------------------------------------------===//
31 // TargetLowering Implementation
32 //===----------------------------------------------------------------------===//
36 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
37 CMPICC, // Compare two GPR operands, set icc.
38 CMPFCC, // Compare two FP operands, set fcc.
39 BRICC, // Branch to dest on icc condition
40 BRFCC, // Branch to dest on fcc condition
41 SELECT_ICC, // Select between two values using the current ICC flags.
42 SELECT_FCC, // Select between two values using the current FCC flags.
44 Hi, Lo, // Hi/Lo operations, typically on a global address.
46 FTOI, // FP to Int within a FP register.
47 ITOF, // Int to FP within a FP register.
49 CALL, // A call instruction.
50 RET_FLAG, // Return with a flag operand.
54 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
56 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
58 default: assert(0 && "Unknown integer condition code!");
59 case ISD::SETEQ: return SPCC::ICC_E;
60 case ISD::SETNE: return SPCC::ICC_NE;
61 case ISD::SETLT: return SPCC::ICC_L;
62 case ISD::SETGT: return SPCC::ICC_G;
63 case ISD::SETLE: return SPCC::ICC_LE;
64 case ISD::SETGE: return SPCC::ICC_GE;
65 case ISD::SETULT: return SPCC::ICC_CS;
66 case ISD::SETULE: return SPCC::ICC_LEU;
67 case ISD::SETUGT: return SPCC::ICC_GU;
68 case ISD::SETUGE: return SPCC::ICC_CC;
72 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
74 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
76 default: assert(0 && "Unknown fp condition code!");
77 case ISD::SETEQ: return SPCC::FCC_E;
78 case ISD::SETNE: return SPCC::FCC_NE;
79 case ISD::SETLT: return SPCC::FCC_L;
80 case ISD::SETGT: return SPCC::FCC_G;
81 case ISD::SETLE: return SPCC::FCC_LE;
82 case ISD::SETGE: return SPCC::FCC_GE;
83 case ISD::SETULT: return SPCC::FCC_UL;
84 case ISD::SETULE: return SPCC::FCC_ULE;
85 case ISD::SETUGT: return SPCC::FCC_UG;
86 case ISD::SETUGE: return SPCC::FCC_UGE;
87 case ISD::SETUO: return SPCC::FCC_U;
88 case ISD::SETO: return SPCC::FCC_O;
89 case ISD::SETONE: return SPCC::FCC_LG;
90 case ISD::SETUEQ: return SPCC::FCC_UE;
95 class SparcTargetLowering : public TargetLowering {
96 int VarArgsFrameOffset; // Frame offset to start of varargs area.
98 SparcTargetLowering(TargetMachine &TM);
99 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
101 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
102 /// be zero. Op is expected to be a target specific node. Used by DAG
104 virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op,
105 uint64_t Mask) const;
107 virtual std::vector<SDOperand>
108 LowerArguments(Function &F, SelectionDAG &DAG);
109 virtual std::pair<SDOperand, SDOperand>
110 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
112 bool isTailCall, SDOperand Callee, ArgListTy &Args,
114 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
115 MachineBasicBlock *MBB);
117 virtual const char *getTargetNodeName(unsigned Opcode) const;
121 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
122 : TargetLowering(TM) {
124 // Set up the register classes.
125 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
126 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
127 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
129 // Custom legalize GlobalAddress nodes into LO/HI parts.
130 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
131 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
133 // Sparc doesn't have sext_inreg, replace them with shl/sra
134 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
135 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
136 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
138 // Sparc has no REM operation.
139 setOperationAction(ISD::UREM, MVT::i32, Expand);
140 setOperationAction(ISD::SREM, MVT::i32, Expand);
142 // Custom expand fp<->sint
143 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
144 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
147 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
148 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
150 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
151 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
153 // Turn FP extload into load/fextend
154 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
156 // Sparc has no select or setcc: expand to SELECT_CC.
157 setOperationAction(ISD::SELECT, MVT::i32, Expand);
158 setOperationAction(ISD::SELECT, MVT::f32, Expand);
159 setOperationAction(ISD::SELECT, MVT::f64, Expand);
160 setOperationAction(ISD::SETCC, MVT::i32, Expand);
161 setOperationAction(ISD::SETCC, MVT::f32, Expand);
162 setOperationAction(ISD::SETCC, MVT::f64, Expand);
164 // Sparc doesn't have BRCOND either, it has BR_CC.
165 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
166 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
167 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
168 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
169 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
170 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
172 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
173 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
174 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
176 // SPARC has no intrinsics for these particular operations.
177 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
178 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
179 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
181 setOperationAction(ISD::FSIN , MVT::f64, Expand);
182 setOperationAction(ISD::FCOS , MVT::f64, Expand);
183 setOperationAction(ISD::FSIN , MVT::f32, Expand);
184 setOperationAction(ISD::FCOS , MVT::f32, Expand);
185 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
186 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
187 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
188 setOperationAction(ISD::ROTL , MVT::i32, Expand);
189 setOperationAction(ISD::ROTR , MVT::i32, Expand);
190 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
192 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
193 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
194 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
196 // We don't have line number support yet.
197 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
198 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
199 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
201 // RET must be custom lowered, to meet ABI requirements
202 setOperationAction(ISD::RET , MVT::Other, Custom);
204 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
205 setOperationAction(ISD::VASTART , MVT::Other, Custom);
206 // VAARG needs to be lowered to not do unaligned accesses for doubles.
207 setOperationAction(ISD::VAARG , MVT::Other, Custom);
209 // Use the default implementation.
210 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
211 setOperationAction(ISD::VAEND , MVT::Other, Expand);
212 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
213 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
214 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
216 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
217 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
219 setStackPointerRegisterToSaveRestore(SP::O6);
221 if (TM.getSubtarget<SparcSubtarget>().isV9()) {
222 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
225 computeRegisterProperties();
228 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
231 case SPISD::CMPICC: return "SPISD::CMPICC";
232 case SPISD::CMPFCC: return "SPISD::CMPFCC";
233 case SPISD::BRICC: return "SPISD::BRICC";
234 case SPISD::BRFCC: return "SPISD::BRFCC";
235 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
236 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
237 case SPISD::Hi: return "SPISD::Hi";
238 case SPISD::Lo: return "SPISD::Lo";
239 case SPISD::FTOI: return "SPISD::FTOI";
240 case SPISD::ITOF: return "SPISD::ITOF";
241 case SPISD::CALL: return "SPISD::CALL";
242 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
246 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
247 /// be zero. Op is expected to be a target specific node. Used by DAG
249 bool SparcTargetLowering::
250 isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask) const {
251 switch (Op.getOpcode()) {
252 default: return false;
253 case SPISD::SELECT_ICC:
254 case SPISD::SELECT_FCC:
255 assert(MVT::isInteger(Op.getValueType()) && "Not an integer select!");
256 // These operations are masked zero if both the left and the right are zero.
257 return MaskedValueIsZero(Op.getOperand(0), Mask) &&
258 MaskedValueIsZero(Op.getOperand(1), Mask);
263 /// LowerArguments - V8 uses a very simple ABI, where all values are passed in
264 /// either one or two GPRs, including FP values. TODO: we should pass FP values
265 /// in FP registers for fastcc functions.
266 std::vector<SDOperand>
267 SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
268 MachineFunction &MF = DAG.getMachineFunction();
269 SSARegMap *RegMap = MF.getSSARegMap();
270 std::vector<SDOperand> ArgValues;
272 static const unsigned ArgRegs[] = {
273 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
276 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
277 unsigned ArgOffset = 68;
279 SDOperand Root = DAG.getRoot();
280 std::vector<SDOperand> OutChains;
282 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
283 MVT::ValueType ObjectVT = getValueType(I->getType());
286 default: assert(0 && "Unhandled argument type!");
291 if (I->use_empty()) { // Argument is dead.
292 if (CurArgReg < ArgRegEnd) ++CurArgReg;
293 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
294 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
295 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
296 MF.addLiveIn(*CurArgReg++, VReg);
297 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
298 if (ObjectVT != MVT::i32) {
299 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
301 Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
302 DAG.getValueType(ObjectVT));
303 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
305 ArgValues.push_back(Arg);
307 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
308 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
310 if (ObjectVT == MVT::i32) {
311 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
314 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
316 // Sparc is big endian, so add an offset based on the ObjectVT.
317 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
318 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
319 DAG.getConstant(Offset, MVT::i32));
320 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
321 DAG.getSrcValue(0), ObjectVT);
322 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
324 ArgValues.push_back(Load);
330 if (I->use_empty()) { // Argument is dead.
331 if (CurArgReg < ArgRegEnd) ++CurArgReg;
332 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
333 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
334 // FP value is passed in an integer register.
335 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
336 MF.addLiveIn(*CurArgReg++, VReg);
337 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
339 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
340 ArgValues.push_back(Arg);
342 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
343 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
344 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0));
345 ArgValues.push_back(Load);
352 if (I->use_empty()) { // Argument is dead.
353 if (CurArgReg < ArgRegEnd) ++CurArgReg;
354 if (CurArgReg < ArgRegEnd) ++CurArgReg;
355 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
356 } else if (/* FIXME: Apparently this isn't safe?? */
357 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
358 ((CurArgReg-ArgRegs) & 1) == 0) {
359 // If this is a double argument and the whole thing lives on the stack,
360 // and the argument is aligned, load the double straight from the stack.
361 // We can't do a load in cases like void foo([6ints], int,double),
362 // because the double wouldn't be aligned!
363 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
364 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
365 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
366 DAG.getSrcValue(0)));
369 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
370 unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
371 MF.addLiveIn(*CurArgReg++, VRegHi);
372 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
374 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
375 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
376 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
380 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
381 unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
382 MF.addLiveIn(*CurArgReg++, VRegLo);
383 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
385 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
386 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
387 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
390 // Compose the two halves together into an i64 unit.
391 SDOperand WholeValue =
392 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
394 // If we want a double, do a bit convert.
395 if (ObjectVT == MVT::f64)
396 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
398 ArgValues.push_back(WholeValue);
405 // Store remaining ArgRegs to the stack if this is a varargs function.
406 if (F.getFunctionType()->isVarArg()) {
407 // Remember the vararg offset for the va_start implementation.
408 VarArgsFrameOffset = ArgOffset;
410 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
411 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
412 MF.addLiveIn(*CurArgReg, VReg);
413 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
415 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
416 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
418 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
419 Arg, FIPtr, DAG.getSrcValue(0)));
424 if (!OutChains.empty())
425 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
427 // Finally, inform the code generator which regs we return values in.
428 switch (getValueType(F.getReturnType())) {
429 default: assert(0 && "Unknown type!");
430 case MVT::isVoid: break;
435 MF.addLiveOut(SP::I0);
438 MF.addLiveOut(SP::I0);
439 MF.addLiveOut(SP::I1);
442 MF.addLiveOut(SP::F0);
445 MF.addLiveOut(SP::D0);
452 std::pair<SDOperand, SDOperand>
453 SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
454 bool isVarArg, unsigned CC,
455 bool isTailCall, SDOperand Callee,
456 ArgListTy &Args, SelectionDAG &DAG) {
457 MachineFunction &MF = DAG.getMachineFunction();
458 // Count the size of the outgoing arguments.
459 unsigned ArgsSize = 0;
460 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
461 switch (getValueType(Args[i].second)) {
462 default: assert(0 && "Unknown value type!");
477 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
481 // Keep stack frames 8-byte aligned.
482 ArgsSize = (ArgsSize+7) & ~7;
484 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
485 DAG.getConstant(ArgsSize, getPointerTy()));
487 SDOperand StackPtr, NullSV;
488 std::vector<SDOperand> Stores;
489 std::vector<SDOperand> RegValuesToPass;
490 unsigned ArgOffset = 68;
491 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
492 SDOperand Val = Args[i].first;
493 MVT::ValueType ObjectVT = Val.getValueType();
494 SDOperand ValToStore(0, 0);
497 default: assert(0 && "Unhandled argument type!");
501 // Promote the integer to 32-bits. If the input type is signed, use a
502 // sign extend, otherwise use a zero extend.
503 if (Args[i].second->isSigned())
504 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
506 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
511 if (RegValuesToPass.size() >= 6) {
514 RegValuesToPass.push_back(Val);
519 if (RegValuesToPass.size() >= 6) {
522 // Convert this to a FP value in an int reg.
523 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
524 RegValuesToPass.push_back(Val);
529 // If we can store this directly into the outgoing slot, do so. We can
530 // do this when all ArgRegs are used and if the outgoing slot is aligned.
531 // FIXME: McGill/misr fails with this.
532 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
537 // Otherwise, convert this to a FP value in int regs.
538 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
542 if (RegValuesToPass.size() >= 6) {
543 ValToStore = Val; // Whole thing is passed in memory.
547 // Split the value into top and bottom part. Top part goes in a reg.
548 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
549 DAG.getConstant(1, MVT::i32));
550 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
551 DAG.getConstant(0, MVT::i32));
552 RegValuesToPass.push_back(Hi);
554 if (RegValuesToPass.size() >= 6) {
559 RegValuesToPass.push_back(Lo);
564 if (ValToStore.Val) {
566 StackPtr = DAG.getRegister(SP::O6, MVT::i32);
567 NullSV = DAG.getSrcValue(NULL);
569 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
570 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
571 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
572 ValToStore, PtrOff, NullSV));
574 ArgOffset += ObjSize;
577 // Emit all stores, make sure the occur before any copies into physregs.
579 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
581 static const unsigned ArgRegs[] = {
582 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
585 // Build a sequence of copy-to-reg nodes chained together with token chain
586 // and flag operands which copy the outgoing args into O[0-5].
588 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
589 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
590 InFlag = Chain.getValue(1);
593 // If the callee is a GlobalAddress node (quite common, every direct call is)
594 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
595 // Likewise ExternalSymbol -> TargetExternalSymbol.
596 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
597 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
598 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
599 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
601 std::vector<MVT::ValueType> NodeTys;
602 NodeTys.push_back(MVT::Other); // Returns a chain
603 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
604 std::vector<SDOperand> Ops;
605 Ops.push_back(Chain);
606 Ops.push_back(Callee);
608 Ops.push_back(InFlag);
609 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops);
610 InFlag = Chain.getValue(1);
612 MVT::ValueType RetTyVT = getValueType(RetTy);
614 if (RetTyVT != MVT::isVoid) {
616 default: assert(0 && "Unknown value type to return!");
620 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
621 Chain = RetVal.getValue(1);
623 // Add a note to keep track of whether it is sign or zero extended.
624 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
625 MVT::i32, RetVal, DAG.getValueType(RetTyVT));
626 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
629 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
630 Chain = RetVal.getValue(1);
633 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag);
634 Chain = RetVal.getValue(1);
637 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag);
638 Chain = RetVal.getValue(1);
641 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag);
642 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32,
644 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
645 Chain = Hi.getValue(1);
650 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
651 DAG.getConstant(ArgsSize, getPointerTy()));
653 return std::make_pair(RetVal, Chain);
656 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
657 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
658 static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
659 ISD::CondCode CC, unsigned &SPCC) {
660 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
662 ((LHS.getOpcode() == SPISD::SELECT_ICC &&
663 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
664 (LHS.getOpcode() == SPISD::SELECT_FCC &&
665 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
666 isa<ConstantSDNode>(LHS.getOperand(0)) &&
667 isa<ConstantSDNode>(LHS.getOperand(1)) &&
668 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
669 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
670 SDOperand CMPCC = LHS.getOperand(3);
671 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
672 LHS = CMPCC.getOperand(0);
673 RHS = CMPCC.getOperand(1);
678 SDOperand SparcTargetLowering::
679 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
680 switch (Op.getOpcode()) {
681 default: assert(0 && "Should not custom lower this!");
682 case ISD::GlobalAddress: {
683 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
684 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
685 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
686 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
687 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
689 case ISD::ConstantPool: {
690 Constant *C = cast<ConstantPoolSDNode>(Op)->get();
691 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
692 cast<ConstantPoolSDNode>(Op)->getAlignment());
693 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
694 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
695 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
697 case ISD::FP_TO_SINT:
698 // Convert the fp value to integer in an FP register.
699 assert(Op.getValueType() == MVT::i32);
700 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
701 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
702 case ISD::SINT_TO_FP: {
703 assert(Op.getOperand(0).getValueType() == MVT::i32);
704 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
705 // Convert the int value to FP in an FP register.
706 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
709 SDOperand Chain = Op.getOperand(0);
710 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
711 SDOperand LHS = Op.getOperand(2);
712 SDOperand RHS = Op.getOperand(3);
713 SDOperand Dest = Op.getOperand(4);
714 unsigned Opc, SPCC = ~0U;
716 // If this is a br_cc of a "setcc", and if the setcc got lowered into
717 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
718 LookThroughSetCC(LHS, RHS, CC, SPCC);
720 // Get the condition flag.
721 SDOperand CompareFlag;
722 if (LHS.getValueType() == MVT::i32) {
723 std::vector<MVT::ValueType> VTs;
724 VTs.push_back(MVT::i32);
725 VTs.push_back(MVT::Flag);
726 std::vector<SDOperand> Ops;
729 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
730 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
733 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
734 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
737 return DAG.getNode(Opc, MVT::Other, Chain, Dest,
738 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
740 case ISD::SELECT_CC: {
741 SDOperand LHS = Op.getOperand(0);
742 SDOperand RHS = Op.getOperand(1);
743 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
744 SDOperand TrueVal = Op.getOperand(2);
745 SDOperand FalseVal = Op.getOperand(3);
746 unsigned Opc, SPCC = ~0U;
748 // If this is a select_cc of a "setcc", and if the setcc got lowered into
749 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
750 LookThroughSetCC(LHS, RHS, CC, SPCC);
752 SDOperand CompareFlag;
753 if (LHS.getValueType() == MVT::i32) {
754 std::vector<MVT::ValueType> VTs;
755 VTs.push_back(LHS.getValueType()); // subcc returns a value
756 VTs.push_back(MVT::Flag);
757 std::vector<SDOperand> Ops;
760 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
761 Opc = SPISD::SELECT_ICC;
762 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
764 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
765 Opc = SPISD::SELECT_FCC;
766 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
768 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
769 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
772 // vastart just stores the address of the VarArgsFrameIndex slot into the
773 // memory location argument.
774 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
775 DAG.getRegister(SP::I6, MVT::i32),
776 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
777 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset,
778 Op.getOperand(1), Op.getOperand(2));
781 SDNode *Node = Op.Val;
782 MVT::ValueType VT = Node->getValueType(0);
783 SDOperand InChain = Node->getOperand(0);
784 SDOperand VAListPtr = Node->getOperand(1);
785 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr,
786 Node->getOperand(2));
787 // Increment the pointer, VAList, to the next vaarg
788 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList,
789 DAG.getConstant(MVT::getSizeInBits(VT)/8,
791 // Store the incremented VAList to the legalized pointer
792 InChain = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), NextPtr,
793 VAListPtr, Node->getOperand(2));
794 // Load the actual argument out of the pointer VAList, unless this is an
796 if (VT != MVT::f64) {
797 return DAG.getLoad(VT, InChain, VAList, DAG.getSrcValue(0));
799 // Otherwise, load it as i64, then do a bitconvert.
800 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, DAG.getSrcValue(0));
801 std::vector<MVT::ValueType> Tys;
802 Tys.push_back(MVT::f64);
803 Tys.push_back(MVT::Other);
804 std::vector<SDOperand> Ops;
805 // Bit-Convert the value to f64.
806 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V));
807 Ops.push_back(V.getValue(1));
808 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
814 switch(Op.getNumOperands()) {
816 assert(0 && "Do not know how to return this many arguments!");
819 return SDOperand(); // ret void is legal
822 switch(Op.getOperand(1).getValueType()) {
823 default: assert(0 && "Unknown type to return!");
824 case MVT::i32: ArgReg = SP::I0; break;
825 case MVT::f32: ArgReg = SP::F0; break;
826 case MVT::f64: ArgReg = SP::D0; break;
828 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
833 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(2),
835 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
838 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
844 SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
845 MachineBasicBlock *BB) {
848 // Figure out the conditional branch opcode to use for this select_cc.
849 switch (MI->getOpcode()) {
850 default: assert(0 && "Unknown SELECT_CC!");
851 case SP::SELECT_CC_Int_ICC:
852 case SP::SELECT_CC_FP_ICC:
853 case SP::SELECT_CC_DFP_ICC:
854 BROpcode = SP::BCOND;
856 case SP::SELECT_CC_Int_FCC:
857 case SP::SELECT_CC_FP_FCC:
858 case SP::SELECT_CC_DFP_FCC:
859 BROpcode = SP::FBCOND;
863 CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue();
865 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
866 // control-flow pattern. The incoming instruction knows the destination vreg
867 // to set, the condition code register to branch on, the true/false values to
868 // select between, and a branch opcode to use.
869 const BasicBlock *LLVM_BB = BB->getBasicBlock();
870 ilist<MachineBasicBlock>::iterator It = BB;
877 // fallthrough --> copy0MBB
878 MachineBasicBlock *thisMBB = BB;
879 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
880 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
881 BuildMI(BB, BROpcode, 2).addMBB(sinkMBB).addImm(CC);
882 MachineFunction *F = BB->getParent();
883 F->getBasicBlockList().insert(It, copy0MBB);
884 F->getBasicBlockList().insert(It, sinkMBB);
885 // Update machine-CFG edges
886 BB->addSuccessor(copy0MBB);
887 BB->addSuccessor(sinkMBB);
891 // # fallthrough to sinkMBB
894 // Update machine-CFG edges
895 BB->addSuccessor(sinkMBB);
898 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
901 BuildMI(BB, SP::PHI, 4, MI->getOperand(0).getReg())
902 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
903 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
905 delete MI; // The pseudo instruction is gone now.
909 //===----------------------------------------------------------------------===//
910 // Instruction Selector Implementation
911 //===----------------------------------------------------------------------===//
913 //===--------------------------------------------------------------------===//
914 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
915 /// instructions for SelectionDAG operations.
918 class SparcDAGToDAGISel : public SelectionDAGISel {
919 SparcTargetLowering Lowering;
921 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
922 /// make the right decision when generating code for different targets.
923 const SparcSubtarget &Subtarget;
925 SparcDAGToDAGISel(TargetMachine &TM)
926 : SelectionDAGISel(Lowering), Lowering(TM),
927 Subtarget(TM.getSubtarget<SparcSubtarget>()) {
930 void Select(SDOperand &Result, SDOperand Op);
932 // Complex Pattern Selectors.
933 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
934 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
936 /// InstructionSelectBasicBlock - This callback is invoked by
937 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
938 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
940 virtual const char *getPassName() const {
941 return "SPARC DAG->DAG Pattern Instruction Selection";
944 // Include the pieces autogenerated from the target description.
945 #include "SparcGenDAGISel.inc"
947 } // end anonymous namespace
949 /// InstructionSelectBasicBlock - This callback is invoked by
950 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
951 void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
954 // Select target instructions for the DAG.
955 DAG.setRoot(SelectRoot(DAG.getRoot()));
957 DAG.RemoveDeadNodes();
959 // Emit machine code to BB.
960 ScheduleAndEmitDAG(DAG);
963 bool SparcDAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
965 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
966 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
967 Offset = CurDAG->getTargetConstant(0, MVT::i32);
970 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
971 Addr.getOpcode() == ISD::TargetGlobalAddress)
972 return false; // direct calls.
974 if (Addr.getOpcode() == ISD::ADD) {
975 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
976 if (Predicate_simm13(CN)) {
977 if (FrameIndexSDNode *FIN =
978 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
979 // Constant offset from frame ref.
980 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
982 Base = Addr.getOperand(0);
984 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
988 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
989 Base = Addr.getOperand(1);
990 Offset = Addr.getOperand(0).getOperand(0);
993 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
994 Base = Addr.getOperand(0);
995 Offset = Addr.getOperand(1).getOperand(0);
1000 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1004 bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
1006 if (Addr.getOpcode() == ISD::FrameIndex) return false;
1007 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1008 Addr.getOpcode() == ISD::TargetGlobalAddress)
1009 return false; // direct calls.
1011 if (Addr.getOpcode() == ISD::ADD) {
1012 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
1013 Predicate_simm13(Addr.getOperand(1).Val))
1014 return false; // Let the reg+imm pattern catch this!
1015 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
1016 Addr.getOperand(1).getOpcode() == SPISD::Lo)
1017 return false; // Let the reg+imm pattern catch this!
1018 R1 = Addr.getOperand(0);
1019 R2 = Addr.getOperand(1);
1024 R2 = CurDAG->getRegister(SP::G0, MVT::i32);
1028 void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
1030 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
1031 N->getOpcode() < SPISD::FIRST_NUMBER) {
1033 return; // Already selected.
1036 // If this has already been converted, use it.
1037 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
1038 if (CGMI != CodeGenMap.end()) {
1039 Result = CGMI->second;
1043 switch (N->getOpcode()) {
1045 case ISD::ADD_PARTS: {
1046 SDOperand LHSL, LHSH, RHSL, RHSH;
1047 Select(LHSL, N->getOperand(0));
1048 Select(LHSH, N->getOperand(1));
1049 Select(RHSL, N->getOperand(2));
1050 Select(RHSH, N->getOperand(3));
1051 // FIXME, handle immediate RHS.
1053 SDOperand(CurDAG->getTargetNode(SP::ADDCCrr, MVT::i32, MVT::Flag,
1056 SDOperand(CurDAG->getTargetNode(SP::ADDXrr, MVT::i32, LHSH, RHSH,
1057 Low.getValue(1)), 0);
1058 CodeGenMap[SDOperand(N, 0)] = Low;
1059 CodeGenMap[SDOperand(N, 1)] = Hi;
1060 Result = Op.ResNo ? Hi : Low;
1063 case ISD::SUB_PARTS: {
1064 SDOperand LHSL, LHSH, RHSL, RHSH;
1065 Select(LHSL, N->getOperand(0));
1066 Select(LHSH, N->getOperand(1));
1067 Select(RHSL, N->getOperand(2));
1068 Select(RHSH, N->getOperand(3));
1070 SDOperand(CurDAG->getTargetNode(SP::SUBCCrr, MVT::i32, MVT::Flag,
1073 SDOperand(CurDAG->getTargetNode(SP::SUBXrr, MVT::i32, LHSH, RHSH,
1074 Low.getValue(1)), 0);
1075 CodeGenMap[SDOperand(N, 0)] = Low;
1076 CodeGenMap[SDOperand(N, 1)] = Hi;
1077 Result = Op.ResNo ? Hi : Low;
1082 // FIXME: should use a custom expander to expose the SRA to the dag.
1083 SDOperand DivLHS, DivRHS;
1084 Select(DivLHS, N->getOperand(0));
1085 Select(DivRHS, N->getOperand(1));
1087 // Set the Y register to the high-part.
1089 if (N->getOpcode() == ISD::SDIV) {
1090 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
1091 CurDAG->getTargetConstant(31, MVT::i32)), 0);
1093 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
1095 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
1096 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
1098 // FIXME: Handle div by immediate.
1099 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
1100 Result = CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
1105 // FIXME: Handle mul by immediate.
1106 SDOperand MulLHS, MulRHS;
1107 Select(MulLHS, N->getOperand(0));
1108 Select(MulRHS, N->getOperand(1));
1109 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
1110 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
1112 // The high part is in the Y register.
1113 Result = CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
1118 SelectCode(Result, Op);
1122 /// createSparcISelDag - This pass converts a legalized DAG into a
1123 /// SPARC-specific DAG, ready for instruction scheduling.
1125 FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
1126 return new SparcDAGToDAGISel(TM);