1 //===-- SparcMCCodeEmitter.cpp - Convert Sparc code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SparcMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #include "SparcMCExpr.h"
15 #include "MCTargetDesc/SparcFixupKinds.h"
16 #include "SparcMCTargetDesc.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "mccodeemitter"
31 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
34 class SparcMCCodeEmitter : public MCCodeEmitter {
35 SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete;
36 void operator=(const SparcMCCodeEmitter &) = delete;
40 SparcMCCodeEmitter(MCContext &ctx): Ctx(ctx) {}
42 ~SparcMCCodeEmitter() override {}
44 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
45 SmallVectorImpl<MCFixup> &Fixups,
46 const MCSubtargetInfo &STI) const override;
48 // getBinaryCodeForInstr - TableGen'erated function for getting the
49 // binary encoding for an instruction.
50 uint64_t getBinaryCodeForInstr(const MCInst &MI,
51 SmallVectorImpl<MCFixup> &Fixups,
52 const MCSubtargetInfo &STI) const;
54 /// getMachineOpValue - Return binary encoding of operand. If the machine
55 /// operand requires relocation, record the relocation and return zero.
56 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
57 SmallVectorImpl<MCFixup> &Fixups,
58 const MCSubtargetInfo &STI) const;
60 unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
61 SmallVectorImpl<MCFixup> &Fixups,
62 const MCSubtargetInfo &STI) const;
63 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
64 SmallVectorImpl<MCFixup> &Fixups,
65 const MCSubtargetInfo &STI) const;
66 unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
67 SmallVectorImpl<MCFixup> &Fixups,
68 const MCSubtargetInfo &STI) const;
69 unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
70 SmallVectorImpl<MCFixup> &Fixups,
71 const MCSubtargetInfo &STI) const;
74 } // end anonymous namespace
76 MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII,
77 const MCRegisterInfo &MRI,
79 return new SparcMCCodeEmitter(Ctx);
82 void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
83 SmallVectorImpl<MCFixup> &Fixups,
84 const MCSubtargetInfo &STI) const {
85 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
87 if (Ctx.getAsmInfo()->isLittleEndian()) {
88 // Output the bits in little-endian byte order.
89 for (unsigned i = 0; i != 4; ++i) {
94 // Output the bits in big-endian byte order.
95 for (unsigned i = 0; i != 4; ++i) {
96 OS << (char)(Bits >> 24);
100 unsigned tlsOpNo = 0;
101 switch (MI.getOpcode()) {
103 case SP::TLS_CALL: tlsOpNo = 1; break;
107 case SP::TLS_LDXrr: tlsOpNo = 3; break;
110 const MCOperand &MO = MI.getOperand(tlsOpNo);
111 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI);
112 assert(op == 0 && "Unexpected operand value!");
113 (void)op; // suppress warning.
116 ++MCNumEmitted; // Keep track of the # of mi's emitted.
120 unsigned SparcMCCodeEmitter::
121 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
122 SmallVectorImpl<MCFixup> &Fixups,
123 const MCSubtargetInfo &STI) const {
126 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
132 const MCExpr *Expr = MO.getExpr();
133 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
134 MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind();
135 Fixups.push_back(MCFixup::create(0, Expr, Kind));
140 if (Expr->EvaluateAsAbsolute(Res))
143 llvm_unreachable("Unhandled expression!");
147 unsigned SparcMCCodeEmitter::
148 getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
149 SmallVectorImpl<MCFixup> &Fixups,
150 const MCSubtargetInfo &STI) const {
151 const MCOperand &MO = MI.getOperand(OpNo);
152 if (MO.isReg() || MO.isImm())
153 return getMachineOpValue(MI, MO, Fixups, STI);
155 if (MI.getOpcode() == SP::TLS_CALL) {
156 // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in
157 // encodeInstruction.
159 // Verify that the callee is actually __tls_get_addr.
160 const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr());
161 assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef &&
162 "Unexpected expression in TLS_CALL");
163 const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr());
164 assert(SymExpr->getSymbol().getName() == "__tls_get_addr" &&
165 "Unexpected function for TLS_CALL");
170 MCFixupKind fixupKind = (MCFixupKind)Sparc::fixup_sparc_call30;
172 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr())) {
173 if (SExpr->getKind() == SparcMCExpr::VK_Sparc_WPLT30)
174 fixupKind = (MCFixupKind)Sparc::fixup_sparc_wplt30;
177 Fixups.push_back(MCFixup::create(0, MO.getExpr(), fixupKind));
182 unsigned SparcMCCodeEmitter::
183 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
184 SmallVectorImpl<MCFixup> &Fixups,
185 const MCSubtargetInfo &STI) const {
186 const MCOperand &MO = MI.getOperand(OpNo);
187 if (MO.isReg() || MO.isImm())
188 return getMachineOpValue(MI, MO, Fixups, STI);
190 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
191 (MCFixupKind)Sparc::fixup_sparc_br22));
195 unsigned SparcMCCodeEmitter::
196 getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
197 SmallVectorImpl<MCFixup> &Fixups,
198 const MCSubtargetInfo &STI) const {
199 const MCOperand &MO = MI.getOperand(OpNo);
200 if (MO.isReg() || MO.isImm())
201 return getMachineOpValue(MI, MO, Fixups, STI);
203 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
204 (MCFixupKind)Sparc::fixup_sparc_br19));
207 unsigned SparcMCCodeEmitter::
208 getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
209 SmallVectorImpl<MCFixup> &Fixups,
210 const MCSubtargetInfo &STI) const {
211 const MCOperand &MO = MI.getOperand(OpNo);
212 if (MO.isReg() || MO.isImm())
213 return getMachineOpValue(MI, MO, Fixups, STI);
215 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
216 (MCFixupKind)Sparc::fixup_sparc_br16_2));
217 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
218 (MCFixupKind)Sparc::fixup_sparc_br16_14));
225 #include "SparcGenMCCodeEmitter.inc"