1 //===-- SparcMCCodeEmitter.cpp - Convert Sparc code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SparcMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "SparcMCExpr.h"
16 #include "MCTargetDesc/SparcFixupKinds.h"
17 #include "SparcMCTargetDesc.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/Support/raw_ostream.h"
29 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
32 class SparcMCCodeEmitter : public MCCodeEmitter {
33 SparcMCCodeEmitter(const SparcMCCodeEmitter &) LLVM_DELETED_FUNCTION;
34 void operator=(const SparcMCCodeEmitter &) LLVM_DELETED_FUNCTION;
38 SparcMCCodeEmitter(MCContext &ctx): Ctx(ctx) {}
40 ~SparcMCCodeEmitter() {}
42 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
43 SmallVectorImpl<MCFixup> &Fixups,
44 const MCSubtargetInfo &STI) const;
46 // getBinaryCodeForInstr - TableGen'erated function for getting the
47 // binary encoding for an instruction.
48 uint64_t getBinaryCodeForInstr(const MCInst &MI,
49 SmallVectorImpl<MCFixup> &Fixups,
50 const MCSubtargetInfo &STI) const;
52 /// getMachineOpValue - Return binary encoding of operand. If the machine
53 /// operand requires relocation, record the relocation and return zero.
54 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
55 SmallVectorImpl<MCFixup> &Fixups,
56 const MCSubtargetInfo &STI) const;
58 unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
59 SmallVectorImpl<MCFixup> &Fixups,
60 const MCSubtargetInfo &STI) const;
61 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
62 SmallVectorImpl<MCFixup> &Fixups,
63 const MCSubtargetInfo &STI) const;
64 unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
65 SmallVectorImpl<MCFixup> &Fixups,
66 const MCSubtargetInfo &STI) const;
68 } // end anonymous namespace
70 MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII,
71 const MCRegisterInfo &MRI,
72 const MCSubtargetInfo &STI,
74 return new SparcMCCodeEmitter(Ctx);
77 void SparcMCCodeEmitter::
78 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
79 SmallVectorImpl<MCFixup> &Fixups,
80 const MCSubtargetInfo &STI) const {
81 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
83 // Output the constant in big endian byte order.
84 for (unsigned i = 0; i != 4; ++i) {
85 OS << (char)(Bits >> 24);
89 switch (MI.getOpcode()) {
91 case SP::TLS_CALL: tlsOpNo = 1; break;
95 case SP::TLS_LDXrr: tlsOpNo = 3; break;
98 const MCOperand &MO = MI.getOperand(tlsOpNo);
99 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI);
100 assert(op == 0 && "Unexpected operand value!");
101 (void)op; // suppress warning.
104 ++MCNumEmitted; // Keep track of the # of mi's emitted.
108 unsigned SparcMCCodeEmitter::
109 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
110 SmallVectorImpl<MCFixup> &Fixups,
111 const MCSubtargetInfo &STI) const {
114 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
120 const MCExpr *Expr = MO.getExpr();
121 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
122 MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind();
123 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
128 if (Expr->EvaluateAsAbsolute(Res))
131 assert(0 && "Unhandled expression!");
135 unsigned SparcMCCodeEmitter::
136 getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
137 SmallVectorImpl<MCFixup> &Fixups,
138 const MCSubtargetInfo &STI) const {
139 const MCOperand &MO = MI.getOperand(OpNo);
140 if (MO.isReg() || MO.isImm())
141 return getMachineOpValue(MI, MO, Fixups, STI);
143 if (MI.getOpcode() == SP::TLS_CALL) {
144 // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in
145 // EncodeInstruction.
147 // Verify that the callee is actually __tls_get_addr.
148 const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr());
149 assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef &&
150 "Unexpected expression in TLS_CALL");
151 const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr());
152 assert(SymExpr->getSymbol().getName() == "__tls_get_addr" &&
153 "Unexpected function for TLS_CALL");
158 MCFixupKind fixupKind = (MCFixupKind)Sparc::fixup_sparc_call30;
160 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr())) {
161 if (SExpr->getKind() == SparcMCExpr::VK_Sparc_WPLT30)
162 fixupKind = (MCFixupKind)Sparc::fixup_sparc_wplt30;
165 Fixups.push_back(MCFixup::Create(0, MO.getExpr(), fixupKind));
170 unsigned SparcMCCodeEmitter::
171 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
172 SmallVectorImpl<MCFixup> &Fixups,
173 const MCSubtargetInfo &STI) const {
174 const MCOperand &MO = MI.getOperand(OpNo);
175 if (MO.isReg() || MO.isImm())
176 return getMachineOpValue(MI, MO, Fixups, STI);
178 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
179 (MCFixupKind)Sparc::fixup_sparc_br22));
183 unsigned SparcMCCodeEmitter::
184 getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
185 SmallVectorImpl<MCFixup> &Fixups,
186 const MCSubtargetInfo &STI) const {
187 const MCOperand &MO = MI.getOperand(OpNo);
188 if (MO.isReg() || MO.isImm())
189 return getMachineOpValue(MI, MO, Fixups, STI);
191 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
192 (MCFixupKind)Sparc::fixup_sparc_br19));
197 #include "SparcGenMCCodeEmitter.inc"