1 //===-- SparcAsmBackend.cpp - Sparc Assembler Backend ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCAsmBackend.h"
11 #include "MCTargetDesc/SparcFixupKinds.h"
12 #include "MCTargetDesc/SparcMCTargetDesc.h"
13 #include "llvm/MC/MCELFObjectWriter.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCFixupKindInfo.h"
16 #include "llvm/MC/MCObjectWriter.h"
17 #include "llvm/MC/MCValue.h"
18 #include "llvm/Support/TargetRegistry.h"
22 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
25 llvm_unreachable("Unknown fixup kind!");
32 case Sparc::fixup_sparc_wplt30:
33 case Sparc::fixup_sparc_call30:
34 return (Value >> 2) & 0x3fffffff;
36 case Sparc::fixup_sparc_br22:
37 return (Value >> 2) & 0x3fffff;
39 case Sparc::fixup_sparc_br19:
40 return (Value >> 2) & 0x7ffff;
42 case Sparc::fixup_sparc_pc22:
43 case Sparc::fixup_sparc_got22:
44 case Sparc::fixup_sparc_tls_gd_hi22:
45 case Sparc::fixup_sparc_tls_ldm_hi22:
46 case Sparc::fixup_sparc_tls_ie_hi22:
47 case Sparc::fixup_sparc_hi22:
48 return (Value >> 10) & 0x3fffff;
50 case Sparc::fixup_sparc_pc10:
51 case Sparc::fixup_sparc_got10:
52 case Sparc::fixup_sparc_tls_gd_lo10:
53 case Sparc::fixup_sparc_tls_ldm_lo10:
54 case Sparc::fixup_sparc_tls_ie_lo10:
55 case Sparc::fixup_sparc_lo10:
58 case Sparc::fixup_sparc_tls_ldo_hix22:
59 case Sparc::fixup_sparc_tls_le_hix22:
60 return (~Value >> 10) & 0x3fffff;
62 case Sparc::fixup_sparc_tls_ldo_lox10:
63 case Sparc::fixup_sparc_tls_le_lox10:
64 return (~(~Value & 0x3ff)) & 0x1fff;
66 case Sparc::fixup_sparc_h44:
67 return (Value >> 22) & 0x3fffff;
69 case Sparc::fixup_sparc_m44:
70 return (Value >> 12) & 0x3ff;
72 case Sparc::fixup_sparc_l44:
75 case Sparc::fixup_sparc_hh:
76 return (Value >> 42) & 0x3fffff;
78 case Sparc::fixup_sparc_hm:
79 return (Value >> 32) & 0x3ff;
81 case Sparc::fixup_sparc_tls_gd_add:
82 case Sparc::fixup_sparc_tls_gd_call:
83 case Sparc::fixup_sparc_tls_ldm_add:
84 case Sparc::fixup_sparc_tls_ldm_call:
85 case Sparc::fixup_sparc_tls_ldo_add:
86 case Sparc::fixup_sparc_tls_ie_ld:
87 case Sparc::fixup_sparc_tls_ie_ldx:
88 case Sparc::fixup_sparc_tls_ie_add:
94 class SparcAsmBackend : public MCAsmBackend {
95 const Target &TheTarget;
97 SparcAsmBackend(const Target &T) : MCAsmBackend(), TheTarget(T) {}
99 unsigned getNumFixupKinds() const {
100 return Sparc::NumTargetFixupKinds;
103 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
104 const static MCFixupKindInfo Infos[Sparc::NumTargetFixupKinds] = {
105 // name offset bits flags
106 { "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
107 { "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
108 { "fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
109 { "fixup_sparc_hi22", 10, 22, 0 },
110 { "fixup_sparc_lo10", 22, 10, 0 },
111 { "fixup_sparc_h44", 10, 22, 0 },
112 { "fixup_sparc_m44", 22, 10, 0 },
113 { "fixup_sparc_l44", 20, 12, 0 },
114 { "fixup_sparc_hh", 10, 22, 0 },
115 { "fixup_sparc_hm", 22, 10, 0 },
116 { "fixup_sparc_pc22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
117 { "fixup_sparc_pc10", 22, 10, MCFixupKindInfo::FKF_IsPCRel },
118 { "fixup_sparc_got22", 10, 22, 0 },
119 { "fixup_sparc_got10", 22, 10, 0 },
120 { "fixup_sparc_wplt30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
121 { "fixup_sparc_tls_gd_hi22", 10, 22, 0 },
122 { "fixup_sparc_tls_gd_lo10", 22, 10, 0 },
123 { "fixup_sparc_tls_gd_add", 0, 0, 0 },
124 { "fixup_sparc_tls_gd_call", 0, 0, 0 },
125 { "fixup_sparc_tls_ldm_hi22", 10, 22, 0 },
126 { "fixup_sparc_tls_ldm_lo10", 22, 10, 0 },
127 { "fixup_sparc_tls_ldm_add", 0, 0, 0 },
128 { "fixup_sparc_tls_ldm_call", 0, 0, 0 },
129 { "fixup_sparc_tls_ldo_hix22", 10, 22, 0 },
130 { "fixup_sparc_tls_ldo_lox10", 22, 10, 0 },
131 { "fixup_sparc_tls_ldo_add", 0, 0, 0 },
132 { "fixup_sparc_tls_ie_hi22", 10, 22, 0 },
133 { "fixup_sparc_tls_ie_lo10", 22, 10, 0 },
134 { "fixup_sparc_tls_ie_ld", 0, 0, 0 },
135 { "fixup_sparc_tls_ie_ldx", 0, 0, 0 },
136 { "fixup_sparc_tls_ie_add", 0, 0, 0 },
137 { "fixup_sparc_tls_le_hix22", 0, 0, 0 },
138 { "fixup_sparc_tls_le_lox10", 0, 0, 0 }
141 if (Kind < FirstTargetFixupKind)
142 return MCAsmBackend::getFixupKindInfo(Kind);
144 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
146 return Infos[Kind - FirstTargetFixupKind];
149 void processFixupValue(const MCAssembler &Asm,
150 const MCAsmLayout &Layout,
151 const MCFixup &Fixup,
152 const MCFragment *DF,
156 switch ((Sparc::Fixups)Fixup.getKind()) {
158 case Sparc::fixup_sparc_wplt30:
159 if (Target.getSymA()->getSymbol().isTemporary())
161 case Sparc::fixup_sparc_tls_gd_hi22:
162 case Sparc::fixup_sparc_tls_gd_lo10:
163 case Sparc::fixup_sparc_tls_gd_add:
164 case Sparc::fixup_sparc_tls_gd_call:
165 case Sparc::fixup_sparc_tls_ldm_hi22:
166 case Sparc::fixup_sparc_tls_ldm_lo10:
167 case Sparc::fixup_sparc_tls_ldm_add:
168 case Sparc::fixup_sparc_tls_ldm_call:
169 case Sparc::fixup_sparc_tls_ldo_hix22:
170 case Sparc::fixup_sparc_tls_ldo_lox10:
171 case Sparc::fixup_sparc_tls_ldo_add:
172 case Sparc::fixup_sparc_tls_ie_hi22:
173 case Sparc::fixup_sparc_tls_ie_lo10:
174 case Sparc::fixup_sparc_tls_ie_ld:
175 case Sparc::fixup_sparc_tls_ie_ldx:
176 case Sparc::fixup_sparc_tls_ie_add:
177 case Sparc::fixup_sparc_tls_le_hix22:
178 case Sparc::fixup_sparc_tls_le_lox10: IsResolved = false; break;
182 bool mayNeedRelaxation(const MCInst &Inst) const {
187 /// fixupNeedsRelaxation - Target specific predicate for whether a given
188 /// fixup requires the associated instruction to be relaxed.
189 bool fixupNeedsRelaxation(const MCFixup &Fixup,
191 const MCRelaxableFragment *DF,
192 const MCAsmLayout &Layout) const {
194 assert(0 && "fixupNeedsRelaxation() unimplemented");
197 void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
199 assert(0 && "relaxInstruction() unimplemented");
202 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
203 // Cannot emit NOP with size not multiple of 32 bits.
207 uint64_t NumNops = Count / 4;
208 for (uint64_t i = 0; i != NumNops; ++i)
209 OW->Write32(0x01000000);
214 bool is64Bit() const {
215 StringRef name = TheTarget.getName();
216 return name == "sparcv9";
220 class ELFSparcAsmBackend : public SparcAsmBackend {
221 Triple::OSType OSType;
223 ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) :
224 SparcAsmBackend(T), OSType(OSType) { }
226 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
227 uint64_t Value) const {
229 Value = adjustFixupValue(Fixup.getKind(), Value);
230 if (!Value) return; // Doesn't change encoding.
232 unsigned Offset = Fixup.getOffset();
234 // For each byte of the fragment that the fixup touches, mask in the bits
235 // from the fixup value. The Value has been "split up" into the
236 // appropriate bitfields above.
237 for (unsigned i = 0; i != 4; ++i)
238 Data[Offset + i] |= uint8_t((Value >> ((4 - i - 1)*8)) & 0xff);
242 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
243 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
244 return createSparcELFObjectWriter(OS, is64Bit(), OSABI);
248 } // end anonymous namespace
251 MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
252 const MCRegisterInfo &MRI,
255 return new ELFSparcAsmBackend(T, Triple(TT).getOS());