1 //===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax -----==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an Sparc MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "SparcInstPrinter.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCSymbol.h"
20 #include "llvm/Support/raw_ostream.h"
23 // The generated AsmMatcher SparcGenAsmWriter uses "Sparc" as the target
24 // namespace. But SPARC backend uses "SP" as its namespace.
31 #define GET_INSTRUCTION_NAME
32 #define PRINT_ALIAS_INSTR
33 #include "SparcGenAsmWriter.inc"
35 bool SparcInstPrinter::isV9() const {
36 return (STI.getFeatureBits() & Sparc::FeatureV9) != 0;
39 void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const
41 OS << '%' << StringRef(getRegisterName(RegNo)).lower();
44 void SparcInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
47 if (!printAliasInstr(MI, O) && !printSparcAliasInstr(MI, O))
48 printInstruction(MI, O);
49 printAnnotation(O, Annot);
52 bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI, raw_ostream &O)
54 switch (MI->getOpcode()) {
55 default: return false;
58 if (MI->getNumOperands() != 3)
60 if (!MI->getOperand(0).isReg())
62 switch (MI->getOperand(0).getReg()) {
63 default: return false;
64 case SP::G0: // jmp $addr
65 O << "\tjmp "; printMemOperand(MI, 1, O);
67 case SP::O7: // call $addr
68 O << "\tcall "; printMemOperand(MI, 1, O);
76 || (MI->getNumOperands() != 3)
77 || (!MI->getOperand(0).isReg())
78 || (MI->getOperand(0).getReg() != SP::FCC0))
80 // if V8, skip printing %fcc0.
81 switch(MI->getOpcode()) {
83 case SP::V9FCMPS: O << "\tfcmps "; break;
84 case SP::V9FCMPD: O << "\tfcmpd "; break;
85 case SP::V9FCMPQ: O << "\tfcmpq "; break;
87 printOperand(MI, 1, O);
89 printOperand(MI, 2, O);
95 void SparcInstPrinter::printOperand(const MCInst *MI, int opNum,
98 const MCOperand &MO = MI->getOperand (opNum);
101 printRegName(O, MO.getReg());
106 O << (int)MO.getImm();
110 assert(MO.isExpr() && "Unknown operand kind in printOperand");
111 MO.getExpr()->print(O);
114 void SparcInstPrinter::printMemOperand(const MCInst *MI, int opNum,
115 raw_ostream &O, const char *Modifier)
117 printOperand(MI, opNum, O);
119 // If this is an ADD operand, emit it like normal operands.
120 if (Modifier && !strcmp(Modifier, "arith")) {
122 printOperand(MI, opNum+1, O);
125 const MCOperand &MO = MI->getOperand(opNum+1);
127 if (MO.isReg() && MO.getReg() == SP::G0)
128 return; // don't print "+%g0"
129 if (MO.isImm() && MO.getImm() == 0)
130 return; // don't print "+0"
134 printOperand(MI, opNum+1, O);
137 void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum,
140 int CC = (int)MI->getOperand(opNum).getImm();
141 switch (MI->getOpcode()) {
153 case SP::FMOVQ_FCC: // Make sure CC is a fp conditional flag.
154 CC = (CC < 16) ? (CC + 16) : CC;
157 O << SPARCCondCodeToString((SPCC::CondCodes)CC);
160 bool SparcInstPrinter::printGetPCX(const MCInst *MI, unsigned opNum,
163 assert(0 && "FIXME: Implement SparcInstPrinter::printGetPCX.");