1 //===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Sparc Disassembler.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "sparc-disassembler"
17 #include "SparcRegisterInfo.h"
18 #include "SparcSubtarget.h"
19 #include "llvm/MC/MCDisassembler.h"
20 #include "llvm/MC/MCFixedLenDisassembler.h"
21 #include "llvm/Support/MemoryObject.h"
22 #include "llvm/Support/TargetRegistry.h"
26 typedef MCDisassembler::DecodeStatus DecodeStatus;
30 /// SparcDisassembler - a disassembler class for Sparc.
31 class SparcDisassembler : public MCDisassembler {
33 /// Constructor - Initializes the disassembler.
35 SparcDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
36 MCDisassembler(STI), RegInfo(Info)
38 virtual ~SparcDisassembler() {}
40 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
42 /// getInstruction - See MCDisassembler.
43 virtual DecodeStatus getInstruction(MCInst &instr,
45 const MemoryObject ®ion,
48 raw_ostream &cStream) const;
50 OwningPtr<const MCRegisterInfo> RegInfo;
56 extern Target TheSparcTarget, TheSparcV9Target;
59 static MCDisassembler *createSparcDisassembler(
61 const MCSubtargetInfo &STI) {
62 return new SparcDisassembler(STI, T.createMCRegInfo(""));
66 extern "C" void LLVMInitializeSparcDisassembler() {
67 // Register the disassembler.
68 TargetRegistry::RegisterMCDisassembler(TheSparcTarget,
69 createSparcDisassembler);
70 TargetRegistry::RegisterMCDisassembler(TheSparcV9Target,
71 createSparcDisassembler);
76 static const unsigned IntRegDecoderTable[] = {
77 SP::G0, SP::G1, SP::G2, SP::G3,
78 SP::G4, SP::G5, SP::G6, SP::G7,
79 SP::O0, SP::O1, SP::O2, SP::O3,
80 SP::O4, SP::O5, SP::O6, SP::O7,
81 SP::L0, SP::L1, SP::L2, SP::L3,
82 SP::L4, SP::L5, SP::L6, SP::L7,
83 SP::I0, SP::I1, SP::I2, SP::I3,
84 SP::I4, SP::I5, SP::I6, SP::I7 };
86 static const unsigned FPRegDecoderTable[] = {
87 SP::F0, SP::F1, SP::F2, SP::F3,
88 SP::F4, SP::F5, SP::F6, SP::F7,
89 SP::F8, SP::F9, SP::F10, SP::F11,
90 SP::F12, SP::F13, SP::F14, SP::F15,
91 SP::F16, SP::F17, SP::F18, SP::F19,
92 SP::F20, SP::F21, SP::F22, SP::F23,
93 SP::F24, SP::F25, SP::F26, SP::F27,
94 SP::F28, SP::F29, SP::F30, SP::F31 };
96 static const unsigned DFPRegDecoderTable[] = {
97 SP::D0, SP::D16, SP::D1, SP::D17,
98 SP::D2, SP::D18, SP::D3, SP::D19,
99 SP::D4, SP::D20, SP::D5, SP::D21,
100 SP::D6, SP::D22, SP::D7, SP::D23,
101 SP::D8, SP::D24, SP::D9, SP::D25,
102 SP::D10, SP::D26, SP::D11, SP::D27,
103 SP::D12, SP::D28, SP::D13, SP::D29,
104 SP::D14, SP::D30, SP::D15, SP::D31 };
106 static const unsigned QFPRegDecoderTable[] = {
107 SP::Q0, SP::Q8, ~0U, ~0U,
108 SP::Q1, SP::Q9, ~0U, ~0U,
109 SP::Q2, SP::Q10, ~0U, ~0U,
110 SP::Q3, SP::Q11, ~0U, ~0U,
111 SP::Q4, SP::Q12, ~0U, ~0U,
112 SP::Q5, SP::Q13, ~0U, ~0U,
113 SP::Q6, SP::Q14, ~0U, ~0U,
114 SP::Q7, SP::Q15, ~0U, ~0U } ;
116 static const unsigned FCCRegDecoderTable[] = {
117 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
119 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
122 const void *Decoder) {
124 return MCDisassembler::Fail;
125 unsigned Reg = IntRegDecoderTable[RegNo];
126 Inst.addOperand(MCOperand::CreateReg(Reg));
127 return MCDisassembler::Success;
130 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst,
133 const void *Decoder) {
135 return MCDisassembler::Fail;
136 unsigned Reg = IntRegDecoderTable[RegNo];
137 Inst.addOperand(MCOperand::CreateReg(Reg));
138 return MCDisassembler::Success;
142 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst,
145 const void *Decoder) {
147 return MCDisassembler::Fail;
148 unsigned Reg = FPRegDecoderTable[RegNo];
149 Inst.addOperand(MCOperand::CreateReg(Reg));
150 return MCDisassembler::Success;
154 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst,
157 const void *Decoder) {
159 return MCDisassembler::Fail;
160 unsigned Reg = DFPRegDecoderTable[RegNo];
161 Inst.addOperand(MCOperand::CreateReg(Reg));
162 return MCDisassembler::Success;
166 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
169 const void *Decoder) {
171 return MCDisassembler::Fail;
173 unsigned Reg = QFPRegDecoderTable[RegNo];
175 return MCDisassembler::Fail;
176 Inst.addOperand(MCOperand::CreateReg(Reg));
177 return MCDisassembler::Success;
180 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
182 const void *Decoder) {
184 return MCDisassembler::Fail;
185 Inst.addOperand(MCOperand::CreateReg(FCCRegDecoderTable[RegNo]));
186 return MCDisassembler::Success;
190 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
191 const void *Decoder);
192 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
193 const void *Decoder);
194 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
195 const void *Decoder);
196 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
197 const void *Decoder);
198 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
199 uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
201 uint64_t Address, const void *Decoder);
202 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
203 uint64_t Address, const void *Decoder);
204 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
205 uint64_t Address, const void *Decoder);
206 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
207 uint64_t Address, const void *Decoder);
208 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
209 uint64_t Address, const void *Decoder);
210 static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
211 const void *Decoder);
212 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
213 const void *Decoder);
215 #include "SparcGenDisassemblerTables.inc"
217 /// readInstruction - read four bytes from the MemoryObject
218 /// and return 32 bit word.
219 static DecodeStatus readInstruction32(const MemoryObject ®ion,
225 // We want to read exactly 4 Bytes of data.
226 if (region.readBytes(address, 4, Bytes) == -1) {
228 return MCDisassembler::Fail;
231 // Encoded as a big-endian 32-bit word in the stream.
232 insn = (Bytes[3] << 0) |
237 return MCDisassembler::Success;
242 SparcDisassembler::getInstruction(MCInst &instr,
244 const MemoryObject &Region,
246 raw_ostream &vStream,
247 raw_ostream &cStream) const {
250 DecodeStatus Result = readInstruction32(Region, Address, Size, Insn);
251 if (Result == MCDisassembler::Fail)
252 return MCDisassembler::Fail;
255 // Calling the auto-generated decoder function.
256 Result = decodeInstruction(DecoderTableSparc32, instr, Insn, Address,
259 if (Result != MCDisassembler::Fail) {
264 return MCDisassembler::Fail;
268 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
269 const void *Decoder);
271 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
273 bool isLoad, DecodeFunc DecodeRD) {
274 unsigned rd = fieldFromInstruction(insn, 25, 5);
275 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
276 bool isImm = fieldFromInstruction(insn, 13, 1);
280 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
282 rs2 = fieldFromInstruction(insn, 0, 5);
286 status = DecodeRD(MI, rd, Address, Decoder);
287 if (status != MCDisassembler::Success)
292 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
293 if (status != MCDisassembler::Success)
298 MI.addOperand(MCOperand::CreateImm(simm13));
300 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
301 if (status != MCDisassembler::Success)
306 status = DecodeRD(MI, rd, Address, Decoder);
307 if (status != MCDisassembler::Success)
310 return MCDisassembler::Success;
313 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
314 const void *Decoder) {
315 return DecodeMem(Inst, insn, Address, Decoder, true,
316 DecodeIntRegsRegisterClass);
319 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
320 const void *Decoder) {
321 return DecodeMem(Inst, insn, Address, Decoder, true,
322 DecodeFPRegsRegisterClass);
325 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
326 const void *Decoder) {
327 return DecodeMem(Inst, insn, Address, Decoder, true,
328 DecodeDFPRegsRegisterClass);
331 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
332 const void *Decoder) {
333 return DecodeMem(Inst, insn, Address, Decoder, true,
334 DecodeQFPRegsRegisterClass);
337 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
338 uint64_t Address, const void *Decoder) {
339 return DecodeMem(Inst, insn, Address, Decoder, false,
340 DecodeIntRegsRegisterClass);
343 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
344 const void *Decoder) {
345 return DecodeMem(Inst, insn, Address, Decoder, false,
346 DecodeFPRegsRegisterClass);
349 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
350 uint64_t Address, const void *Decoder) {
351 return DecodeMem(Inst, insn, Address, Decoder, false,
352 DecodeDFPRegsRegisterClass);
355 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
356 uint64_t Address, const void *Decoder) {
357 return DecodeMem(Inst, insn, Address, Decoder, false,
358 DecodeQFPRegsRegisterClass);
361 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
362 uint64_t Address, uint64_t Offset,
363 uint64_t Width, MCInst &MI,
364 const void *Decoder) {
365 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
366 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
370 static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
371 uint64_t Address, const void *Decoder) {
372 unsigned tgt = fieldFromInstruction(insn, 0, 30);
374 if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
376 MI.addOperand(MCOperand::CreateImm(tgt));
377 return MCDisassembler::Success;
380 static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
381 uint64_t Address, const void *Decoder) {
382 unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
383 MI.addOperand(MCOperand::CreateImm(tgt));
384 return MCDisassembler::Success;
387 static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
388 const void *Decoder) {
390 unsigned rd = fieldFromInstruction(insn, 25, 5);
391 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
392 unsigned isImm = fieldFromInstruction(insn, 13, 1);
396 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
398 rs2 = fieldFromInstruction(insn, 0, 5);
401 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
402 if (status != MCDisassembler::Success)
406 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
407 if (status != MCDisassembler::Success)
410 // Decode RS1 | SIMM13.
412 MI.addOperand(MCOperand::CreateImm(simm13));
414 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
415 if (status != MCDisassembler::Success)
418 return MCDisassembler::Success;
421 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
422 const void *Decoder) {
424 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
425 unsigned isImm = fieldFromInstruction(insn, 13, 1);
429 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
431 rs2 = fieldFromInstruction(insn, 0, 5);
434 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
435 if (status != MCDisassembler::Success)
438 // Decode RS2 | SIMM13.
440 MI.addOperand(MCOperand::CreateImm(simm13));
442 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
443 if (status != MCDisassembler::Success)
446 return MCDisassembler::Success;