1 //===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Sparc Disassembler.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "sparc-disassembler"
17 #include "SparcRegisterInfo.h"
18 #include "SparcSubtarget.h"
19 #include "llvm/MC/MCDisassembler.h"
20 #include "llvm/MC/MCFixedLenDisassembler.h"
21 #include "llvm/Support/MemoryObject.h"
22 #include "llvm/Support/TargetRegistry.h"
26 typedef MCDisassembler::DecodeStatus DecodeStatus;
30 /// SparcDisassembler - a disassembler class for Sparc.
31 class SparcDisassembler : public MCDisassembler {
33 /// Constructor - Initializes the disassembler.
35 SparcDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
36 MCDisassembler(STI), RegInfo(Info)
38 virtual ~SparcDisassembler() {}
40 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
42 /// getInstruction - See MCDisassembler.
43 virtual DecodeStatus getInstruction(MCInst &instr,
45 const MemoryObject ®ion,
48 raw_ostream &cStream) const;
50 OwningPtr<const MCRegisterInfo> RegInfo;
56 extern Target TheSparcTarget, TheSparcV9Target;
59 static MCDisassembler *createSparcDisassembler(
61 const MCSubtargetInfo &STI) {
62 return new SparcDisassembler(STI, T.createMCRegInfo(""));
66 extern "C" void LLVMInitializeSparcDisassembler() {
67 // Register the disassembler.
68 TargetRegistry::RegisterMCDisassembler(TheSparcTarget,
69 createSparcDisassembler);
70 TargetRegistry::RegisterMCDisassembler(TheSparcV9Target,
71 createSparcDisassembler);
76 static const unsigned IntRegDecoderTable[] = {
77 SP::G0, SP::G1, SP::G2, SP::G3,
78 SP::G4, SP::G5, SP::G6, SP::G7,
79 SP::O0, SP::O1, SP::O2, SP::O3,
80 SP::O4, SP::O5, SP::O6, SP::O7,
81 SP::L0, SP::L1, SP::L2, SP::L3,
82 SP::L4, SP::L5, SP::L6, SP::L7,
83 SP::I0, SP::I1, SP::I2, SP::I3,
84 SP::I4, SP::I5, SP::I6, SP::I7 };
86 static const unsigned FPRegDecoderTable[] = {
87 SP::F0, SP::F1, SP::F2, SP::F3,
88 SP::F4, SP::F5, SP::F6, SP::F7,
89 SP::F8, SP::F9, SP::F10, SP::F11,
90 SP::F12, SP::F13, SP::F14, SP::F15,
91 SP::F16, SP::F17, SP::F18, SP::F19,
92 SP::F20, SP::F21, SP::F22, SP::F23,
93 SP::F24, SP::F25, SP::F26, SP::F27,
94 SP::F28, SP::F29, SP::F30, SP::F31 };
96 static const unsigned DFPRegDecoderTable[] = {
97 SP::D0, SP::D16, SP::D1, SP::D17,
98 SP::D2, SP::D18, SP::D3, SP::D19,
99 SP::D4, SP::D20, SP::D5, SP::D21,
100 SP::D6, SP::D22, SP::D7, SP::D23,
101 SP::D8, SP::D24, SP::D9, SP::D25,
102 SP::D10, SP::D26, SP::D11, SP::D27,
103 SP::D12, SP::D28, SP::D13, SP::D29,
104 SP::D14, SP::D30, SP::D15, SP::D31 };
106 static const unsigned QFPRegDecoderTable[] = {
107 SP::Q0, SP::Q8, ~0U, ~0U,
108 SP::Q1, SP::Q9, ~0U, ~0U,
109 SP::Q2, SP::Q10, ~0U, ~0U,
110 SP::Q3, SP::Q11, ~0U, ~0U,
111 SP::Q4, SP::Q12, ~0U, ~0U,
112 SP::Q5, SP::Q13, ~0U, ~0U,
113 SP::Q6, SP::Q14, ~0U, ~0U,
114 SP::Q7, SP::Q15, ~0U, ~0U } ;
116 static const unsigned FCCRegDecoderTable[] = {
117 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
119 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
122 const void *Decoder) {
124 return MCDisassembler::Fail;
125 unsigned Reg = IntRegDecoderTable[RegNo];
126 Inst.addOperand(MCOperand::CreateReg(Reg));
127 return MCDisassembler::Success;
130 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst,
133 const void *Decoder) {
135 return MCDisassembler::Fail;
136 unsigned Reg = IntRegDecoderTable[RegNo];
137 Inst.addOperand(MCOperand::CreateReg(Reg));
138 return MCDisassembler::Success;
142 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst,
145 const void *Decoder) {
147 return MCDisassembler::Fail;
148 unsigned Reg = FPRegDecoderTable[RegNo];
149 Inst.addOperand(MCOperand::CreateReg(Reg));
150 return MCDisassembler::Success;
154 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst,
157 const void *Decoder) {
159 return MCDisassembler::Fail;
160 unsigned Reg = DFPRegDecoderTable[RegNo];
161 Inst.addOperand(MCOperand::CreateReg(Reg));
162 return MCDisassembler::Success;
166 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
169 const void *Decoder) {
171 return MCDisassembler::Fail;
173 unsigned Reg = QFPRegDecoderTable[RegNo];
175 return MCDisassembler::Fail;
176 Inst.addOperand(MCOperand::CreateReg(Reg));
177 return MCDisassembler::Success;
180 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
182 const void *Decoder) {
184 return MCDisassembler::Fail;
185 Inst.addOperand(MCOperand::CreateReg(FCCRegDecoderTable[RegNo]));
186 return MCDisassembler::Success;
190 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
191 const void *Decoder);
192 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
193 const void *Decoder);
194 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
195 const void *Decoder);
196 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
197 const void *Decoder);
198 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
199 uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
201 uint64_t Address, const void *Decoder);
202 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
203 uint64_t Address, const void *Decoder);
204 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
205 uint64_t Address, const void *Decoder);
206 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
207 uint64_t Address, const void *Decoder);
208 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
209 uint64_t Address, const void *Decoder);
210 static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
211 const void *Decoder);
213 #include "SparcGenDisassemblerTables.inc"
215 /// readInstruction - read four bytes from the MemoryObject
216 /// and return 32 bit word.
217 static DecodeStatus readInstruction32(const MemoryObject ®ion,
223 // We want to read exactly 4 Bytes of data.
224 if (region.readBytes(address, 4, Bytes) == -1) {
226 return MCDisassembler::Fail;
229 // Encoded as a big-endian 32-bit word in the stream.
230 insn = (Bytes[3] << 0) |
235 return MCDisassembler::Success;
240 SparcDisassembler::getInstruction(MCInst &instr,
242 const MemoryObject &Region,
244 raw_ostream &vStream,
245 raw_ostream &cStream) const {
248 DecodeStatus Result = readInstruction32(Region, Address, Size, Insn);
249 if (Result == MCDisassembler::Fail)
250 return MCDisassembler::Fail;
253 // Calling the auto-generated decoder function.
254 Result = decodeInstruction(DecoderTableSparc32, instr, Insn, Address,
257 if (Result != MCDisassembler::Fail) {
262 return MCDisassembler::Fail;
266 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
267 const void *Decoder);
269 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
271 bool isLoad, DecodeFunc DecodeRD) {
272 unsigned rd = fieldFromInstruction(insn, 25, 5);
273 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
274 bool isImm = fieldFromInstruction(insn, 13, 1);
278 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
280 rs2 = fieldFromInstruction(insn, 0, 5);
284 status = DecodeRD(MI, rd, Address, Decoder);
285 if (status != MCDisassembler::Success)
290 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
291 if (status != MCDisassembler::Success)
296 MI.addOperand(MCOperand::CreateImm(simm13));
298 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
299 if (status != MCDisassembler::Success)
304 status = DecodeRD(MI, rd, Address, Decoder);
305 if (status != MCDisassembler::Success)
308 return MCDisassembler::Success;
311 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
312 const void *Decoder) {
313 return DecodeMem(Inst, insn, Address, Decoder, true,
314 DecodeIntRegsRegisterClass);
317 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
318 const void *Decoder) {
319 return DecodeMem(Inst, insn, Address, Decoder, true,
320 DecodeFPRegsRegisterClass);
323 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
324 const void *Decoder) {
325 return DecodeMem(Inst, insn, Address, Decoder, true,
326 DecodeDFPRegsRegisterClass);
329 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
330 const void *Decoder) {
331 return DecodeMem(Inst, insn, Address, Decoder, true,
332 DecodeQFPRegsRegisterClass);
335 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
336 uint64_t Address, const void *Decoder) {
337 return DecodeMem(Inst, insn, Address, Decoder, false,
338 DecodeIntRegsRegisterClass);
341 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
342 const void *Decoder) {
343 return DecodeMem(Inst, insn, Address, Decoder, false,
344 DecodeFPRegsRegisterClass);
347 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
348 uint64_t Address, const void *Decoder) {
349 return DecodeMem(Inst, insn, Address, Decoder, false,
350 DecodeDFPRegsRegisterClass);
353 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
354 uint64_t Address, const void *Decoder) {
355 return DecodeMem(Inst, insn, Address, Decoder, false,
356 DecodeQFPRegsRegisterClass);
359 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
360 uint64_t Address, uint64_t Offset,
361 uint64_t Width, MCInst &MI,
362 const void *Decoder) {
363 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
364 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
368 static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
369 uint64_t Address, const void *Decoder) {
370 unsigned tgt = fieldFromInstruction(insn, 0, 30);
372 if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
374 MI.addOperand(MCOperand::CreateImm(tgt));
375 return MCDisassembler::Success;
378 static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
379 uint64_t Address, const void *Decoder) {
380 unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
381 MI.addOperand(MCOperand::CreateImm(tgt));
382 return MCDisassembler::Success;
385 static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
386 const void *Decoder) {
388 unsigned rd = fieldFromInstruction(insn, 25, 5);
389 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
390 unsigned isImm = fieldFromInstruction(insn, 13, 1);
394 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
396 rs2 = fieldFromInstruction(insn, 0, 5);
399 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
400 if (status != MCDisassembler::Success)
404 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
405 if (status != MCDisassembler::Success)
408 // Decode RS1 | SIMM13.
410 MI.addOperand(MCOperand::CreateImm(simm13));
412 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
413 if (status != MCDisassembler::Success)
416 return MCDisassembler::Success;