1 //===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Sparc Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "SparcRegisterInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/MC/MCDisassembler.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/Support/TargetRegistry.h"
25 #define DEBUG_TYPE "sparc-disassembler"
27 typedef MCDisassembler::DecodeStatus DecodeStatus;
31 /// A disassembler class for Sparc.
32 class SparcDisassembler : public MCDisassembler {
34 SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
35 : MCDisassembler(STI, Ctx) {}
36 virtual ~SparcDisassembler() {}
38 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
39 ArrayRef<uint8_t> Bytes, uint64_t Address,
41 raw_ostream &CStream) const override;
46 extern Target TheSparcTarget, TheSparcV9Target, TheSparcelTarget;
49 static MCDisassembler *createSparcDisassembler(const Target &T,
50 const MCSubtargetInfo &STI,
52 return new SparcDisassembler(STI, Ctx);
56 extern "C" void LLVMInitializeSparcDisassembler() {
57 // Register the disassembler.
58 TargetRegistry::RegisterMCDisassembler(TheSparcTarget,
59 createSparcDisassembler);
60 TargetRegistry::RegisterMCDisassembler(TheSparcV9Target,
61 createSparcDisassembler);
62 TargetRegistry::RegisterMCDisassembler(TheSparcelTarget,
63 createSparcDisassembler);
66 static const unsigned IntRegDecoderTable[] = {
67 SP::G0, SP::G1, SP::G2, SP::G3,
68 SP::G4, SP::G5, SP::G6, SP::G7,
69 SP::O0, SP::O1, SP::O2, SP::O3,
70 SP::O4, SP::O5, SP::O6, SP::O7,
71 SP::L0, SP::L1, SP::L2, SP::L3,
72 SP::L4, SP::L5, SP::L6, SP::L7,
73 SP::I0, SP::I1, SP::I2, SP::I3,
74 SP::I4, SP::I5, SP::I6, SP::I7 };
76 static const unsigned FPRegDecoderTable[] = {
77 SP::F0, SP::F1, SP::F2, SP::F3,
78 SP::F4, SP::F5, SP::F6, SP::F7,
79 SP::F8, SP::F9, SP::F10, SP::F11,
80 SP::F12, SP::F13, SP::F14, SP::F15,
81 SP::F16, SP::F17, SP::F18, SP::F19,
82 SP::F20, SP::F21, SP::F22, SP::F23,
83 SP::F24, SP::F25, SP::F26, SP::F27,
84 SP::F28, SP::F29, SP::F30, SP::F31 };
86 static const unsigned DFPRegDecoderTable[] = {
87 SP::D0, SP::D16, SP::D1, SP::D17,
88 SP::D2, SP::D18, SP::D3, SP::D19,
89 SP::D4, SP::D20, SP::D5, SP::D21,
90 SP::D6, SP::D22, SP::D7, SP::D23,
91 SP::D8, SP::D24, SP::D9, SP::D25,
92 SP::D10, SP::D26, SP::D11, SP::D27,
93 SP::D12, SP::D28, SP::D13, SP::D29,
94 SP::D14, SP::D30, SP::D15, SP::D31 };
96 static const unsigned QFPRegDecoderTable[] = {
97 SP::Q0, SP::Q8, ~0U, ~0U,
98 SP::Q1, SP::Q9, ~0U, ~0U,
99 SP::Q2, SP::Q10, ~0U, ~0U,
100 SP::Q3, SP::Q11, ~0U, ~0U,
101 SP::Q4, SP::Q12, ~0U, ~0U,
102 SP::Q5, SP::Q13, ~0U, ~0U,
103 SP::Q6, SP::Q14, ~0U, ~0U,
104 SP::Q7, SP::Q15, ~0U, ~0U } ;
106 static const unsigned FCCRegDecoderTable[] = {
107 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
109 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
112 const void *Decoder) {
114 return MCDisassembler::Fail;
115 unsigned Reg = IntRegDecoderTable[RegNo];
116 Inst.addOperand(MCOperand::createReg(Reg));
117 return MCDisassembler::Success;
120 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst,
123 const void *Decoder) {
125 return MCDisassembler::Fail;
126 unsigned Reg = IntRegDecoderTable[RegNo];
127 Inst.addOperand(MCOperand::createReg(Reg));
128 return MCDisassembler::Success;
132 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst,
135 const void *Decoder) {
137 return MCDisassembler::Fail;
138 unsigned Reg = FPRegDecoderTable[RegNo];
139 Inst.addOperand(MCOperand::createReg(Reg));
140 return MCDisassembler::Success;
144 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst,
147 const void *Decoder) {
149 return MCDisassembler::Fail;
150 unsigned Reg = DFPRegDecoderTable[RegNo];
151 Inst.addOperand(MCOperand::createReg(Reg));
152 return MCDisassembler::Success;
156 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
159 const void *Decoder) {
161 return MCDisassembler::Fail;
163 unsigned Reg = QFPRegDecoderTable[RegNo];
165 return MCDisassembler::Fail;
166 Inst.addOperand(MCOperand::createReg(Reg));
167 return MCDisassembler::Success;
170 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
172 const void *Decoder) {
174 return MCDisassembler::Fail;
175 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo]));
176 return MCDisassembler::Success;
180 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
181 const void *Decoder);
182 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
183 const void *Decoder);
184 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
185 const void *Decoder);
186 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
187 const void *Decoder);
188 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
199 uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
201 const void *Decoder);
202 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
203 const void *Decoder);
204 static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address,
205 const void *Decoder);
207 #include "SparcGenDisassemblerTables.inc"
209 /// Read four bytes from the ArrayRef and return 32 bit word.
210 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
211 uint64_t &Size, uint32_t &Insn,
212 bool IsLittleEndian) {
213 // We want to read exactly 4 Bytes of data.
214 if (Bytes.size() < 4) {
216 return MCDisassembler::Fail;
219 Insn = IsLittleEndian
220 ? (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
222 : (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) |
225 return MCDisassembler::Success;
228 DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
229 ArrayRef<uint8_t> Bytes,
231 raw_ostream &VStream,
232 raw_ostream &CStream) const {
234 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();
235 DecodeStatus Result =
236 readInstruction32(Bytes, Address, Size, Insn, isLittleEndian);
237 if (Result == MCDisassembler::Fail)
238 return MCDisassembler::Fail;
240 // Calling the auto-generated decoder function.
242 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI);
244 if (Result != MCDisassembler::Fail) {
249 return MCDisassembler::Fail;
253 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
254 const void *Decoder);
256 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
258 bool isLoad, DecodeFunc DecodeRD) {
259 unsigned rd = fieldFromInstruction(insn, 25, 5);
260 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
261 bool isImm = fieldFromInstruction(insn, 13, 1);
265 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
267 rs2 = fieldFromInstruction(insn, 0, 5);
271 status = DecodeRD(MI, rd, Address, Decoder);
272 if (status != MCDisassembler::Success)
277 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
278 if (status != MCDisassembler::Success)
283 MI.addOperand(MCOperand::createImm(simm13));
285 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
286 if (status != MCDisassembler::Success)
291 status = DecodeRD(MI, rd, Address, Decoder);
292 if (status != MCDisassembler::Success)
295 return MCDisassembler::Success;
298 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
299 const void *Decoder) {
300 return DecodeMem(Inst, insn, Address, Decoder, true,
301 DecodeIntRegsRegisterClass);
304 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
305 const void *Decoder) {
306 return DecodeMem(Inst, insn, Address, Decoder, true,
307 DecodeFPRegsRegisterClass);
310 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
311 const void *Decoder) {
312 return DecodeMem(Inst, insn, Address, Decoder, true,
313 DecodeDFPRegsRegisterClass);
316 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
317 const void *Decoder) {
318 return DecodeMem(Inst, insn, Address, Decoder, true,
319 DecodeQFPRegsRegisterClass);
322 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
323 uint64_t Address, const void *Decoder) {
324 return DecodeMem(Inst, insn, Address, Decoder, false,
325 DecodeIntRegsRegisterClass);
328 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
329 const void *Decoder) {
330 return DecodeMem(Inst, insn, Address, Decoder, false,
331 DecodeFPRegsRegisterClass);
334 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
335 uint64_t Address, const void *Decoder) {
336 return DecodeMem(Inst, insn, Address, Decoder, false,
337 DecodeDFPRegsRegisterClass);
340 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
341 uint64_t Address, const void *Decoder) {
342 return DecodeMem(Inst, insn, Address, Decoder, false,
343 DecodeQFPRegsRegisterClass);
346 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
347 uint64_t Address, uint64_t Offset,
348 uint64_t Width, MCInst &MI,
349 const void *Decoder) {
350 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
351 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
355 static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
356 uint64_t Address, const void *Decoder) {
357 unsigned tgt = fieldFromInstruction(insn, 0, 30);
359 if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
361 MI.addOperand(MCOperand::createImm(tgt));
362 return MCDisassembler::Success;
365 static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
366 uint64_t Address, const void *Decoder) {
367 unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
368 MI.addOperand(MCOperand::createImm(tgt));
369 return MCDisassembler::Success;
372 static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
373 const void *Decoder) {
375 unsigned rd = fieldFromInstruction(insn, 25, 5);
376 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
377 unsigned isImm = fieldFromInstruction(insn, 13, 1);
381 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
383 rs2 = fieldFromInstruction(insn, 0, 5);
386 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
387 if (status != MCDisassembler::Success)
391 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
392 if (status != MCDisassembler::Success)
395 // Decode RS1 | SIMM13.
397 MI.addOperand(MCOperand::createImm(simm13));
399 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
400 if (status != MCDisassembler::Success)
403 return MCDisassembler::Success;
406 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
407 const void *Decoder) {
409 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
410 unsigned isImm = fieldFromInstruction(insn, 13, 1);
414 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
416 rs2 = fieldFromInstruction(insn, 0, 5);
419 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
420 if (status != MCDisassembler::Success)
423 // Decode RS2 | SIMM13.
425 MI.addOperand(MCOperand::createImm(simm13));
427 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
428 if (status != MCDisassembler::Success)
431 return MCDisassembler::Success;
434 static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
435 const void *Decoder) {
437 unsigned rd = fieldFromInstruction(insn, 25, 5);
438 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
439 unsigned isImm = fieldFromInstruction(insn, 13, 1);
443 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
445 rs2 = fieldFromInstruction(insn, 0, 5);
448 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
449 if (status != MCDisassembler::Success)
453 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
454 if (status != MCDisassembler::Success)
457 // Decode RS1 | SIMM13.
459 MI.addOperand(MCOperand::createImm(simm13));
461 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
462 if (status != MCDisassembler::Success)
465 return MCDisassembler::Success;