1 //===-- DelaySlotFiller.cpp - SPARC delay slot filler ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a simple local pass that attempts to fill delay slots with useful
11 // instructions. If no instructions can be moved into the delay slot, then a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "delay-slot-filler"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
28 STATISTIC(FilledSlots, "Number of delay slots filled");
30 static cl::opt<bool> DisableDelaySlotFiller(
31 "disable-sparc-delay-filler",
33 cl::desc("Disable the Sparc delay slot filler."),
37 struct Filler : public MachineFunctionPass {
38 /// Target machine description which we query for reg. names, data
42 const TargetInstrInfo *TII;
45 Filler(TargetMachine &tm)
46 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
48 virtual const char *getPassName() const {
49 return "SPARC Delay Slot Filler";
52 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
53 bool runOnMachineFunction(MachineFunction &F) {
55 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
57 Changed |= runOnMachineBasicBlock(*FI);
61 bool isDelayFiller(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator candidate);
64 void insertCallDefsUses(MachineBasicBlock::iterator MI,
65 SmallSet<unsigned, 32>& RegDefs,
66 SmallSet<unsigned, 32>& RegUses);
68 void insertDefsUses(MachineBasicBlock::iterator MI,
69 SmallSet<unsigned, 32>& RegDefs,
70 SmallSet<unsigned, 32>& RegUses);
72 bool IsRegInSet(SmallSet<unsigned, 32>& RegSet,
75 bool delayHasHazard(MachineBasicBlock::iterator candidate,
76 bool &sawLoad, bool &sawStore,
77 SmallSet<unsigned, 32> &RegDefs,
78 SmallSet<unsigned, 32> &RegUses);
80 MachineBasicBlock::iterator
81 findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot);
83 bool needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize);
87 } // end of anonymous namespace
89 /// createSparcDelaySlotFillerPass - Returns a pass that fills in delay
90 /// slots in Sparc MachineFunctions
92 FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) {
93 return new Filler(tm);
97 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
98 /// We assume there is only one delay slot per delayed instruction.
100 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
101 bool Changed = false;
103 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
104 if (I->hasDelaySlot()) {
105 MachineBasicBlock::iterator D = MBB.end();
106 MachineBasicBlock::iterator J = I;
108 if (!DisableDelaySlotFiller)
109 D = findDelayInstr(MBB, I);
115 BuildMI(MBB, ++J, I->getDebugLoc(), TII->get(SP::NOP));
117 MBB.splice(++J, &MBB, D);
118 unsigned structSize = 0;
119 if (needsUnimp(I, structSize)) {
120 MachineBasicBlock::iterator J = I;
121 ++J; //skip the delay filler.
122 BuildMI(MBB, ++J, I->getDebugLoc(),
123 TII->get(SP::UNIMP)).addImm(structSize);
129 MachineBasicBlock::iterator
130 Filler::findDelayInstr(MachineBasicBlock &MBB,
131 MachineBasicBlock::iterator slot)
133 SmallSet<unsigned, 32> RegDefs;
134 SmallSet<unsigned, 32> RegUses;
135 bool sawLoad = false;
136 bool sawStore = false;
138 MachineBasicBlock::iterator I = slot;
140 if (slot->getOpcode() == SP::RET)
143 if (slot->getOpcode() == SP::RETL) {
145 if (I->getOpcode() != SP::RESTORErr)
148 slot->setDesc(TII->get(SP::RET));
152 //Call's delay filler can def some of call's uses.
154 insertCallDefsUses(slot, RegDefs, RegUses);
156 insertDefsUses(slot, RegDefs, RegUses);
161 done = (I == MBB.begin());
167 if (I->isDebugValue())
171 if (I->hasUnmodeledSideEffects()
175 || isDelayFiller(MBB, I))
178 if (delayHasHazard(I, sawLoad, sawStore, RegDefs, RegUses)) {
179 insertDefsUses(I, RegDefs, RegUses);
188 bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate,
191 SmallSet<unsigned, 32> &RegDefs,
192 SmallSet<unsigned, 32> &RegUses)
195 if (candidate->isImplicitDef() || candidate->isKill())
198 if (candidate->mayLoad()) {
204 if (candidate->mayStore()) {
212 for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
213 const MachineOperand &MO = candidate->getOperand(i);
217 unsigned Reg = MO.getReg();
220 //check whether Reg is defined or used before delay slot.
221 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
225 //check whether Reg is defined before delay slot.
226 if (IsRegInSet(RegDefs, Reg))
234 void Filler::insertCallDefsUses(MachineBasicBlock::iterator MI,
235 SmallSet<unsigned, 32>& RegDefs,
236 SmallSet<unsigned, 32>& RegUses)
238 //Call defines o7, which is visible to the instruction in delay slot.
239 RegDefs.insert(SP::O7);
241 switch(MI->getOpcode()) {
242 default: llvm_unreachable("Unknown opcode.");
243 case SP::CALL: break;
246 assert(MI->getNumOperands() >= 2);
247 const MachineOperand &Reg = MI->getOperand(0);
248 assert(Reg.isReg() && "JMPL first operand is not a register.");
249 assert(Reg.isUse() && "JMPL first operand is not a use.");
250 RegUses.insert(Reg.getReg());
252 const MachineOperand &RegOrImm = MI->getOperand(1);
253 if (RegOrImm.isImm())
255 assert(RegOrImm.isReg() && "JMPLrr second operand is not a register.");
256 assert(RegOrImm.isUse() && "JMPLrr second operand is not a use.");
257 RegUses.insert(RegOrImm.getReg());
262 //Insert Defs and Uses of MI into the sets RegDefs and RegUses.
263 void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
264 SmallSet<unsigned, 32>& RegDefs,
265 SmallSet<unsigned, 32>& RegUses)
267 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
268 const MachineOperand &MO = MI->getOperand(i);
272 unsigned Reg = MO.getReg();
283 //returns true if the Reg or its alias is in the RegSet.
284 bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg)
286 // Check Reg and all aliased Registers.
287 for (MCRegAliasIterator AI(Reg, TM.getRegisterInfo(), true);
289 if (RegSet.count(*AI))
294 // return true if the candidate is a delay filler.
295 bool Filler::isDelayFiller(MachineBasicBlock &MBB,
296 MachineBasicBlock::iterator candidate)
298 if (candidate == MBB.begin())
300 if (candidate->getOpcode() == SP::UNIMP)
303 return candidate->hasDelaySlot();
306 bool Filler::needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize)
311 unsigned structSizeOpNum = 0;
312 switch (I->getOpcode()) {
313 default: llvm_unreachable("Unknown call opcode.");
314 case SP::CALL: structSizeOpNum = 1; break;
316 case SP::JMPLri: structSizeOpNum = 2; break;
319 const MachineOperand &MO = I->getOperand(structSizeOpNum);
322 StructSize = MO.getImm();