1 //===-- DelaySlotFiller.cpp - SPARC delay slot filler ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a simple local pass that attempts to fill delay slots with useful
11 // instructions. If no instructions can be moved into the delay slot, then a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "delay-slot-filler"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
28 STATISTIC(FilledSlots, "Number of delay slots filled");
30 static cl::opt<bool> DisableDelaySlotFiller(
31 "disable-sparc-delay-filler",
33 cl::desc("Disable the Sparc delay slot filler."),
37 struct Filler : public MachineFunctionPass {
38 /// Target machine description which we query for reg. names, data
42 const TargetInstrInfo *TII;
45 Filler(TargetMachine &tm)
46 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
48 virtual const char *getPassName() const {
49 return "SPARC Delay Slot Filler";
52 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
53 bool runOnMachineFunction(MachineFunction &F) {
55 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
57 Changed |= runOnMachineBasicBlock(*FI);
61 bool isDelayFiller(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator candidate);
64 void insertCallDefsUses(MachineBasicBlock::iterator MI,
65 SmallSet<unsigned, 32>& RegDefs,
66 SmallSet<unsigned, 32>& RegUses);
68 void insertDefsUses(MachineBasicBlock::iterator MI,
69 SmallSet<unsigned, 32>& RegDefs,
70 SmallSet<unsigned, 32>& RegUses);
72 bool IsRegInSet(SmallSet<unsigned, 32>& RegSet,
75 bool delayHasHazard(MachineBasicBlock::iterator candidate,
76 bool &sawLoad, bool &sawStore,
77 SmallSet<unsigned, 32> &RegDefs,
78 SmallSet<unsigned, 32> &RegUses);
80 MachineBasicBlock::iterator
81 findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot);
83 bool needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize);
87 } // end of anonymous namespace
89 /// createSparcDelaySlotFillerPass - Returns a pass that fills in delay
90 /// slots in Sparc MachineFunctions
92 FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) {
93 return new Filler(tm);
97 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
98 /// We assume there is only one delay slot per delayed instruction.
100 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
101 bool Changed = false;
103 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
104 if (I->hasDelaySlot()) {
105 MachineBasicBlock::iterator D = MBB.end();
106 MachineBasicBlock::iterator J = I;
108 if (!DisableDelaySlotFiller)
109 D = findDelayInstr(MBB, I);
115 BuildMI(MBB, ++J, I->getDebugLoc(), TII->get(SP::NOP));
117 MBB.splice(++J, &MBB, D);
118 unsigned structSize = 0;
119 if (needsUnimp(I, structSize)) {
120 MachineBasicBlock::iterator J = I;
121 ++J; //skip the delay filler.
122 BuildMI(MBB, ++J, I->getDebugLoc(),
123 TII->get(SP::UNIMP)).addImm(structSize);
129 MachineBasicBlock::iterator
130 Filler::findDelayInstr(MachineBasicBlock &MBB,
131 MachineBasicBlock::iterator slot)
133 SmallSet<unsigned, 32> RegDefs;
134 SmallSet<unsigned, 32> RegUses;
135 bool sawLoad = false;
136 bool sawStore = false;
138 if (slot == MBB.begin())
141 if (slot->getOpcode() == SP::RET)
144 if (slot->getOpcode() == SP::RETL) {
145 MachineBasicBlock::iterator J = slot;
148 if (J->getOpcode() == SP::RESTORErr
149 || J->getOpcode() == SP::RESTOREri) {
151 slot->setDesc(TII->get(SP::RET));
156 //Call's delay filler can def some of call's uses.
158 insertCallDefsUses(slot, RegDefs, RegUses);
160 insertDefsUses(slot, RegDefs, RegUses);
164 MachineBasicBlock::iterator I = slot;
167 done = (I == MBB.begin());
173 if (I->isDebugValue())
177 if (I->hasUnmodeledSideEffects()
181 || isDelayFiller(MBB, I))
184 if (delayHasHazard(I, sawLoad, sawStore, RegDefs, RegUses)) {
185 insertDefsUses(I, RegDefs, RegUses);
194 bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate,
197 SmallSet<unsigned, 32> &RegDefs,
198 SmallSet<unsigned, 32> &RegUses)
201 if (candidate->isImplicitDef() || candidate->isKill())
204 if (candidate->mayLoad()) {
210 if (candidate->mayStore()) {
218 for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
219 const MachineOperand &MO = candidate->getOperand(i);
223 unsigned Reg = MO.getReg();
226 //check whether Reg is defined or used before delay slot.
227 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
231 //check whether Reg is defined before delay slot.
232 if (IsRegInSet(RegDefs, Reg))
240 void Filler::insertCallDefsUses(MachineBasicBlock::iterator MI,
241 SmallSet<unsigned, 32>& RegDefs,
242 SmallSet<unsigned, 32>& RegUses)
244 //Call defines o7, which is visible to the instruction in delay slot.
245 RegDefs.insert(SP::O7);
247 switch(MI->getOpcode()) {
248 default: llvm_unreachable("Unknown opcode.");
249 case SP::CALL: break;
252 assert(MI->getNumOperands() >= 2);
253 const MachineOperand &Reg = MI->getOperand(0);
254 assert(Reg.isReg() && "JMPL first operand is not a register.");
255 assert(Reg.isUse() && "JMPL first operand is not a use.");
256 RegUses.insert(Reg.getReg());
258 const MachineOperand &RegOrImm = MI->getOperand(1);
259 if (RegOrImm.isImm())
261 assert(RegOrImm.isReg() && "JMPLrr second operand is not a register.");
262 assert(RegOrImm.isUse() && "JMPLrr second operand is not a use.");
263 RegUses.insert(RegOrImm.getReg());
268 //Insert Defs and Uses of MI into the sets RegDefs and RegUses.
269 void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
270 SmallSet<unsigned, 32>& RegDefs,
271 SmallSet<unsigned, 32>& RegUses)
273 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
274 const MachineOperand &MO = MI->getOperand(i);
278 unsigned Reg = MO.getReg();
284 //Implicit register uses of retl are return values and
285 //retl does not use them.
286 if (MO.isImplicit() && MI->getOpcode() == SP::RETL)
293 //returns true if the Reg or its alias is in the RegSet.
294 bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg)
296 // Check Reg and all aliased Registers.
297 for (MCRegAliasIterator AI(Reg, TM.getRegisterInfo(), true);
299 if (RegSet.count(*AI))
304 // return true if the candidate is a delay filler.
305 bool Filler::isDelayFiller(MachineBasicBlock &MBB,
306 MachineBasicBlock::iterator candidate)
308 if (candidate == MBB.begin())
310 if (candidate->getOpcode() == SP::UNIMP)
313 return candidate->hasDelaySlot();
316 bool Filler::needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize)
321 unsigned structSizeOpNum = 0;
322 switch (I->getOpcode()) {
323 default: llvm_unreachable("Unknown call opcode.");
324 case SP::CALL: structSizeOpNum = 1; break;
326 case SP::JMPLri: structSizeOpNum = 2; break;
329 const MachineOperand &MO = I->getOperand(structSizeOpNum);
332 StructSize = MO.getImm();