1 //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SparcMCTargetDesc.h"
11 #include "MCTargetDesc/SparcMCExpr.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCObjectFileInfo.h"
16 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/MC/MCSymbol.h"
20 #include "llvm/MC/MCTargetAsmParser.h"
21 #include "llvm/Support/TargetRegistry.h"
25 // The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target
26 // namespace. But SPARC backend uses "SP" as its namespace.
35 class SparcAsmParser : public MCTargetAsmParser {
40 /// @name Auto-generated Match Functions
43 #define GET_ASSEMBLER_HEADER
44 #include "SparcGenAsmMatcher.inc"
48 // public interface of the MCTargetAsmParser.
49 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
50 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
51 MCStreamer &Out, unsigned &ErrorInfo,
52 bool MatchingInlineAsm);
53 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
54 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
56 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
57 bool ParseDirective(AsmToken DirectiveID);
59 virtual unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
62 // Custom parse functions for Sparc specific operands.
64 parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
67 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
71 parseSparcAsmOperand(SparcOperand *&Operand, bool isCall = false);
74 parseBranchModifiers(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
76 // returns true if Tok is matched to a register and returns register in RegNo.
77 bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
80 bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
81 bool parseDirectiveWord(unsigned Size, SMLoc L);
83 bool is64Bit() const { return STI.getTargetTriple().startswith("sparcv9"); }
85 SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
86 const MCInstrInfo &MII)
87 : MCTargetAsmParser(), STI(sti), Parser(parser) {
88 // Initialize the set of available features.
89 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
94 static unsigned IntRegs[32] = {
95 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
96 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
97 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
98 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
99 Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
100 Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
101 Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
102 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
104 static unsigned FloatRegs[32] = {
105 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
106 Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
107 Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
108 Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
109 Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
110 Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
111 Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
112 Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
114 static unsigned DoubleRegs[32] = {
115 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
116 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
117 Sparc::D8, Sparc::D7, Sparc::D8, Sparc::D9,
118 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
119 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
120 Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
121 Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
122 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
124 static unsigned QuadFPRegs[32] = {
125 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
126 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
127 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
128 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
131 /// SparcOperand - Instances of this class represent a parsed Sparc machine
133 class SparcOperand : public MCParsedAsmOperand {
153 SMLoc StartLoc, EndLoc;
155 SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
184 bool isToken() const { return Kind == k_Token; }
185 bool isReg() const { return Kind == k_Register; }
186 bool isImm() const { return Kind == k_Immediate; }
187 bool isMem() const { return isMEMrr() || isMEMri(); }
188 bool isMEMrr() const { return Kind == k_MemoryReg; }
189 bool isMEMri() const { return Kind == k_MemoryImm; }
191 bool isFloatReg() const {
192 return (Kind == k_Register && Reg.Kind == rk_FloatReg);
195 bool isFloatOrDoubleReg() const {
196 return (Kind == k_Register && (Reg.Kind == rk_FloatReg
197 || Reg.Kind == rk_DoubleReg));
201 StringRef getToken() const {
202 assert(Kind == k_Token && "Invalid access!");
203 return StringRef(Tok.Data, Tok.Length);
206 unsigned getReg() const {
207 assert((Kind == k_Register) && "Invalid access!");
211 const MCExpr *getImm() const {
212 assert((Kind == k_Immediate) && "Invalid access!");
216 unsigned getMemBase() const {
217 assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!");
221 unsigned getMemOffsetReg() const {
222 assert((Kind == k_MemoryReg) && "Invalid access!");
223 return Mem.OffsetReg;
226 const MCExpr *getMemOff() const {
227 assert((Kind == k_MemoryImm) && "Invalid access!");
231 /// getStartLoc - Get the location of the first token of this operand.
232 SMLoc getStartLoc() const {
235 /// getEndLoc - Get the location of the last token of this operand.
236 SMLoc getEndLoc() const {
240 virtual void print(raw_ostream &OS) const {
242 case k_Token: OS << "Token: " << getToken() << "\n"; break;
243 case k_Register: OS << "Reg: #" << getReg() << "\n"; break;
244 case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
245 case k_MemoryReg: OS << "Mem: " << getMemBase() << "+"
246 << getMemOffsetReg() << "\n"; break;
247 case k_MemoryImm: assert(getMemOff() != 0);
248 OS << "Mem: " << getMemBase()
249 << "+" << *getMemOff()
254 void addRegOperands(MCInst &Inst, unsigned N) const {
255 assert(N == 1 && "Invalid number of operands!");
256 Inst.addOperand(MCOperand::CreateReg(getReg()));
259 void addImmOperands(MCInst &Inst, unsigned N) const {
260 assert(N == 1 && "Invalid number of operands!");
261 const MCExpr *Expr = getImm();
265 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
266 // Add as immediate when possible. Null MCExpr = 0.
268 Inst.addOperand(MCOperand::CreateImm(0));
269 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
270 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
272 Inst.addOperand(MCOperand::CreateExpr(Expr));
275 void addMEMrrOperands(MCInst &Inst, unsigned N) const {
276 assert(N == 2 && "Invalid number of operands!");
278 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
280 assert(getMemOffsetReg() != 0 && "Invalid offset");
281 Inst.addOperand(MCOperand::CreateReg(getMemOffsetReg()));
284 void addMEMriOperands(MCInst &Inst, unsigned N) const {
285 assert(N == 2 && "Invalid number of operands!");
287 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
289 const MCExpr *Expr = getMemOff();
293 static SparcOperand *CreateToken(StringRef Str, SMLoc S) {
294 SparcOperand *Op = new SparcOperand(k_Token);
295 Op->Tok.Data = Str.data();
296 Op->Tok.Length = Str.size();
302 static SparcOperand *CreateReg(unsigned RegNum,
305 SparcOperand *Op = new SparcOperand(k_Register);
306 Op->Reg.RegNum = RegNum;
307 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind;
313 static SparcOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
314 SparcOperand *Op = new SparcOperand(k_Immediate);
321 static SparcOperand *MorphToDoubleReg(SparcOperand *Op) {
322 unsigned Reg = Op->getReg();
323 assert(Op->Reg.Kind == rk_FloatReg);
324 unsigned regIdx = Reg - Sparc::F0;
325 if (regIdx % 2 || regIdx > 31)
327 Op->Reg.RegNum = DoubleRegs[regIdx / 2];
328 Op->Reg.Kind = rk_DoubleReg;
332 static SparcOperand *MorphToQuadReg(SparcOperand *Op) {
333 unsigned Reg = Op->getReg();
335 switch (Op->Reg.Kind) {
336 default: assert(0 && "Unexpected register kind!");
338 regIdx = Reg - Sparc::F0;
339 if (regIdx % 4 || regIdx > 31)
341 Reg = QuadFPRegs[regIdx / 4];
344 regIdx = Reg - Sparc::D0;
345 if (regIdx % 2 || regIdx > 31)
347 Reg = QuadFPRegs[regIdx / 2];
350 Op->Reg.RegNum = Reg;
351 Op->Reg.Kind = rk_QuadReg;
355 static SparcOperand *MorphToMEMrr(unsigned Base, SparcOperand *Op) {
356 unsigned offsetReg = Op->getReg();
357 Op->Kind = k_MemoryReg;
359 Op->Mem.OffsetReg = offsetReg;
364 static SparcOperand *CreateMEMri(unsigned Base,
367 SparcOperand *Op = new SparcOperand(k_MemoryImm);
369 Op->Mem.OffsetReg = 0;
376 static SparcOperand *MorphToMEMri(unsigned Base, SparcOperand *Op) {
377 const MCExpr *Imm = Op->getImm();
378 Op->Kind = k_MemoryImm;
380 Op->Mem.OffsetReg = 0;
388 bool SparcAsmParser::
389 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
390 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
391 MCStreamer &Out, unsigned &ErrorInfo,
392 bool MatchingInlineAsm) {
394 SmallVector<MCInst, 8> Instructions;
395 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
397 switch (MatchResult) {
401 case Match_Success: {
403 Out.EmitInstruction(Inst, STI);
407 case Match_MissingFeature:
409 "instruction requires a CPU feature not currently enabled");
411 case Match_InvalidOperand: {
412 SMLoc ErrorLoc = IDLoc;
413 if (ErrorInfo != ~0U) {
414 if (ErrorInfo >= Operands.size())
415 return Error(IDLoc, "too few operands for instruction");
417 ErrorLoc = ((SparcOperand*) Operands[ErrorInfo])->getStartLoc();
418 if (ErrorLoc == SMLoc())
422 return Error(ErrorLoc, "invalid operand for instruction");
424 case Match_MnemonicFail:
425 return Error(IDLoc, "invalid instruction mnemonic");
430 bool SparcAsmParser::
431 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)
433 const AsmToken &Tok = Parser.getTok();
434 StartLoc = Tok.getLoc();
435 EndLoc = Tok.getEndLoc();
437 if (getLexer().getKind() != AsmToken::Percent)
440 unsigned regKind = SparcOperand::rk_None;
441 if (matchRegisterName(Tok, RegNo, regKind)) {
446 return Error(StartLoc, "invalid register name");
449 bool SparcAsmParser::
450 ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
452 SmallVectorImpl<MCParsedAsmOperand*> &Operands)
455 // First operand in MCInst is instruction mnemonic.
456 Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
458 if (getLexer().isNot(AsmToken::EndOfStatement)) {
459 // Read the first operand.
460 if (getLexer().is(AsmToken::Comma)) {
461 if (parseBranchModifiers(Operands) != MatchOperand_Success) {
462 SMLoc Loc = getLexer().getLoc();
463 Parser.eatToEndOfStatement();
464 return Error(Loc, "unexpected token");
467 if (parseOperand(Operands, Name) != MatchOperand_Success) {
468 SMLoc Loc = getLexer().getLoc();
469 Parser.eatToEndOfStatement();
470 return Error(Loc, "unexpected token");
473 while (getLexer().is(AsmToken::Comma)) {
474 Parser.Lex(); // Eat the comma.
475 // Parse and remember the operand.
476 if (parseOperand(Operands, Name) != MatchOperand_Success) {
477 SMLoc Loc = getLexer().getLoc();
478 Parser.eatToEndOfStatement();
479 return Error(Loc, "unexpected token");
483 if (getLexer().isNot(AsmToken::EndOfStatement)) {
484 SMLoc Loc = getLexer().getLoc();
485 Parser.eatToEndOfStatement();
486 return Error(Loc, "unexpected token");
488 Parser.Lex(); // Consume the EndOfStatement.
492 bool SparcAsmParser::
493 ParseDirective(AsmToken DirectiveID)
495 StringRef IDVal = DirectiveID.getString();
497 if (IDVal == ".byte")
498 return parseDirectiveWord(1, DirectiveID.getLoc());
500 if (IDVal == ".half")
501 return parseDirectiveWord(2, DirectiveID.getLoc());
503 if (IDVal == ".word")
504 return parseDirectiveWord(4, DirectiveID.getLoc());
506 if (IDVal == ".nword")
507 return parseDirectiveWord(is64Bit() ? 8 : 4, DirectiveID.getLoc());
509 if (is64Bit() && IDVal == ".xword")
510 return parseDirectiveWord(8, DirectiveID.getLoc());
512 if (IDVal == ".register") {
513 // For now, ignore .register directive.
514 Parser.eatToEndOfStatement();
518 // Let the MC layer to handle other directives.
522 bool SparcAsmParser:: parseDirectiveWord(unsigned Size, SMLoc L) {
523 if (getLexer().isNot(AsmToken::EndOfStatement)) {
526 if (getParser().parseExpression(Value))
529 getParser().getStreamer().EmitValue(Value, Size);
531 if (getLexer().is(AsmToken::EndOfStatement))
534 // FIXME: Improve diagnostic.
535 if (getLexer().isNot(AsmToken::Comma))
536 return Error(L, "unexpected token in directive");
544 SparcAsmParser::OperandMatchResultTy SparcAsmParser::
545 parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands)
549 unsigned BaseReg = 0;
551 if (ParseRegister(BaseReg, S, E)) {
552 return MatchOperand_NoMatch;
555 switch (getLexer().getKind()) {
556 default: return MatchOperand_NoMatch;
558 case AsmToken::Comma:
559 case AsmToken::RBrac:
560 case AsmToken::EndOfStatement:
561 Operands.push_back(SparcOperand::CreateMEMri(BaseReg, 0, S, E));
562 return MatchOperand_Success;
564 case AsmToken:: Plus:
565 Parser.Lex(); // Eat the '+'
567 case AsmToken::Minus:
571 SparcOperand *Offset = 0;
572 OperandMatchResultTy ResTy = parseSparcAsmOperand(Offset);
573 if (ResTy != MatchOperand_Success || !Offset)
574 return MatchOperand_NoMatch;
576 Offset = (Offset->isImm()
577 ? SparcOperand::MorphToMEMri(BaseReg, Offset)
578 : SparcOperand::MorphToMEMrr(BaseReg, Offset));
580 Operands.push_back(Offset);
581 return MatchOperand_Success;
584 SparcAsmParser::OperandMatchResultTy SparcAsmParser::
585 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
589 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
591 // If there wasn't a custom match, try the generic matcher below. Otherwise,
592 // there was a match, but an error occurred, in which case, just return that
593 // the operand parsing failed.
594 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
597 if (getLexer().is(AsmToken::LBrac)) {
599 Operands.push_back(SparcOperand::CreateToken("[",
600 Parser.getTok().getLoc()));
601 Parser.Lex(); // Eat the [
603 if (Mnemonic == "cas" || Mnemonic == "casx") {
604 SMLoc S = Parser.getTok().getLoc();
605 if (getLexer().getKind() != AsmToken::Percent)
606 return MatchOperand_NoMatch;
607 Parser.Lex(); // eat %
609 unsigned RegNo, RegKind;
610 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
611 return MatchOperand_NoMatch;
613 Parser.Lex(); // Eat the identifier token.
614 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
615 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
616 ResTy = MatchOperand_Success;
618 ResTy = parseMEMOperand(Operands);
621 if (ResTy != MatchOperand_Success)
624 if (!getLexer().is(AsmToken::RBrac))
625 return MatchOperand_ParseFail;
627 Operands.push_back(SparcOperand::CreateToken("]",
628 Parser.getTok().getLoc()));
629 Parser.Lex(); // Eat the ]
630 return MatchOperand_Success;
633 SparcOperand *Op = 0;
634 ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
635 if (ResTy != MatchOperand_Success || !Op)
636 return MatchOperand_ParseFail;
638 // Push the parsed operand into the list of operands
639 Operands.push_back(Op);
641 return MatchOperand_Success;
644 SparcAsmParser::OperandMatchResultTy
645 SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op, bool isCall)
648 SMLoc S = Parser.getTok().getLoc();
649 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
653 switch (getLexer().getKind()) {
656 case AsmToken::Percent:
657 Parser.Lex(); // Eat the '%'.
660 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
661 StringRef name = Parser.getTok().getString();
662 Parser.Lex(); // Eat the identifier token.
663 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
666 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
669 Op = SparcOperand::CreateToken("%y", S);
674 Op = SparcOperand::CreateToken("%xcc", S);
676 Op = SparcOperand::CreateToken("%icc", S);
680 assert(name == "fcc0" && "Cannot handle %fcc other than %fcc0 yet");
681 Op = SparcOperand::CreateToken("%fcc0", S);
686 if (matchSparcAsmModifiers(EVal, E)) {
687 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
688 Op = SparcOperand::CreateImm(EVal, S, E);
692 case AsmToken::Minus:
693 case AsmToken::Integer:
694 if (!getParser().parseExpression(EVal, E))
695 Op = SparcOperand::CreateImm(EVal, S, E);
698 case AsmToken::Identifier: {
699 StringRef Identifier;
700 if (!getParser().parseIdentifier(Identifier)) {
701 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
702 MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
704 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
707 getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_)
708 Res = SparcMCExpr::Create(SparcMCExpr::VK_Sparc_WPLT30, Res,
710 Op = SparcOperand::CreateImm(Res, S, E);
715 return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
718 SparcAsmParser::OperandMatchResultTy SparcAsmParser::
719 parseBranchModifiers(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
721 // parse (,a|,pn|,pt)+
723 while (getLexer().is(AsmToken::Comma)) {
725 Parser.Lex(); // Eat the comma
727 if (!getLexer().is(AsmToken::Identifier))
728 return MatchOperand_ParseFail;
729 StringRef modName = Parser.getTok().getString();
730 if (modName == "a" || modName == "pn" || modName == "pt") {
731 Operands.push_back(SparcOperand::CreateToken(modName,
732 Parser.getTok().getLoc()));
733 Parser.Lex(); // eat the identifier.
736 return MatchOperand_Success;
739 bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
745 RegKind = SparcOperand::rk_None;
746 if (Tok.is(AsmToken::Identifier)) {
747 StringRef name = Tok.getString();
750 if (name.equals("fp")) {
752 RegKind = SparcOperand::rk_IntReg;
756 if (name.equals("sp")) {
758 RegKind = SparcOperand::rk_IntReg;
762 if (name.equals("y")) {
764 RegKind = SparcOperand::rk_Y;
768 if (name.equals("icc")) {
770 RegKind = SparcOperand::rk_CCReg;
774 if (name.equals("xcc")) {
775 // FIXME:: check 64bit.
777 RegKind = SparcOperand::rk_CCReg;
782 if (name.substr(0, 3).equals_lower("fcc")
783 && !name.substr(3).getAsInteger(10, intVal)
785 // FIXME: check 64bit and handle %fcc1 - %fcc3
787 RegKind = SparcOperand::rk_CCReg;
792 if (name.substr(0, 1).equals_lower("g")
793 && !name.substr(1).getAsInteger(10, intVal)
795 RegNo = IntRegs[intVal];
796 RegKind = SparcOperand::rk_IntReg;
800 if (name.substr(0, 1).equals_lower("o")
801 && !name.substr(1).getAsInteger(10, intVal)
803 RegNo = IntRegs[8 + intVal];
804 RegKind = SparcOperand::rk_IntReg;
807 if (name.substr(0, 1).equals_lower("l")
808 && !name.substr(1).getAsInteger(10, intVal)
810 RegNo = IntRegs[16 + intVal];
811 RegKind = SparcOperand::rk_IntReg;
814 if (name.substr(0, 1).equals_lower("i")
815 && !name.substr(1).getAsInteger(10, intVal)
817 RegNo = IntRegs[24 + intVal];
818 RegKind = SparcOperand::rk_IntReg;
822 if (name.substr(0, 1).equals_lower("f")
823 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
824 RegNo = FloatRegs[intVal];
825 RegKind = SparcOperand::rk_FloatReg;
829 if (name.substr(0, 1).equals_lower("f")
830 && !name.substr(1, 2).getAsInteger(10, intVal)
831 && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) {
833 RegNo = DoubleRegs[intVal/2];
834 RegKind = SparcOperand::rk_DoubleReg;
839 if (name.substr(0, 1).equals_lower("r")
840 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
841 RegNo = IntRegs[intVal];
842 RegKind = SparcOperand::rk_IntReg;
849 static bool hasGOTReference(const MCExpr *Expr) {
850 switch (Expr->getKind()) {
852 if (const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
853 return hasGOTReference(SE->getSubExpr());
856 case MCExpr::Constant:
859 case MCExpr::Binary: {
860 const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
861 return hasGOTReference(BE->getLHS()) || hasGOTReference(BE->getRHS());
864 case MCExpr::SymbolRef: {
865 const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);
866 return (SymRef.getSymbol().getName() == "_GLOBAL_OFFSET_TABLE_");
870 return hasGOTReference(cast<MCUnaryExpr>(Expr)->getSubExpr());
875 bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
878 AsmToken Tok = Parser.getTok();
879 if (!Tok.is(AsmToken::Identifier))
882 StringRef name = Tok.getString();
884 SparcMCExpr::VariantKind VK = SparcMCExpr::parseVariantKind(name);
886 if (VK == SparcMCExpr::VK_Sparc_None)
889 Parser.Lex(); // Eat the identifier.
890 if (Parser.getTok().getKind() != AsmToken::LParen)
893 Parser.Lex(); // Eat the LParen token.
894 const MCExpr *subExpr;
895 if (Parser.parseParenExpression(subExpr, EndLoc))
898 bool isPIC = getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_;
902 case SparcMCExpr::VK_Sparc_LO:
903 VK = (hasGOTReference(subExpr)
904 ? SparcMCExpr::VK_Sparc_PC10
905 : (isPIC ? SparcMCExpr::VK_Sparc_GOT10 : VK));
907 case SparcMCExpr::VK_Sparc_HI:
908 VK = (hasGOTReference(subExpr)
909 ? SparcMCExpr::VK_Sparc_PC22
910 : (isPIC ? SparcMCExpr::VK_Sparc_GOT22 : VK));
914 EVal = SparcMCExpr::Create(VK, subExpr, getContext());
919 extern "C" void LLVMInitializeSparcAsmParser() {
920 RegisterMCAsmParser<SparcAsmParser> A(TheSparcTarget);
921 RegisterMCAsmParser<SparcAsmParser> B(TheSparcV9Target);
924 #define GET_REGISTER_MATCHER
925 #define GET_MATCHER_IMPLEMENTATION
926 #include "SparcGenAsmMatcher.inc"
930 unsigned SparcAsmParser::
931 validateTargetOperandClass(MCParsedAsmOperand *GOp,
934 SparcOperand *Op = (SparcOperand*)GOp;
935 if (Op->isFloatOrDoubleReg()) {
939 if (!Op->isFloatReg() || SparcOperand::MorphToDoubleReg(Op))
940 return MCTargetAsmParser::Match_Success;
943 if (SparcOperand::MorphToQuadReg(Op))
944 return MCTargetAsmParser::Match_Success;
948 return Match_InvalidOperand;