1 //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SparcMCTargetDesc.h"
11 #include "MCTargetDesc/SparcMCExpr.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCObjectFileInfo.h"
16 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/MC/MCSymbol.h"
20 #include "llvm/MC/MCTargetAsmParser.h"
21 #include "llvm/Support/TargetRegistry.h"
25 // The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target
26 // namespace. But SPARC backend uses "SP" as its namespace.
35 class SparcAsmParser : public MCTargetAsmParser {
40 /// @name Auto-generated Match Functions
43 #define GET_ASSEMBLER_HEADER
44 #include "SparcGenAsmMatcher.inc"
48 // public interface of the MCTargetAsmParser.
49 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
50 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
51 MCStreamer &Out, unsigned &ErrorInfo,
52 bool MatchingInlineAsm);
53 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
54 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
56 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
57 bool ParseDirective(AsmToken DirectiveID);
59 virtual unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
62 // Custom parse functions for Sparc specific operands.
64 parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
67 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
71 parseSparcAsmOperand(SparcOperand *&Operand, bool isCall = false);
74 parseBranchModifiers(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
76 // returns true if Tok is matched to a register and returns register in RegNo.
77 bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
80 bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
81 bool parseDirectiveWord(unsigned Size, SMLoc L);
83 bool is64Bit() const { return STI.getTargetTriple().startswith("sparcv9"); }
85 SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
86 const MCInstrInfo &MII,
87 const MCTargetOptions &Options)
88 : MCTargetAsmParser(), STI(sti), Parser(parser) {
89 // Initialize the set of available features.
90 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
95 static unsigned IntRegs[32] = {
96 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
97 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
98 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
99 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
100 Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
101 Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
102 Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
103 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
105 static unsigned FloatRegs[32] = {
106 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
107 Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
108 Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
109 Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
110 Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
111 Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
112 Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
113 Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
115 static unsigned DoubleRegs[32] = {
116 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
117 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
118 Sparc::D8, Sparc::D7, Sparc::D8, Sparc::D9,
119 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
120 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
121 Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
122 Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
123 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
125 static unsigned QuadFPRegs[32] = {
126 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
127 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
128 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
129 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
132 /// SparcOperand - Instances of this class represent a parsed Sparc machine
134 class SparcOperand : public MCParsedAsmOperand {
154 SMLoc StartLoc, EndLoc;
156 SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
185 bool isToken() const { return Kind == k_Token; }
186 bool isReg() const { return Kind == k_Register; }
187 bool isImm() const { return Kind == k_Immediate; }
188 bool isMem() const { return isMEMrr() || isMEMri(); }
189 bool isMEMrr() const { return Kind == k_MemoryReg; }
190 bool isMEMri() const { return Kind == k_MemoryImm; }
192 bool isFloatReg() const {
193 return (Kind == k_Register && Reg.Kind == rk_FloatReg);
196 bool isFloatOrDoubleReg() const {
197 return (Kind == k_Register && (Reg.Kind == rk_FloatReg
198 || Reg.Kind == rk_DoubleReg));
202 StringRef getToken() const {
203 assert(Kind == k_Token && "Invalid access!");
204 return StringRef(Tok.Data, Tok.Length);
207 unsigned getReg() const {
208 assert((Kind == k_Register) && "Invalid access!");
212 const MCExpr *getImm() const {
213 assert((Kind == k_Immediate) && "Invalid access!");
217 unsigned getMemBase() const {
218 assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!");
222 unsigned getMemOffsetReg() const {
223 assert((Kind == k_MemoryReg) && "Invalid access!");
224 return Mem.OffsetReg;
227 const MCExpr *getMemOff() const {
228 assert((Kind == k_MemoryImm) && "Invalid access!");
232 /// getStartLoc - Get the location of the first token of this operand.
233 SMLoc getStartLoc() const {
236 /// getEndLoc - Get the location of the last token of this operand.
237 SMLoc getEndLoc() const {
241 virtual void print(raw_ostream &OS) const {
243 case k_Token: OS << "Token: " << getToken() << "\n"; break;
244 case k_Register: OS << "Reg: #" << getReg() << "\n"; break;
245 case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
246 case k_MemoryReg: OS << "Mem: " << getMemBase() << "+"
247 << getMemOffsetReg() << "\n"; break;
248 case k_MemoryImm: assert(getMemOff() != 0);
249 OS << "Mem: " << getMemBase()
250 << "+" << *getMemOff()
255 void addRegOperands(MCInst &Inst, unsigned N) const {
256 assert(N == 1 && "Invalid number of operands!");
257 Inst.addOperand(MCOperand::CreateReg(getReg()));
260 void addImmOperands(MCInst &Inst, unsigned N) const {
261 assert(N == 1 && "Invalid number of operands!");
262 const MCExpr *Expr = getImm();
266 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
267 // Add as immediate when possible. Null MCExpr = 0.
269 Inst.addOperand(MCOperand::CreateImm(0));
270 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
271 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
273 Inst.addOperand(MCOperand::CreateExpr(Expr));
276 void addMEMrrOperands(MCInst &Inst, unsigned N) const {
277 assert(N == 2 && "Invalid number of operands!");
279 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
281 assert(getMemOffsetReg() != 0 && "Invalid offset");
282 Inst.addOperand(MCOperand::CreateReg(getMemOffsetReg()));
285 void addMEMriOperands(MCInst &Inst, unsigned N) const {
286 assert(N == 2 && "Invalid number of operands!");
288 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
290 const MCExpr *Expr = getMemOff();
294 static SparcOperand *CreateToken(StringRef Str, SMLoc S) {
295 SparcOperand *Op = new SparcOperand(k_Token);
296 Op->Tok.Data = Str.data();
297 Op->Tok.Length = Str.size();
303 static SparcOperand *CreateReg(unsigned RegNum,
306 SparcOperand *Op = new SparcOperand(k_Register);
307 Op->Reg.RegNum = RegNum;
308 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind;
314 static SparcOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
315 SparcOperand *Op = new SparcOperand(k_Immediate);
322 static SparcOperand *MorphToDoubleReg(SparcOperand *Op) {
323 unsigned Reg = Op->getReg();
324 assert(Op->Reg.Kind == rk_FloatReg);
325 unsigned regIdx = Reg - Sparc::F0;
326 if (regIdx % 2 || regIdx > 31)
328 Op->Reg.RegNum = DoubleRegs[regIdx / 2];
329 Op->Reg.Kind = rk_DoubleReg;
333 static SparcOperand *MorphToQuadReg(SparcOperand *Op) {
334 unsigned Reg = Op->getReg();
336 switch (Op->Reg.Kind) {
337 default: assert(0 && "Unexpected register kind!");
339 regIdx = Reg - Sparc::F0;
340 if (regIdx % 4 || regIdx > 31)
342 Reg = QuadFPRegs[regIdx / 4];
345 regIdx = Reg - Sparc::D0;
346 if (regIdx % 2 || regIdx > 31)
348 Reg = QuadFPRegs[regIdx / 2];
351 Op->Reg.RegNum = Reg;
352 Op->Reg.Kind = rk_QuadReg;
356 static SparcOperand *MorphToMEMrr(unsigned Base, SparcOperand *Op) {
357 unsigned offsetReg = Op->getReg();
358 Op->Kind = k_MemoryReg;
360 Op->Mem.OffsetReg = offsetReg;
361 Op->Mem.Off = nullptr;
365 static SparcOperand *CreateMEMri(unsigned Base,
368 SparcOperand *Op = new SparcOperand(k_MemoryImm);
370 Op->Mem.OffsetReg = 0;
377 static SparcOperand *MorphToMEMri(unsigned Base, SparcOperand *Op) {
378 const MCExpr *Imm = Op->getImm();
379 Op->Kind = k_MemoryImm;
381 Op->Mem.OffsetReg = 0;
389 bool SparcAsmParser::
390 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
391 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
392 MCStreamer &Out, unsigned &ErrorInfo,
393 bool MatchingInlineAsm) {
395 SmallVector<MCInst, 8> Instructions;
396 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
398 switch (MatchResult) {
402 case Match_Success: {
404 Out.EmitInstruction(Inst, STI);
408 case Match_MissingFeature:
410 "instruction requires a CPU feature not currently enabled");
412 case Match_InvalidOperand: {
413 SMLoc ErrorLoc = IDLoc;
414 if (ErrorInfo != ~0U) {
415 if (ErrorInfo >= Operands.size())
416 return Error(IDLoc, "too few operands for instruction");
418 ErrorLoc = ((SparcOperand*) Operands[ErrorInfo])->getStartLoc();
419 if (ErrorLoc == SMLoc())
423 return Error(ErrorLoc, "invalid operand for instruction");
425 case Match_MnemonicFail:
426 return Error(IDLoc, "invalid instruction mnemonic");
431 bool SparcAsmParser::
432 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)
434 const AsmToken &Tok = Parser.getTok();
435 StartLoc = Tok.getLoc();
436 EndLoc = Tok.getEndLoc();
438 if (getLexer().getKind() != AsmToken::Percent)
441 unsigned regKind = SparcOperand::rk_None;
442 if (matchRegisterName(Tok, RegNo, regKind)) {
447 return Error(StartLoc, "invalid register name");
450 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
453 bool SparcAsmParser::
454 ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
456 SmallVectorImpl<MCParsedAsmOperand*> &Operands)
459 // First operand in MCInst is instruction mnemonic.
460 Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
462 // apply mnemonic aliases, if any, so that we can parse operands correctly.
463 applyMnemonicAliases(Name, getAvailableFeatures(), 0);
465 if (getLexer().isNot(AsmToken::EndOfStatement)) {
466 // Read the first operand.
467 if (getLexer().is(AsmToken::Comma)) {
468 if (parseBranchModifiers(Operands) != MatchOperand_Success) {
469 SMLoc Loc = getLexer().getLoc();
470 Parser.eatToEndOfStatement();
471 return Error(Loc, "unexpected token");
474 if (parseOperand(Operands, Name) != MatchOperand_Success) {
475 SMLoc Loc = getLexer().getLoc();
476 Parser.eatToEndOfStatement();
477 return Error(Loc, "unexpected token");
480 while (getLexer().is(AsmToken::Comma)) {
481 Parser.Lex(); // Eat the comma.
482 // Parse and remember the operand.
483 if (parseOperand(Operands, Name) != MatchOperand_Success) {
484 SMLoc Loc = getLexer().getLoc();
485 Parser.eatToEndOfStatement();
486 return Error(Loc, "unexpected token");
490 if (getLexer().isNot(AsmToken::EndOfStatement)) {
491 SMLoc Loc = getLexer().getLoc();
492 Parser.eatToEndOfStatement();
493 return Error(Loc, "unexpected token");
495 Parser.Lex(); // Consume the EndOfStatement.
499 bool SparcAsmParser::
500 ParseDirective(AsmToken DirectiveID)
502 StringRef IDVal = DirectiveID.getString();
504 if (IDVal == ".byte")
505 return parseDirectiveWord(1, DirectiveID.getLoc());
507 if (IDVal == ".half")
508 return parseDirectiveWord(2, DirectiveID.getLoc());
510 if (IDVal == ".word")
511 return parseDirectiveWord(4, DirectiveID.getLoc());
513 if (IDVal == ".nword")
514 return parseDirectiveWord(is64Bit() ? 8 : 4, DirectiveID.getLoc());
516 if (is64Bit() && IDVal == ".xword")
517 return parseDirectiveWord(8, DirectiveID.getLoc());
519 if (IDVal == ".register") {
520 // For now, ignore .register directive.
521 Parser.eatToEndOfStatement();
525 // Let the MC layer to handle other directives.
529 bool SparcAsmParser:: parseDirectiveWord(unsigned Size, SMLoc L) {
530 if (getLexer().isNot(AsmToken::EndOfStatement)) {
533 if (getParser().parseExpression(Value))
536 getParser().getStreamer().EmitValue(Value, Size);
538 if (getLexer().is(AsmToken::EndOfStatement))
541 // FIXME: Improve diagnostic.
542 if (getLexer().isNot(AsmToken::Comma))
543 return Error(L, "unexpected token in directive");
551 SparcAsmParser::OperandMatchResultTy SparcAsmParser::
552 parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands)
556 unsigned BaseReg = 0;
558 if (ParseRegister(BaseReg, S, E)) {
559 return MatchOperand_NoMatch;
562 switch (getLexer().getKind()) {
563 default: return MatchOperand_NoMatch;
565 case AsmToken::Comma:
566 case AsmToken::RBrac:
567 case AsmToken::EndOfStatement:
568 Operands.push_back(SparcOperand::CreateMEMri(BaseReg, nullptr, S, E));
569 return MatchOperand_Success;
571 case AsmToken:: Plus:
572 Parser.Lex(); // Eat the '+'
574 case AsmToken::Minus:
578 SparcOperand *Offset = nullptr;
579 OperandMatchResultTy ResTy = parseSparcAsmOperand(Offset);
580 if (ResTy != MatchOperand_Success || !Offset)
581 return MatchOperand_NoMatch;
583 Offset = (Offset->isImm()
584 ? SparcOperand::MorphToMEMri(BaseReg, Offset)
585 : SparcOperand::MorphToMEMrr(BaseReg, Offset));
587 Operands.push_back(Offset);
588 return MatchOperand_Success;
591 SparcAsmParser::OperandMatchResultTy SparcAsmParser::
592 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
596 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
598 // If there wasn't a custom match, try the generic matcher below. Otherwise,
599 // there was a match, but an error occurred, in which case, just return that
600 // the operand parsing failed.
601 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
604 if (getLexer().is(AsmToken::LBrac)) {
606 Operands.push_back(SparcOperand::CreateToken("[",
607 Parser.getTok().getLoc()));
608 Parser.Lex(); // Eat the [
610 if (Mnemonic == "cas" || Mnemonic == "casx") {
611 SMLoc S = Parser.getTok().getLoc();
612 if (getLexer().getKind() != AsmToken::Percent)
613 return MatchOperand_NoMatch;
614 Parser.Lex(); // eat %
616 unsigned RegNo, RegKind;
617 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
618 return MatchOperand_NoMatch;
620 Parser.Lex(); // Eat the identifier token.
621 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
622 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
623 ResTy = MatchOperand_Success;
625 ResTy = parseMEMOperand(Operands);
628 if (ResTy != MatchOperand_Success)
631 if (!getLexer().is(AsmToken::RBrac))
632 return MatchOperand_ParseFail;
634 Operands.push_back(SparcOperand::CreateToken("]",
635 Parser.getTok().getLoc()));
636 Parser.Lex(); // Eat the ]
637 return MatchOperand_Success;
640 SparcOperand *Op = nullptr;
642 ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
643 if (ResTy != MatchOperand_Success || !Op)
644 return MatchOperand_ParseFail;
646 // Push the parsed operand into the list of operands
647 Operands.push_back(Op);
649 return MatchOperand_Success;
652 SparcAsmParser::OperandMatchResultTy
653 SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op, bool isCall)
656 SMLoc S = Parser.getTok().getLoc();
657 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
661 switch (getLexer().getKind()) {
664 case AsmToken::Percent:
665 Parser.Lex(); // Eat the '%'.
668 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
669 StringRef name = Parser.getTok().getString();
670 Parser.Lex(); // Eat the identifier token.
671 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
674 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
677 Op = SparcOperand::CreateToken("%y", S);
682 Op = SparcOperand::CreateToken("%xcc", S);
684 Op = SparcOperand::CreateToken("%icc", S);
689 if (matchSparcAsmModifiers(EVal, E)) {
690 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
691 Op = SparcOperand::CreateImm(EVal, S, E);
695 case AsmToken::Minus:
696 case AsmToken::Integer:
697 if (!getParser().parseExpression(EVal, E))
698 Op = SparcOperand::CreateImm(EVal, S, E);
701 case AsmToken::Identifier: {
702 StringRef Identifier;
703 if (!getParser().parseIdentifier(Identifier)) {
704 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
705 MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
707 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
710 getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_)
711 Res = SparcMCExpr::Create(SparcMCExpr::VK_Sparc_WPLT30, Res,
713 Op = SparcOperand::CreateImm(Res, S, E);
718 return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
721 SparcAsmParser::OperandMatchResultTy SparcAsmParser::
722 parseBranchModifiers(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
724 // parse (,a|,pn|,pt)+
726 while (getLexer().is(AsmToken::Comma)) {
728 Parser.Lex(); // Eat the comma
730 if (!getLexer().is(AsmToken::Identifier))
731 return MatchOperand_ParseFail;
732 StringRef modName = Parser.getTok().getString();
733 if (modName == "a" || modName == "pn" || modName == "pt") {
734 Operands.push_back(SparcOperand::CreateToken(modName,
735 Parser.getTok().getLoc()));
736 Parser.Lex(); // eat the identifier.
739 return MatchOperand_Success;
742 bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
748 RegKind = SparcOperand::rk_None;
749 if (Tok.is(AsmToken::Identifier)) {
750 StringRef name = Tok.getString();
753 if (name.equals("fp")) {
755 RegKind = SparcOperand::rk_IntReg;
759 if (name.equals("sp")) {
761 RegKind = SparcOperand::rk_IntReg;
765 if (name.equals("y")) {
767 RegKind = SparcOperand::rk_Y;
771 if (name.equals("icc")) {
773 RegKind = SparcOperand::rk_CCReg;
777 if (name.equals("xcc")) {
778 // FIXME:: check 64bit.
780 RegKind = SparcOperand::rk_CCReg;
785 if (name.substr(0, 3).equals_lower("fcc")
786 && !name.substr(3).getAsInteger(10, intVal)
788 // FIXME: check 64bit and handle %fcc1 - %fcc3
789 RegNo = Sparc::FCC0 + intVal;
790 RegKind = SparcOperand::rk_CCReg;
795 if (name.substr(0, 1).equals_lower("g")
796 && !name.substr(1).getAsInteger(10, intVal)
798 RegNo = IntRegs[intVal];
799 RegKind = SparcOperand::rk_IntReg;
803 if (name.substr(0, 1).equals_lower("o")
804 && !name.substr(1).getAsInteger(10, intVal)
806 RegNo = IntRegs[8 + intVal];
807 RegKind = SparcOperand::rk_IntReg;
810 if (name.substr(0, 1).equals_lower("l")
811 && !name.substr(1).getAsInteger(10, intVal)
813 RegNo = IntRegs[16 + intVal];
814 RegKind = SparcOperand::rk_IntReg;
817 if (name.substr(0, 1).equals_lower("i")
818 && !name.substr(1).getAsInteger(10, intVal)
820 RegNo = IntRegs[24 + intVal];
821 RegKind = SparcOperand::rk_IntReg;
825 if (name.substr(0, 1).equals_lower("f")
826 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
827 RegNo = FloatRegs[intVal];
828 RegKind = SparcOperand::rk_FloatReg;
832 if (name.substr(0, 1).equals_lower("f")
833 && !name.substr(1, 2).getAsInteger(10, intVal)
834 && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) {
836 RegNo = DoubleRegs[intVal/2];
837 RegKind = SparcOperand::rk_DoubleReg;
842 if (name.substr(0, 1).equals_lower("r")
843 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
844 RegNo = IntRegs[intVal];
845 RegKind = SparcOperand::rk_IntReg;
852 static bool hasGOTReference(const MCExpr *Expr) {
853 switch (Expr->getKind()) {
855 if (const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
856 return hasGOTReference(SE->getSubExpr());
859 case MCExpr::Constant:
862 case MCExpr::Binary: {
863 const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
864 return hasGOTReference(BE->getLHS()) || hasGOTReference(BE->getRHS());
867 case MCExpr::SymbolRef: {
868 const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);
869 return (SymRef.getSymbol().getName() == "_GLOBAL_OFFSET_TABLE_");
873 return hasGOTReference(cast<MCUnaryExpr>(Expr)->getSubExpr());
878 bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
881 AsmToken Tok = Parser.getTok();
882 if (!Tok.is(AsmToken::Identifier))
885 StringRef name = Tok.getString();
887 SparcMCExpr::VariantKind VK = SparcMCExpr::parseVariantKind(name);
889 if (VK == SparcMCExpr::VK_Sparc_None)
892 Parser.Lex(); // Eat the identifier.
893 if (Parser.getTok().getKind() != AsmToken::LParen)
896 Parser.Lex(); // Eat the LParen token.
897 const MCExpr *subExpr;
898 if (Parser.parseParenExpression(subExpr, EndLoc))
901 bool isPIC = getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_;
905 case SparcMCExpr::VK_Sparc_LO:
906 VK = (hasGOTReference(subExpr)
907 ? SparcMCExpr::VK_Sparc_PC10
908 : (isPIC ? SparcMCExpr::VK_Sparc_GOT10 : VK));
910 case SparcMCExpr::VK_Sparc_HI:
911 VK = (hasGOTReference(subExpr)
912 ? SparcMCExpr::VK_Sparc_PC22
913 : (isPIC ? SparcMCExpr::VK_Sparc_GOT22 : VK));
917 EVal = SparcMCExpr::Create(VK, subExpr, getContext());
922 extern "C" void LLVMInitializeSparcAsmParser() {
923 RegisterMCAsmParser<SparcAsmParser> A(TheSparcTarget);
924 RegisterMCAsmParser<SparcAsmParser> B(TheSparcV9Target);
927 #define GET_REGISTER_MATCHER
928 #define GET_MATCHER_IMPLEMENTATION
929 #include "SparcGenAsmMatcher.inc"
933 unsigned SparcAsmParser::
934 validateTargetOperandClass(MCParsedAsmOperand *GOp,
937 SparcOperand *Op = (SparcOperand*)GOp;
938 if (Op->isFloatOrDoubleReg()) {
942 if (!Op->isFloatReg() || SparcOperand::MorphToDoubleReg(Op))
943 return MCTargetAsmParser::Match_Success;
946 if (SparcOperand::MorphToQuadReg(Op))
947 return MCTargetAsmParser::Match_Success;
951 return Match_InvalidOperand;