1 //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SparcMCTargetDesc.h"
11 #include "MCTargetDesc/SparcMCExpr.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCObjectFileInfo.h"
16 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/MC/MCSymbol.h"
20 #include "llvm/MC/MCTargetAsmParser.h"
21 #include "llvm/Support/TargetRegistry.h"
25 // The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target
26 // namespace. But SPARC backend uses "SP" as its namespace.
35 class SparcAsmParser : public MCTargetAsmParser {
40 /// @name Auto-generated Match Functions
43 #define GET_ASSEMBLER_HEADER
44 #include "SparcGenAsmMatcher.inc"
48 // public interface of the MCTargetAsmParser.
49 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
50 OperandVector &Operands, MCStreamer &Out,
52 bool MatchingInlineAsm) override;
53 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
54 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
55 SMLoc NameLoc, OperandVector &Operands) override;
56 bool ParseDirective(AsmToken DirectiveID) override;
58 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
59 unsigned Kind) override;
61 // Custom parse functions for Sparc specific operands.
62 OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
64 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
67 parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Operand,
70 OperandMatchResultTy parseBranchModifiers(OperandVector &Operands);
72 // returns true if Tok is matched to a register and returns register in RegNo.
73 bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
76 bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
77 bool parseDirectiveWord(unsigned Size, SMLoc L);
79 bool is64Bit() const {
80 return STI.getTargetTriple().getArch() == Triple::sparcv9;
83 void expandSET(MCInst &Inst, SMLoc IDLoc,
84 SmallVectorImpl<MCInst> &Instructions);
87 SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
88 const MCInstrInfo &MII,
89 const MCTargetOptions &Options)
90 : MCTargetAsmParser(Options), STI(sti), Parser(parser) {
91 // Initialize the set of available features.
92 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
97 static unsigned IntRegs[32] = {
98 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
99 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
100 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
101 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
102 Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
103 Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
104 Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
105 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
107 static unsigned FloatRegs[32] = {
108 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
109 Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
110 Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
111 Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
112 Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
113 Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
114 Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
115 Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
117 static unsigned DoubleRegs[32] = {
118 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
119 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
120 Sparc::D8, Sparc::D7, Sparc::D8, Sparc::D9,
121 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
122 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
123 Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
124 Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
125 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
127 static unsigned QuadFPRegs[32] = {
128 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
129 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
130 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
131 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
133 static unsigned ASRRegs[32] = {
134 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
135 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
136 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
137 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
138 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
139 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
140 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
141 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
143 static unsigned IntPairRegs[] = {
144 Sparc::G0_G1, Sparc::G2_G3, Sparc::G4_G5, Sparc::G6_G7,
145 Sparc::O0_O1, Sparc::O2_O3, Sparc::O4_O5, Sparc::O6_O7,
146 Sparc::L0_L1, Sparc::L2_L3, Sparc::L4_L5, Sparc::L6_L7,
147 Sparc::I0_I1, Sparc::I2_I3, Sparc::I4_I5, Sparc::I6_I7};
149 /// SparcOperand - Instances of this class represent a parsed Sparc machine
151 class SparcOperand : public MCParsedAsmOperand {
172 SMLoc StartLoc, EndLoc;
201 SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
203 bool isToken() const override { return Kind == k_Token; }
204 bool isReg() const override { return Kind == k_Register; }
205 bool isImm() const override { return Kind == k_Immediate; }
206 bool isMem() const override { return isMEMrr() || isMEMri(); }
207 bool isMEMrr() const { return Kind == k_MemoryReg; }
208 bool isMEMri() const { return Kind == k_MemoryImm; }
210 bool isIntReg() const {
211 return (Kind == k_Register && Reg.Kind == rk_IntReg);
214 bool isFloatReg() const {
215 return (Kind == k_Register && Reg.Kind == rk_FloatReg);
218 bool isFloatOrDoubleReg() const {
219 return (Kind == k_Register && (Reg.Kind == rk_FloatReg
220 || Reg.Kind == rk_DoubleReg));
224 StringRef getToken() const {
225 assert(Kind == k_Token && "Invalid access!");
226 return StringRef(Tok.Data, Tok.Length);
229 unsigned getReg() const override {
230 assert((Kind == k_Register) && "Invalid access!");
234 const MCExpr *getImm() const {
235 assert((Kind == k_Immediate) && "Invalid access!");
239 unsigned getMemBase() const {
240 assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!");
244 unsigned getMemOffsetReg() const {
245 assert((Kind == k_MemoryReg) && "Invalid access!");
246 return Mem.OffsetReg;
249 const MCExpr *getMemOff() const {
250 assert((Kind == k_MemoryImm) && "Invalid access!");
254 /// getStartLoc - Get the location of the first token of this operand.
255 SMLoc getStartLoc() const override {
258 /// getEndLoc - Get the location of the last token of this operand.
259 SMLoc getEndLoc() const override {
263 void print(raw_ostream &OS) const override {
265 case k_Token: OS << "Token: " << getToken() << "\n"; break;
266 case k_Register: OS << "Reg: #" << getReg() << "\n"; break;
267 case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
268 case k_MemoryReg: OS << "Mem: " << getMemBase() << "+"
269 << getMemOffsetReg() << "\n"; break;
270 case k_MemoryImm: assert(getMemOff() != nullptr);
271 OS << "Mem: " << getMemBase()
272 << "+" << *getMemOff()
277 void addRegOperands(MCInst &Inst, unsigned N) const {
278 assert(N == 1 && "Invalid number of operands!");
279 Inst.addOperand(MCOperand::createReg(getReg()));
282 void addImmOperands(MCInst &Inst, unsigned N) const {
283 assert(N == 1 && "Invalid number of operands!");
284 const MCExpr *Expr = getImm();
288 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
289 // Add as immediate when possible. Null MCExpr = 0.
291 Inst.addOperand(MCOperand::createImm(0));
292 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
293 Inst.addOperand(MCOperand::createImm(CE->getValue()));
295 Inst.addOperand(MCOperand::createExpr(Expr));
298 void addMEMrrOperands(MCInst &Inst, unsigned N) const {
299 assert(N == 2 && "Invalid number of operands!");
301 Inst.addOperand(MCOperand::createReg(getMemBase()));
303 assert(getMemOffsetReg() != 0 && "Invalid offset");
304 Inst.addOperand(MCOperand::createReg(getMemOffsetReg()));
307 void addMEMriOperands(MCInst &Inst, unsigned N) const {
308 assert(N == 2 && "Invalid number of operands!");
310 Inst.addOperand(MCOperand::createReg(getMemBase()));
312 const MCExpr *Expr = getMemOff();
316 static std::unique_ptr<SparcOperand> CreateToken(StringRef Str, SMLoc S) {
317 auto Op = make_unique<SparcOperand>(k_Token);
318 Op->Tok.Data = Str.data();
319 Op->Tok.Length = Str.size();
325 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind,
327 auto Op = make_unique<SparcOperand>(k_Register);
328 Op->Reg.RegNum = RegNum;
329 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind;
335 static std::unique_ptr<SparcOperand> CreateImm(const MCExpr *Val, SMLoc S,
337 auto Op = make_unique<SparcOperand>(k_Immediate);
344 static bool MorphToIntPairReg(SparcOperand &Op) {
345 unsigned Reg = Op.getReg();
346 assert(Op.Reg.Kind == rk_IntReg);
347 unsigned regIdx = 32;
348 if (Reg >= Sparc::G0 && Reg <= Sparc::G7)
349 regIdx = Reg - Sparc::G0;
350 else if (Reg >= Sparc::O0 && Reg <= Sparc::O7)
351 regIdx = Reg - Sparc::O0 + 8;
352 else if (Reg >= Sparc::L0 && Reg <= Sparc::L7)
353 regIdx = Reg - Sparc::L0 + 16;
354 else if (Reg >= Sparc::I0 && Reg <= Sparc::I7)
355 regIdx = Reg - Sparc::I0 + 24;
356 if (regIdx % 2 || regIdx > 31)
358 Op.Reg.RegNum = IntPairRegs[regIdx / 2];
359 Op.Reg.Kind = rk_IntPairReg;
363 static bool MorphToDoubleReg(SparcOperand &Op) {
364 unsigned Reg = Op.getReg();
365 assert(Op.Reg.Kind == rk_FloatReg);
366 unsigned regIdx = Reg - Sparc::F0;
367 if (regIdx % 2 || regIdx > 31)
369 Op.Reg.RegNum = DoubleRegs[regIdx / 2];
370 Op.Reg.Kind = rk_DoubleReg;
374 static bool MorphToQuadReg(SparcOperand &Op) {
375 unsigned Reg = Op.getReg();
377 switch (Op.Reg.Kind) {
378 default: llvm_unreachable("Unexpected register kind!");
380 regIdx = Reg - Sparc::F0;
381 if (regIdx % 4 || regIdx > 31)
383 Reg = QuadFPRegs[regIdx / 4];
386 regIdx = Reg - Sparc::D0;
387 if (regIdx % 2 || regIdx > 31)
389 Reg = QuadFPRegs[regIdx / 2];
393 Op.Reg.Kind = rk_QuadReg;
397 static std::unique_ptr<SparcOperand>
398 MorphToMEMrr(unsigned Base, std::unique_ptr<SparcOperand> Op) {
399 unsigned offsetReg = Op->getReg();
400 Op->Kind = k_MemoryReg;
402 Op->Mem.OffsetReg = offsetReg;
403 Op->Mem.Off = nullptr;
407 static std::unique_ptr<SparcOperand>
408 CreateMEMr(unsigned Base, SMLoc S, SMLoc E) {
409 auto Op = make_unique<SparcOperand>(k_MemoryReg);
411 Op->Mem.OffsetReg = Sparc::G0; // always 0
412 Op->Mem.Off = nullptr;
418 static std::unique_ptr<SparcOperand>
419 MorphToMEMri(unsigned Base, std::unique_ptr<SparcOperand> Op) {
420 const MCExpr *Imm = Op->getImm();
421 Op->Kind = k_MemoryImm;
423 Op->Mem.OffsetReg = 0;
431 void SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc,
432 SmallVectorImpl<MCInst> &Instructions) {
433 MCOperand MCRegOp = Inst.getOperand(0);
434 MCOperand MCValOp = Inst.getOperand(1);
435 assert(MCRegOp.isReg());
436 assert(MCValOp.isImm() || MCValOp.isExpr());
438 // the imm operand can be either an expression or an immediate.
439 bool IsImm = Inst.getOperand(1).isImm();
440 int64_t RawImmValue = IsImm ? MCValOp.getImm() : 0;
442 // Allow either a signed or unsigned 32-bit immediate.
443 if (RawImmValue < -2147483648 || RawImmValue > 4294967295) {
444 Error(IDLoc, "set: argument must be between -2147483648 and 4294967295");
448 // If the value was expressed as a large unsigned number, that's ok.
449 // We want to see if it "looks like" a small signed number.
450 int32_t ImmValue = RawImmValue;
451 // For 'set' you can't use 'or' with a negative operand on V9 because
452 // that would splat the sign bit across the upper half of the destination
453 // register, whereas 'set' is defined to zero the high 32 bits.
454 bool IsEffectivelyImm13 =
455 IsImm && ((is64Bit() ? 0 : -4096) <= ImmValue && ImmValue < 4096);
456 const MCExpr *ValExpr;
458 ValExpr = MCConstantExpr::create(ImmValue, getContext());
460 ValExpr = MCValOp.getExpr();
462 MCOperand PrevReg = MCOperand::createReg(Sparc::G0);
464 // If not just a signed imm13 value, then either we use a 'sethi' with a
465 // following 'or', or a 'sethi' by itself if there are no more 1 bits.
466 // In either case, start with the 'sethi'.
467 if (!IsEffectivelyImm13) {
470 SparcMCExpr::create(SparcMCExpr::VK_Sparc_HI, ValExpr, getContext());
471 TmpInst.setLoc(IDLoc);
472 TmpInst.setOpcode(SP::SETHIi);
473 TmpInst.addOperand(MCRegOp);
474 TmpInst.addOperand(MCOperand::createExpr(Expr));
475 Instructions.push_back(TmpInst);
479 // The low bits require touching in 3 cases:
480 // * A non-immediate value will always require both instructions.
481 // * An effectively imm13 value needs only an 'or' instruction.
482 // * Otherwise, an immediate that is not effectively imm13 requires the
483 // 'or' only if bits remain after clearing the 22 bits that 'sethi' set.
484 // If the low bits are known zeros, there's nothing to do.
485 // In the second case, and only in that case, must we NOT clear
486 // bits of the immediate value via the %lo() assembler function.
487 // Note also, the 'or' instruction doesn't mind a large value in the case
488 // where the operand to 'set' was 0xFFFFFzzz - it does exactly what you mean.
489 if (!IsImm || IsEffectivelyImm13 || (ImmValue & 0x3ff)) {
492 if (IsEffectivelyImm13)
496 SparcMCExpr::create(SparcMCExpr::VK_Sparc_LO, ValExpr, getContext());
497 TmpInst.setLoc(IDLoc);
498 TmpInst.setOpcode(SP::ORri);
499 TmpInst.addOperand(MCRegOp);
500 TmpInst.addOperand(PrevReg);
501 TmpInst.addOperand(MCOperand::createExpr(Expr));
502 Instructions.push_back(TmpInst);
506 bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
507 OperandVector &Operands,
510 bool MatchingInlineAsm) {
512 SmallVector<MCInst, 8> Instructions;
513 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
515 switch (MatchResult) {
516 case Match_Success: {
517 switch (Inst.getOpcode()) {
520 Instructions.push_back(Inst);
523 expandSET(Inst, IDLoc, Instructions);
527 for (const MCInst &I : Instructions) {
528 Out.EmitInstruction(I, STI);
533 case Match_MissingFeature:
535 "instruction requires a CPU feature not currently enabled");
537 case Match_InvalidOperand: {
538 SMLoc ErrorLoc = IDLoc;
539 if (ErrorInfo != ~0ULL) {
540 if (ErrorInfo >= Operands.size())
541 return Error(IDLoc, "too few operands for instruction");
543 ErrorLoc = ((SparcOperand &)*Operands[ErrorInfo]).getStartLoc();
544 if (ErrorLoc == SMLoc())
548 return Error(ErrorLoc, "invalid operand for instruction");
550 case Match_MnemonicFail:
551 return Error(IDLoc, "invalid instruction mnemonic");
553 llvm_unreachable("Implement any new match types added!");
556 bool SparcAsmParser::
557 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)
559 const AsmToken &Tok = Parser.getTok();
560 StartLoc = Tok.getLoc();
561 EndLoc = Tok.getEndLoc();
563 if (getLexer().getKind() != AsmToken::Percent)
566 unsigned regKind = SparcOperand::rk_None;
567 if (matchRegisterName(Tok, RegNo, regKind)) {
572 return Error(StartLoc, "invalid register name");
575 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
578 bool SparcAsmParser::ParseInstruction(ParseInstructionInfo &Info,
579 StringRef Name, SMLoc NameLoc,
580 OperandVector &Operands) {
582 // First operand in MCInst is instruction mnemonic.
583 Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
585 // apply mnemonic aliases, if any, so that we can parse operands correctly.
586 applyMnemonicAliases(Name, getAvailableFeatures(), 0);
588 if (getLexer().isNot(AsmToken::EndOfStatement)) {
589 // Read the first operand.
590 if (getLexer().is(AsmToken::Comma)) {
591 if (parseBranchModifiers(Operands) != MatchOperand_Success) {
592 SMLoc Loc = getLexer().getLoc();
593 Parser.eatToEndOfStatement();
594 return Error(Loc, "unexpected token");
597 if (parseOperand(Operands, Name) != MatchOperand_Success) {
598 SMLoc Loc = getLexer().getLoc();
599 Parser.eatToEndOfStatement();
600 return Error(Loc, "unexpected token");
603 while (getLexer().is(AsmToken::Comma)) {
604 Parser.Lex(); // Eat the comma.
605 // Parse and remember the operand.
606 if (parseOperand(Operands, Name) != MatchOperand_Success) {
607 SMLoc Loc = getLexer().getLoc();
608 Parser.eatToEndOfStatement();
609 return Error(Loc, "unexpected token");
613 if (getLexer().isNot(AsmToken::EndOfStatement)) {
614 SMLoc Loc = getLexer().getLoc();
615 Parser.eatToEndOfStatement();
616 return Error(Loc, "unexpected token");
618 Parser.Lex(); // Consume the EndOfStatement.
622 bool SparcAsmParser::
623 ParseDirective(AsmToken DirectiveID)
625 StringRef IDVal = DirectiveID.getString();
627 if (IDVal == ".byte")
628 return parseDirectiveWord(1, DirectiveID.getLoc());
630 if (IDVal == ".half")
631 return parseDirectiveWord(2, DirectiveID.getLoc());
633 if (IDVal == ".word")
634 return parseDirectiveWord(4, DirectiveID.getLoc());
636 if (IDVal == ".nword")
637 return parseDirectiveWord(is64Bit() ? 8 : 4, DirectiveID.getLoc());
639 if (is64Bit() && IDVal == ".xword")
640 return parseDirectiveWord(8, DirectiveID.getLoc());
642 if (IDVal == ".register") {
643 // For now, ignore .register directive.
644 Parser.eatToEndOfStatement();
648 // Let the MC layer to handle other directives.
652 bool SparcAsmParser:: parseDirectiveWord(unsigned Size, SMLoc L) {
653 if (getLexer().isNot(AsmToken::EndOfStatement)) {
656 if (getParser().parseExpression(Value))
659 getParser().getStreamer().EmitValue(Value, Size);
661 if (getLexer().is(AsmToken::EndOfStatement))
664 // FIXME: Improve diagnostic.
665 if (getLexer().isNot(AsmToken::Comma))
666 return Error(L, "unexpected token in directive");
674 SparcAsmParser::OperandMatchResultTy
675 SparcAsmParser::parseMEMOperand(OperandVector &Operands) {
678 unsigned BaseReg = 0;
680 if (ParseRegister(BaseReg, S, E)) {
681 return MatchOperand_NoMatch;
684 switch (getLexer().getKind()) {
685 default: return MatchOperand_NoMatch;
687 case AsmToken::Comma:
688 case AsmToken::RBrac:
689 case AsmToken::EndOfStatement:
690 Operands.push_back(SparcOperand::CreateMEMr(BaseReg, S, E));
691 return MatchOperand_Success;
693 case AsmToken:: Plus:
694 Parser.Lex(); // Eat the '+'
696 case AsmToken::Minus:
700 std::unique_ptr<SparcOperand> Offset;
701 OperandMatchResultTy ResTy = parseSparcAsmOperand(Offset);
702 if (ResTy != MatchOperand_Success || !Offset)
703 return MatchOperand_NoMatch;
706 Offset->isImm() ? SparcOperand::MorphToMEMri(BaseReg, std::move(Offset))
707 : SparcOperand::MorphToMEMrr(BaseReg, std::move(Offset)));
709 return MatchOperand_Success;
712 SparcAsmParser::OperandMatchResultTy
713 SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
715 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
717 // If there wasn't a custom match, try the generic matcher below. Otherwise,
718 // there was a match, but an error occurred, in which case, just return that
719 // the operand parsing failed.
720 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
723 if (getLexer().is(AsmToken::LBrac)) {
725 Operands.push_back(SparcOperand::CreateToken("[",
726 Parser.getTok().getLoc()));
727 Parser.Lex(); // Eat the [
729 if (Mnemonic == "cas" || Mnemonic == "casx") {
730 SMLoc S = Parser.getTok().getLoc();
731 if (getLexer().getKind() != AsmToken::Percent)
732 return MatchOperand_NoMatch;
733 Parser.Lex(); // eat %
735 unsigned RegNo, RegKind;
736 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
737 return MatchOperand_NoMatch;
739 Parser.Lex(); // Eat the identifier token.
740 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
741 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
742 ResTy = MatchOperand_Success;
744 ResTy = parseMEMOperand(Operands);
747 if (ResTy != MatchOperand_Success)
750 if (!getLexer().is(AsmToken::RBrac))
751 return MatchOperand_ParseFail;
753 Operands.push_back(SparcOperand::CreateToken("]",
754 Parser.getTok().getLoc()));
755 Parser.Lex(); // Eat the ]
757 // Parse an optional address-space identifier after the address.
758 if (getLexer().is(AsmToken::Integer)) {
759 std::unique_ptr<SparcOperand> Op;
760 ResTy = parseSparcAsmOperand(Op, false);
761 if (ResTy != MatchOperand_Success || !Op)
762 return MatchOperand_ParseFail;
763 Operands.push_back(std::move(Op));
765 return MatchOperand_Success;
768 std::unique_ptr<SparcOperand> Op;
770 ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
771 if (ResTy != MatchOperand_Success || !Op)
772 return MatchOperand_ParseFail;
774 // Push the parsed operand into the list of operands
775 Operands.push_back(std::move(Op));
777 return MatchOperand_Success;
780 SparcAsmParser::OperandMatchResultTy
781 SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
784 SMLoc S = Parser.getTok().getLoc();
785 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
789 switch (getLexer().getKind()) {
792 case AsmToken::Percent:
793 Parser.Lex(); // Eat the '%'.
796 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
797 StringRef name = Parser.getTok().getString();
798 Parser.Lex(); // Eat the identifier token.
799 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
802 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
805 Op = SparcOperand::CreateToken("%psr", S);
808 Op = SparcOperand::CreateToken("%fsr", S);
811 Op = SparcOperand::CreateToken("%wim", S);
814 Op = SparcOperand::CreateToken("%tbr", S);
818 Op = SparcOperand::CreateToken("%xcc", S);
820 Op = SparcOperand::CreateToken("%icc", S);
825 if (matchSparcAsmModifiers(EVal, E)) {
826 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
827 Op = SparcOperand::CreateImm(EVal, S, E);
831 case AsmToken::Minus:
832 case AsmToken::Integer:
833 case AsmToken::LParen:
835 if (!getParser().parseExpression(EVal, E))
836 Op = SparcOperand::CreateImm(EVal, S, E);
839 case AsmToken::Identifier: {
840 StringRef Identifier;
841 if (!getParser().parseIdentifier(Identifier)) {
842 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
843 MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
845 const MCExpr *Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
848 getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_)
849 Res = SparcMCExpr::create(SparcMCExpr::VK_Sparc_WPLT30, Res,
851 Op = SparcOperand::CreateImm(Res, S, E);
856 return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
859 SparcAsmParser::OperandMatchResultTy
860 SparcAsmParser::parseBranchModifiers(OperandVector &Operands) {
862 // parse (,a|,pn|,pt)+
864 while (getLexer().is(AsmToken::Comma)) {
866 Parser.Lex(); // Eat the comma
868 if (!getLexer().is(AsmToken::Identifier))
869 return MatchOperand_ParseFail;
870 StringRef modName = Parser.getTok().getString();
871 if (modName == "a" || modName == "pn" || modName == "pt") {
872 Operands.push_back(SparcOperand::CreateToken(modName,
873 Parser.getTok().getLoc()));
874 Parser.Lex(); // eat the identifier.
877 return MatchOperand_Success;
880 bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
886 RegKind = SparcOperand::rk_None;
887 if (Tok.is(AsmToken::Identifier)) {
888 StringRef name = Tok.getString();
891 if (name.equals("fp")) {
893 RegKind = SparcOperand::rk_IntReg;
897 if (name.equals("sp")) {
899 RegKind = SparcOperand::rk_IntReg;
903 if (name.equals("y")) {
905 RegKind = SparcOperand::rk_Special;
909 if (name.substr(0, 3).equals_lower("asr")
910 && !name.substr(3).getAsInteger(10, intVal)
911 && intVal > 0 && intVal < 32) {
912 RegNo = ASRRegs[intVal];
913 RegKind = SparcOperand::rk_Special;
917 // %fprs is an alias of %asr6.
918 if (name.equals("fprs")) {
920 RegKind = SparcOperand::rk_Special;
924 if (name.equals("icc")) {
926 RegKind = SparcOperand::rk_Special;
930 if (name.equals("psr")) {
932 RegKind = SparcOperand::rk_Special;
936 if (name.equals("fsr")) {
938 RegKind = SparcOperand::rk_Special;
942 if (name.equals("wim")) {
944 RegKind = SparcOperand::rk_Special;
948 if (name.equals("tbr")) {
950 RegKind = SparcOperand::rk_Special;
954 if (name.equals("xcc")) {
955 // FIXME:: check 64bit.
957 RegKind = SparcOperand::rk_Special;
962 if (name.substr(0, 3).equals_lower("fcc")
963 && !name.substr(3).getAsInteger(10, intVal)
965 // FIXME: check 64bit and handle %fcc1 - %fcc3
966 RegNo = Sparc::FCC0 + intVal;
967 RegKind = SparcOperand::rk_Special;
972 if (name.substr(0, 1).equals_lower("g")
973 && !name.substr(1).getAsInteger(10, intVal)
975 RegNo = IntRegs[intVal];
976 RegKind = SparcOperand::rk_IntReg;
980 if (name.substr(0, 1).equals_lower("o")
981 && !name.substr(1).getAsInteger(10, intVal)
983 RegNo = IntRegs[8 + intVal];
984 RegKind = SparcOperand::rk_IntReg;
987 if (name.substr(0, 1).equals_lower("l")
988 && !name.substr(1).getAsInteger(10, intVal)
990 RegNo = IntRegs[16 + intVal];
991 RegKind = SparcOperand::rk_IntReg;
994 if (name.substr(0, 1).equals_lower("i")
995 && !name.substr(1).getAsInteger(10, intVal)
997 RegNo = IntRegs[24 + intVal];
998 RegKind = SparcOperand::rk_IntReg;
1002 if (name.substr(0, 1).equals_lower("f")
1003 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
1004 RegNo = FloatRegs[intVal];
1005 RegKind = SparcOperand::rk_FloatReg;
1009 if (name.substr(0, 1).equals_lower("f")
1010 && !name.substr(1, 2).getAsInteger(10, intVal)
1011 && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) {
1013 RegNo = DoubleRegs[intVal/2];
1014 RegKind = SparcOperand::rk_DoubleReg;
1019 if (name.substr(0, 1).equals_lower("r")
1020 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
1021 RegNo = IntRegs[intVal];
1022 RegKind = SparcOperand::rk_IntReg;
1029 // Determine if an expression contains a reference to the symbol
1030 // "_GLOBAL_OFFSET_TABLE_".
1031 static bool hasGOTReference(const MCExpr *Expr) {
1032 switch (Expr->getKind()) {
1033 case MCExpr::Target:
1034 if (const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
1035 return hasGOTReference(SE->getSubExpr());
1038 case MCExpr::Constant:
1041 case MCExpr::Binary: {
1042 const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
1043 return hasGOTReference(BE->getLHS()) || hasGOTReference(BE->getRHS());
1046 case MCExpr::SymbolRef: {
1047 const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);
1048 return (SymRef.getSymbol().getName() == "_GLOBAL_OFFSET_TABLE_");
1052 return hasGOTReference(cast<MCUnaryExpr>(Expr)->getSubExpr());
1057 bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
1060 AsmToken Tok = Parser.getTok();
1061 if (!Tok.is(AsmToken::Identifier))
1064 StringRef name = Tok.getString();
1066 SparcMCExpr::VariantKind VK = SparcMCExpr::parseVariantKind(name);
1068 if (VK == SparcMCExpr::VK_Sparc_None)
1071 Parser.Lex(); // Eat the identifier.
1072 if (Parser.getTok().getKind() != AsmToken::LParen)
1075 Parser.Lex(); // Eat the LParen token.
1076 const MCExpr *subExpr;
1077 if (Parser.parseParenExpression(subExpr, EndLoc))
1080 bool isPIC = getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_;
1082 // Ugly: if a sparc assembly expression says "%hi(...)" but the
1083 // expression within contains _GLOBAL_OFFSET_TABLE_, it REALLY means
1084 // %pc22. Same with %lo -> %pc10. Worse, if it doesn't contain that,
1085 // the meaning depends on whether the assembler was invoked with
1086 // -KPIC or not: if so, it really means %got22/%got10; if not, it
1087 // actually means what it said! Sigh, historical mistakes...
1091 case SparcMCExpr::VK_Sparc_LO:
1092 VK = (hasGOTReference(subExpr)
1093 ? SparcMCExpr::VK_Sparc_PC10
1094 : (isPIC ? SparcMCExpr::VK_Sparc_GOT10 : VK));
1096 case SparcMCExpr::VK_Sparc_HI:
1097 VK = (hasGOTReference(subExpr)
1098 ? SparcMCExpr::VK_Sparc_PC22
1099 : (isPIC ? SparcMCExpr::VK_Sparc_GOT22 : VK));
1103 EVal = SparcMCExpr::create(VK, subExpr, getContext());
1107 extern "C" void LLVMInitializeSparcAsmParser() {
1108 RegisterMCAsmParser<SparcAsmParser> A(TheSparcTarget);
1109 RegisterMCAsmParser<SparcAsmParser> B(TheSparcV9Target);
1110 RegisterMCAsmParser<SparcAsmParser> C(TheSparcelTarget);
1113 #define GET_REGISTER_MATCHER
1114 #define GET_MATCHER_IMPLEMENTATION
1115 #include "SparcGenAsmMatcher.inc"
1117 unsigned SparcAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,
1119 SparcOperand &Op = (SparcOperand &)GOp;
1120 if (Op.isFloatOrDoubleReg()) {
1124 if (!Op.isFloatReg() || SparcOperand::MorphToDoubleReg(Op))
1125 return MCTargetAsmParser::Match_Success;
1128 if (SparcOperand::MorphToQuadReg(Op))
1129 return MCTargetAsmParser::Match_Success;
1133 if (Op.isIntReg() && Kind == MCK_IntPair) {
1134 if (SparcOperand::MorphToIntPairReg(Op))
1135 return MCTargetAsmParser::Match_Success;
1137 return Match_InvalidOperand;