1 //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SparcMCTargetDesc.h"
11 #include "MCTargetDesc/SparcMCExpr.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCObjectFileInfo.h"
16 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/MC/MCSymbol.h"
20 #include "llvm/MC/MCTargetAsmParser.h"
21 #include "llvm/Support/TargetRegistry.h"
25 // The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target
26 // namespace. But SPARC backend uses "SP" as its namespace.
35 class SparcAsmParser : public MCTargetAsmParser {
40 /// @name Auto-generated Match Functions
43 #define GET_ASSEMBLER_HEADER
44 #include "SparcGenAsmMatcher.inc"
48 // public interface of the MCTargetAsmParser.
49 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
50 OperandVector &Operands, MCStreamer &Out,
52 bool MatchingInlineAsm) override;
53 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
54 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
55 SMLoc NameLoc, OperandVector &Operands) override;
56 bool ParseDirective(AsmToken DirectiveID) override;
58 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
59 unsigned Kind) override;
61 // Custom parse functions for Sparc specific operands.
62 OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
64 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
67 parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Operand,
70 OperandMatchResultTy parseBranchModifiers(OperandVector &Operands);
72 // returns true if Tok is matched to a register and returns register in RegNo.
73 bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
76 bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
77 bool parseDirectiveWord(unsigned Size, SMLoc L);
79 bool is64Bit() const { return STI.getTargetTriple().startswith("sparcv9"); }
81 SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
82 const MCInstrInfo &MII,
83 const MCTargetOptions &Options)
84 : MCTargetAsmParser(), STI(sti), Parser(parser) {
85 // Initialize the set of available features.
86 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
91 static unsigned IntRegs[32] = {
92 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
93 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
94 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
95 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
96 Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
97 Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
98 Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
99 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
101 static unsigned FloatRegs[32] = {
102 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
103 Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
104 Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
105 Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
106 Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
107 Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
108 Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
109 Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
111 static unsigned DoubleRegs[32] = {
112 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
113 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
114 Sparc::D8, Sparc::D7, Sparc::D8, Sparc::D9,
115 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
116 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
117 Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
118 Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
119 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
121 static unsigned QuadFPRegs[32] = {
122 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
123 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
124 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
125 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
128 /// SparcOperand - Instances of this class represent a parsed Sparc machine
130 class SparcOperand : public MCParsedAsmOperand {
150 SMLoc StartLoc, EndLoc;
179 SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
181 bool isToken() const override { return Kind == k_Token; }
182 bool isReg() const override { return Kind == k_Register; }
183 bool isImm() const override { return Kind == k_Immediate; }
184 bool isMem() const override { return isMEMrr() || isMEMri(); }
185 bool isMEMrr() const { return Kind == k_MemoryReg; }
186 bool isMEMri() const { return Kind == k_MemoryImm; }
188 bool isFloatReg() const {
189 return (Kind == k_Register && Reg.Kind == rk_FloatReg);
192 bool isFloatOrDoubleReg() const {
193 return (Kind == k_Register && (Reg.Kind == rk_FloatReg
194 || Reg.Kind == rk_DoubleReg));
198 StringRef getToken() const {
199 assert(Kind == k_Token && "Invalid access!");
200 return StringRef(Tok.Data, Tok.Length);
203 unsigned getReg() const override {
204 assert((Kind == k_Register) && "Invalid access!");
208 const MCExpr *getImm() const {
209 assert((Kind == k_Immediate) && "Invalid access!");
213 unsigned getMemBase() const {
214 assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!");
218 unsigned getMemOffsetReg() const {
219 assert((Kind == k_MemoryReg) && "Invalid access!");
220 return Mem.OffsetReg;
223 const MCExpr *getMemOff() const {
224 assert((Kind == k_MemoryImm) && "Invalid access!");
228 /// getStartLoc - Get the location of the first token of this operand.
229 SMLoc getStartLoc() const override {
232 /// getEndLoc - Get the location of the last token of this operand.
233 SMLoc getEndLoc() const override {
237 void print(raw_ostream &OS) const override {
239 case k_Token: OS << "Token: " << getToken() << "\n"; break;
240 case k_Register: OS << "Reg: #" << getReg() << "\n"; break;
241 case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
242 case k_MemoryReg: OS << "Mem: " << getMemBase() << "+"
243 << getMemOffsetReg() << "\n"; break;
244 case k_MemoryImm: assert(getMemOff() != nullptr);
245 OS << "Mem: " << getMemBase()
246 << "+" << *getMemOff()
251 void addRegOperands(MCInst &Inst, unsigned N) const {
252 assert(N == 1 && "Invalid number of operands!");
253 Inst.addOperand(MCOperand::CreateReg(getReg()));
256 void addImmOperands(MCInst &Inst, unsigned N) const {
257 assert(N == 1 && "Invalid number of operands!");
258 const MCExpr *Expr = getImm();
262 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
263 // Add as immediate when possible. Null MCExpr = 0.
265 Inst.addOperand(MCOperand::CreateImm(0));
266 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
267 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
269 Inst.addOperand(MCOperand::CreateExpr(Expr));
272 void addMEMrrOperands(MCInst &Inst, unsigned N) const {
273 assert(N == 2 && "Invalid number of operands!");
275 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
277 assert(getMemOffsetReg() != 0 && "Invalid offset");
278 Inst.addOperand(MCOperand::CreateReg(getMemOffsetReg()));
281 void addMEMriOperands(MCInst &Inst, unsigned N) const {
282 assert(N == 2 && "Invalid number of operands!");
284 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
286 const MCExpr *Expr = getMemOff();
290 static std::unique_ptr<SparcOperand> CreateToken(StringRef Str, SMLoc S) {
291 auto Op = make_unique<SparcOperand>(k_Token);
292 Op->Tok.Data = Str.data();
293 Op->Tok.Length = Str.size();
299 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind,
301 auto Op = make_unique<SparcOperand>(k_Register);
302 Op->Reg.RegNum = RegNum;
303 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind;
309 static std::unique_ptr<SparcOperand> CreateImm(const MCExpr *Val, SMLoc S,
311 auto Op = make_unique<SparcOperand>(k_Immediate);
318 static bool MorphToDoubleReg(SparcOperand &Op) {
319 unsigned Reg = Op.getReg();
320 assert(Op.Reg.Kind == rk_FloatReg);
321 unsigned regIdx = Reg - Sparc::F0;
322 if (regIdx % 2 || regIdx > 31)
324 Op.Reg.RegNum = DoubleRegs[regIdx / 2];
325 Op.Reg.Kind = rk_DoubleReg;
329 static bool MorphToQuadReg(SparcOperand &Op) {
330 unsigned Reg = Op.getReg();
332 switch (Op.Reg.Kind) {
333 default: llvm_unreachable("Unexpected register kind!");
335 regIdx = Reg - Sparc::F0;
336 if (regIdx % 4 || regIdx > 31)
338 Reg = QuadFPRegs[regIdx / 4];
341 regIdx = Reg - Sparc::D0;
342 if (regIdx % 2 || regIdx > 31)
344 Reg = QuadFPRegs[regIdx / 2];
348 Op.Reg.Kind = rk_QuadReg;
352 static std::unique_ptr<SparcOperand>
353 MorphToMEMrr(unsigned Base, std::unique_ptr<SparcOperand> Op) {
354 unsigned offsetReg = Op->getReg();
355 Op->Kind = k_MemoryReg;
357 Op->Mem.OffsetReg = offsetReg;
358 Op->Mem.Off = nullptr;
362 static std::unique_ptr<SparcOperand>
363 CreateMEMr(unsigned Base, SMLoc S, SMLoc E) {
364 auto Op = make_unique<SparcOperand>(k_MemoryReg);
366 Op->Mem.OffsetReg = Sparc::G0; // always 0
367 Op->Mem.Off = nullptr;
373 static std::unique_ptr<SparcOperand>
374 MorphToMEMri(unsigned Base, std::unique_ptr<SparcOperand> Op) {
375 const MCExpr *Imm = Op->getImm();
376 Op->Kind = k_MemoryImm;
378 Op->Mem.OffsetReg = 0;
386 bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
387 OperandVector &Operands,
390 bool MatchingInlineAsm) {
392 SmallVector<MCInst, 8> Instructions;
393 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
395 switch (MatchResult) {
396 case Match_Success: {
398 Out.EmitInstruction(Inst, STI);
402 case Match_MissingFeature:
404 "instruction requires a CPU feature not currently enabled");
406 case Match_InvalidOperand: {
407 SMLoc ErrorLoc = IDLoc;
408 if (ErrorInfo != ~0ULL) {
409 if (ErrorInfo >= Operands.size())
410 return Error(IDLoc, "too few operands for instruction");
412 ErrorLoc = ((SparcOperand &)*Operands[ErrorInfo]).getStartLoc();
413 if (ErrorLoc == SMLoc())
417 return Error(ErrorLoc, "invalid operand for instruction");
419 case Match_MnemonicFail:
420 return Error(IDLoc, "invalid instruction mnemonic");
422 llvm_unreachable("Implement any new match types added!");
425 bool SparcAsmParser::
426 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)
428 const AsmToken &Tok = Parser.getTok();
429 StartLoc = Tok.getLoc();
430 EndLoc = Tok.getEndLoc();
432 if (getLexer().getKind() != AsmToken::Percent)
435 unsigned regKind = SparcOperand::rk_None;
436 if (matchRegisterName(Tok, RegNo, regKind)) {
441 return Error(StartLoc, "invalid register name");
444 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
447 bool SparcAsmParser::ParseInstruction(ParseInstructionInfo &Info,
448 StringRef Name, SMLoc NameLoc,
449 OperandVector &Operands) {
451 // First operand in MCInst is instruction mnemonic.
452 Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
454 // apply mnemonic aliases, if any, so that we can parse operands correctly.
455 applyMnemonicAliases(Name, getAvailableFeatures(), 0);
457 if (getLexer().isNot(AsmToken::EndOfStatement)) {
458 // Read the first operand.
459 if (getLexer().is(AsmToken::Comma)) {
460 if (parseBranchModifiers(Operands) != MatchOperand_Success) {
461 SMLoc Loc = getLexer().getLoc();
462 Parser.eatToEndOfStatement();
463 return Error(Loc, "unexpected token");
466 if (parseOperand(Operands, Name) != MatchOperand_Success) {
467 SMLoc Loc = getLexer().getLoc();
468 Parser.eatToEndOfStatement();
469 return Error(Loc, "unexpected token");
472 while (getLexer().is(AsmToken::Comma)) {
473 Parser.Lex(); // Eat the comma.
474 // Parse and remember the operand.
475 if (parseOperand(Operands, Name) != MatchOperand_Success) {
476 SMLoc Loc = getLexer().getLoc();
477 Parser.eatToEndOfStatement();
478 return Error(Loc, "unexpected token");
482 if (getLexer().isNot(AsmToken::EndOfStatement)) {
483 SMLoc Loc = getLexer().getLoc();
484 Parser.eatToEndOfStatement();
485 return Error(Loc, "unexpected token");
487 Parser.Lex(); // Consume the EndOfStatement.
491 bool SparcAsmParser::
492 ParseDirective(AsmToken DirectiveID)
494 StringRef IDVal = DirectiveID.getString();
496 if (IDVal == ".byte")
497 return parseDirectiveWord(1, DirectiveID.getLoc());
499 if (IDVal == ".half")
500 return parseDirectiveWord(2, DirectiveID.getLoc());
502 if (IDVal == ".word")
503 return parseDirectiveWord(4, DirectiveID.getLoc());
505 if (IDVal == ".nword")
506 return parseDirectiveWord(is64Bit() ? 8 : 4, DirectiveID.getLoc());
508 if (is64Bit() && IDVal == ".xword")
509 return parseDirectiveWord(8, DirectiveID.getLoc());
511 if (IDVal == ".register") {
512 // For now, ignore .register directive.
513 Parser.eatToEndOfStatement();
517 // Let the MC layer to handle other directives.
521 bool SparcAsmParser:: parseDirectiveWord(unsigned Size, SMLoc L) {
522 if (getLexer().isNot(AsmToken::EndOfStatement)) {
525 if (getParser().parseExpression(Value))
528 getParser().getStreamer().EmitValue(Value, Size);
530 if (getLexer().is(AsmToken::EndOfStatement))
533 // FIXME: Improve diagnostic.
534 if (getLexer().isNot(AsmToken::Comma))
535 return Error(L, "unexpected token in directive");
543 SparcAsmParser::OperandMatchResultTy
544 SparcAsmParser::parseMEMOperand(OperandVector &Operands) {
547 unsigned BaseReg = 0;
549 if (ParseRegister(BaseReg, S, E)) {
550 return MatchOperand_NoMatch;
553 switch (getLexer().getKind()) {
554 default: return MatchOperand_NoMatch;
556 case AsmToken::Comma:
557 case AsmToken::RBrac:
558 case AsmToken::EndOfStatement:
559 Operands.push_back(SparcOperand::CreateMEMr(BaseReg, S, E));
560 return MatchOperand_Success;
562 case AsmToken:: Plus:
563 Parser.Lex(); // Eat the '+'
565 case AsmToken::Minus:
569 std::unique_ptr<SparcOperand> Offset;
570 OperandMatchResultTy ResTy = parseSparcAsmOperand(Offset);
571 if (ResTy != MatchOperand_Success || !Offset)
572 return MatchOperand_NoMatch;
575 Offset->isImm() ? SparcOperand::MorphToMEMri(BaseReg, std::move(Offset))
576 : SparcOperand::MorphToMEMrr(BaseReg, std::move(Offset)));
578 return MatchOperand_Success;
581 SparcAsmParser::OperandMatchResultTy
582 SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
584 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
586 // If there wasn't a custom match, try the generic matcher below. Otherwise,
587 // there was a match, but an error occurred, in which case, just return that
588 // the operand parsing failed.
589 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
592 if (getLexer().is(AsmToken::LBrac)) {
594 Operands.push_back(SparcOperand::CreateToken("[",
595 Parser.getTok().getLoc()));
596 Parser.Lex(); // Eat the [
598 if (Mnemonic == "cas" || Mnemonic == "casx") {
599 SMLoc S = Parser.getTok().getLoc();
600 if (getLexer().getKind() != AsmToken::Percent)
601 return MatchOperand_NoMatch;
602 Parser.Lex(); // eat %
604 unsigned RegNo, RegKind;
605 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
606 return MatchOperand_NoMatch;
608 Parser.Lex(); // Eat the identifier token.
609 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
610 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
611 ResTy = MatchOperand_Success;
613 ResTy = parseMEMOperand(Operands);
616 if (ResTy != MatchOperand_Success)
619 if (!getLexer().is(AsmToken::RBrac))
620 return MatchOperand_ParseFail;
622 Operands.push_back(SparcOperand::CreateToken("]",
623 Parser.getTok().getLoc()));
624 Parser.Lex(); // Eat the ]
625 return MatchOperand_Success;
628 std::unique_ptr<SparcOperand> Op;
630 ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
631 if (ResTy != MatchOperand_Success || !Op)
632 return MatchOperand_ParseFail;
634 // Push the parsed operand into the list of operands
635 Operands.push_back(std::move(Op));
637 return MatchOperand_Success;
640 SparcAsmParser::OperandMatchResultTy
641 SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
644 SMLoc S = Parser.getTok().getLoc();
645 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
649 switch (getLexer().getKind()) {
652 case AsmToken::Percent:
653 Parser.Lex(); // Eat the '%'.
656 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
657 StringRef name = Parser.getTok().getString();
658 Parser.Lex(); // Eat the identifier token.
659 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
662 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
665 Op = SparcOperand::CreateToken("%y", S);
670 Op = SparcOperand::CreateToken("%xcc", S);
672 Op = SparcOperand::CreateToken("%icc", S);
677 if (matchSparcAsmModifiers(EVal, E)) {
678 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
679 Op = SparcOperand::CreateImm(EVal, S, E);
683 case AsmToken::Minus:
684 case AsmToken::Integer:
685 case AsmToken::LParen:
686 if (!getParser().parseExpression(EVal, E))
687 Op = SparcOperand::CreateImm(EVal, S, E);
690 case AsmToken::Identifier: {
691 StringRef Identifier;
692 if (!getParser().parseIdentifier(Identifier)) {
693 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
694 MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
696 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
699 getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_)
700 Res = SparcMCExpr::Create(SparcMCExpr::VK_Sparc_WPLT30, Res,
702 Op = SparcOperand::CreateImm(Res, S, E);
707 return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
710 SparcAsmParser::OperandMatchResultTy
711 SparcAsmParser::parseBranchModifiers(OperandVector &Operands) {
713 // parse (,a|,pn|,pt)+
715 while (getLexer().is(AsmToken::Comma)) {
717 Parser.Lex(); // Eat the comma
719 if (!getLexer().is(AsmToken::Identifier))
720 return MatchOperand_ParseFail;
721 StringRef modName = Parser.getTok().getString();
722 if (modName == "a" || modName == "pn" || modName == "pt") {
723 Operands.push_back(SparcOperand::CreateToken(modName,
724 Parser.getTok().getLoc()));
725 Parser.Lex(); // eat the identifier.
728 return MatchOperand_Success;
731 bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
737 RegKind = SparcOperand::rk_None;
738 if (Tok.is(AsmToken::Identifier)) {
739 StringRef name = Tok.getString();
742 if (name.equals("fp")) {
744 RegKind = SparcOperand::rk_IntReg;
748 if (name.equals("sp")) {
750 RegKind = SparcOperand::rk_IntReg;
754 if (name.equals("y")) {
756 RegKind = SparcOperand::rk_Y;
760 if (name.equals("icc")) {
762 RegKind = SparcOperand::rk_CCReg;
766 if (name.equals("xcc")) {
767 // FIXME:: check 64bit.
769 RegKind = SparcOperand::rk_CCReg;
774 if (name.substr(0, 3).equals_lower("fcc")
775 && !name.substr(3).getAsInteger(10, intVal)
777 // FIXME: check 64bit and handle %fcc1 - %fcc3
778 RegNo = Sparc::FCC0 + intVal;
779 RegKind = SparcOperand::rk_CCReg;
784 if (name.substr(0, 1).equals_lower("g")
785 && !name.substr(1).getAsInteger(10, intVal)
787 RegNo = IntRegs[intVal];
788 RegKind = SparcOperand::rk_IntReg;
792 if (name.substr(0, 1).equals_lower("o")
793 && !name.substr(1).getAsInteger(10, intVal)
795 RegNo = IntRegs[8 + intVal];
796 RegKind = SparcOperand::rk_IntReg;
799 if (name.substr(0, 1).equals_lower("l")
800 && !name.substr(1).getAsInteger(10, intVal)
802 RegNo = IntRegs[16 + intVal];
803 RegKind = SparcOperand::rk_IntReg;
806 if (name.substr(0, 1).equals_lower("i")
807 && !name.substr(1).getAsInteger(10, intVal)
809 RegNo = IntRegs[24 + intVal];
810 RegKind = SparcOperand::rk_IntReg;
814 if (name.substr(0, 1).equals_lower("f")
815 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
816 RegNo = FloatRegs[intVal];
817 RegKind = SparcOperand::rk_FloatReg;
821 if (name.substr(0, 1).equals_lower("f")
822 && !name.substr(1, 2).getAsInteger(10, intVal)
823 && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) {
825 RegNo = DoubleRegs[intVal/2];
826 RegKind = SparcOperand::rk_DoubleReg;
831 if (name.substr(0, 1).equals_lower("r")
832 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
833 RegNo = IntRegs[intVal];
834 RegKind = SparcOperand::rk_IntReg;
841 static bool hasGOTReference(const MCExpr *Expr) {
842 switch (Expr->getKind()) {
844 if (const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
845 return hasGOTReference(SE->getSubExpr());
848 case MCExpr::Constant:
851 case MCExpr::Binary: {
852 const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
853 return hasGOTReference(BE->getLHS()) || hasGOTReference(BE->getRHS());
856 case MCExpr::SymbolRef: {
857 const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);
858 return (SymRef.getSymbol().getName() == "_GLOBAL_OFFSET_TABLE_");
862 return hasGOTReference(cast<MCUnaryExpr>(Expr)->getSubExpr());
867 bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
870 AsmToken Tok = Parser.getTok();
871 if (!Tok.is(AsmToken::Identifier))
874 StringRef name = Tok.getString();
876 SparcMCExpr::VariantKind VK = SparcMCExpr::parseVariantKind(name);
878 if (VK == SparcMCExpr::VK_Sparc_None)
881 Parser.Lex(); // Eat the identifier.
882 if (Parser.getTok().getKind() != AsmToken::LParen)
885 Parser.Lex(); // Eat the LParen token.
886 const MCExpr *subExpr;
887 if (Parser.parseParenExpression(subExpr, EndLoc))
890 bool isPIC = getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_;
894 case SparcMCExpr::VK_Sparc_LO:
895 VK = (hasGOTReference(subExpr)
896 ? SparcMCExpr::VK_Sparc_PC10
897 : (isPIC ? SparcMCExpr::VK_Sparc_GOT10 : VK));
899 case SparcMCExpr::VK_Sparc_HI:
900 VK = (hasGOTReference(subExpr)
901 ? SparcMCExpr::VK_Sparc_PC22
902 : (isPIC ? SparcMCExpr::VK_Sparc_GOT22 : VK));
906 EVal = SparcMCExpr::Create(VK, subExpr, getContext());
911 extern "C" void LLVMInitializeSparcAsmParser() {
912 RegisterMCAsmParser<SparcAsmParser> A(TheSparcTarget);
913 RegisterMCAsmParser<SparcAsmParser> B(TheSparcV9Target);
916 #define GET_REGISTER_MATCHER
917 #define GET_MATCHER_IMPLEMENTATION
918 #include "SparcGenAsmMatcher.inc"
920 unsigned SparcAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,
922 SparcOperand &Op = (SparcOperand &)GOp;
923 if (Op.isFloatOrDoubleReg()) {
927 if (!Op.isFloatReg() || SparcOperand::MorphToDoubleReg(Op))
928 return MCTargetAsmParser::Match_Success;
931 if (SparcOperand::MorphToQuadReg(Op))
932 return MCTargetAsmParser::Match_Success;
936 return Match_InvalidOperand;