1 //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SparcMCTargetDesc.h"
11 #include "MCTargetDesc/SparcMCExpr.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCObjectFileInfo.h"
16 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/MC/MCSymbol.h"
20 #include "llvm/MC/MCTargetAsmParser.h"
21 #include "llvm/Support/TargetRegistry.h"
25 // The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target
26 // namespace. But SPARC backend uses "SP" as its namespace.
35 class SparcAsmParser : public MCTargetAsmParser {
40 /// @name Auto-generated Match Functions
43 #define GET_ASSEMBLER_HEADER
44 #include "SparcGenAsmMatcher.inc"
48 // public interface of the MCTargetAsmParser.
49 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
50 OperandVector &Operands, MCStreamer &Out,
52 bool MatchingInlineAsm) override;
53 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
54 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
55 SMLoc NameLoc, OperandVector &Operands) override;
56 bool ParseDirective(AsmToken DirectiveID) override;
58 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
59 unsigned Kind) override;
61 // Custom parse functions for Sparc specific operands.
62 OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
64 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
67 parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Operand,
70 OperandMatchResultTy parseBranchModifiers(OperandVector &Operands);
72 // returns true if Tok is matched to a register and returns register in RegNo.
73 bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
76 bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
77 bool parseDirectiveWord(unsigned Size, SMLoc L);
79 bool is64Bit() const { return STI.getTargetTriple().startswith("sparcv9"); }
81 SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
82 const MCInstrInfo &MII,
83 const MCTargetOptions &Options)
84 : MCTargetAsmParser(), STI(sti), Parser(parser) {
85 // Initialize the set of available features.
86 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
91 static unsigned IntRegs[32] = {
92 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
93 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
94 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
95 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
96 Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
97 Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
98 Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
99 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
101 static unsigned FloatRegs[32] = {
102 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
103 Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
104 Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
105 Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
106 Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
107 Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
108 Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
109 Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
111 static unsigned DoubleRegs[32] = {
112 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
113 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
114 Sparc::D8, Sparc::D7, Sparc::D8, Sparc::D9,
115 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
116 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
117 Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
118 Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
119 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
121 static unsigned QuadFPRegs[32] = {
122 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
123 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
124 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
125 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
128 /// SparcOperand - Instances of this class represent a parsed Sparc machine
130 class SparcOperand : public MCParsedAsmOperand {
150 SMLoc StartLoc, EndLoc;
179 SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
181 bool isToken() const override { return Kind == k_Token; }
182 bool isReg() const override { return Kind == k_Register; }
183 bool isImm() const override { return Kind == k_Immediate; }
184 bool isMem() const override { return isMEMrr() || isMEMri(); }
185 bool isMEMrr() const { return Kind == k_MemoryReg; }
186 bool isMEMri() const { return Kind == k_MemoryImm; }
188 bool isFloatReg() const {
189 return (Kind == k_Register && Reg.Kind == rk_FloatReg);
192 bool isFloatOrDoubleReg() const {
193 return (Kind == k_Register && (Reg.Kind == rk_FloatReg
194 || Reg.Kind == rk_DoubleReg));
198 StringRef getToken() const {
199 assert(Kind == k_Token && "Invalid access!");
200 return StringRef(Tok.Data, Tok.Length);
203 unsigned getReg() const override {
204 assert((Kind == k_Register) && "Invalid access!");
208 const MCExpr *getImm() const {
209 assert((Kind == k_Immediate) && "Invalid access!");
213 unsigned getMemBase() const {
214 assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!");
218 unsigned getMemOffsetReg() const {
219 assert((Kind == k_MemoryReg) && "Invalid access!");
220 return Mem.OffsetReg;
223 const MCExpr *getMemOff() const {
224 assert((Kind == k_MemoryImm) && "Invalid access!");
228 /// getStartLoc - Get the location of the first token of this operand.
229 SMLoc getStartLoc() const override {
232 /// getEndLoc - Get the location of the last token of this operand.
233 SMLoc getEndLoc() const override {
237 void print(raw_ostream &OS) const override {
239 case k_Token: OS << "Token: " << getToken() << "\n"; break;
240 case k_Register: OS << "Reg: #" << getReg() << "\n"; break;
241 case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
242 case k_MemoryReg: OS << "Mem: " << getMemBase() << "+"
243 << getMemOffsetReg() << "\n"; break;
244 case k_MemoryImm: assert(getMemOff() != nullptr);
245 OS << "Mem: " << getMemBase()
246 << "+" << *getMemOff()
251 void addRegOperands(MCInst &Inst, unsigned N) const {
252 assert(N == 1 && "Invalid number of operands!");
253 Inst.addOperand(MCOperand::CreateReg(getReg()));
256 void addImmOperands(MCInst &Inst, unsigned N) const {
257 assert(N == 1 && "Invalid number of operands!");
258 const MCExpr *Expr = getImm();
262 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
263 // Add as immediate when possible. Null MCExpr = 0.
265 Inst.addOperand(MCOperand::CreateImm(0));
266 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
267 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
269 Inst.addOperand(MCOperand::CreateExpr(Expr));
272 void addMEMrrOperands(MCInst &Inst, unsigned N) const {
273 assert(N == 2 && "Invalid number of operands!");
275 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
277 assert(getMemOffsetReg() != 0 && "Invalid offset");
278 Inst.addOperand(MCOperand::CreateReg(getMemOffsetReg()));
281 void addMEMriOperands(MCInst &Inst, unsigned N) const {
282 assert(N == 2 && "Invalid number of operands!");
284 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
286 const MCExpr *Expr = getMemOff();
290 static std::unique_ptr<SparcOperand> CreateToken(StringRef Str, SMLoc S) {
291 auto Op = make_unique<SparcOperand>(k_Token);
292 Op->Tok.Data = Str.data();
293 Op->Tok.Length = Str.size();
299 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind,
301 auto Op = make_unique<SparcOperand>(k_Register);
302 Op->Reg.RegNum = RegNum;
303 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind;
309 static std::unique_ptr<SparcOperand> CreateImm(const MCExpr *Val, SMLoc S,
311 auto Op = make_unique<SparcOperand>(k_Immediate);
318 static bool MorphToDoubleReg(SparcOperand &Op) {
319 unsigned Reg = Op.getReg();
320 assert(Op.Reg.Kind == rk_FloatReg);
321 unsigned regIdx = Reg - Sparc::F0;
322 if (regIdx % 2 || regIdx > 31)
324 Op.Reg.RegNum = DoubleRegs[regIdx / 2];
325 Op.Reg.Kind = rk_DoubleReg;
329 static bool MorphToQuadReg(SparcOperand &Op) {
330 unsigned Reg = Op.getReg();
332 switch (Op.Reg.Kind) {
333 default: llvm_unreachable("Unexpected register kind!");
335 regIdx = Reg - Sparc::F0;
336 if (regIdx % 4 || regIdx > 31)
338 Reg = QuadFPRegs[regIdx / 4];
341 regIdx = Reg - Sparc::D0;
342 if (regIdx % 2 || regIdx > 31)
344 Reg = QuadFPRegs[regIdx / 2];
348 Op.Reg.Kind = rk_QuadReg;
352 static std::unique_ptr<SparcOperand>
353 MorphToMEMrr(unsigned Base, std::unique_ptr<SparcOperand> Op) {
354 unsigned offsetReg = Op->getReg();
355 Op->Kind = k_MemoryReg;
357 Op->Mem.OffsetReg = offsetReg;
358 Op->Mem.Off = nullptr;
362 static std::unique_ptr<SparcOperand>
363 CreateMEMri(unsigned Base, const MCExpr *Off, SMLoc S, SMLoc E) {
364 auto Op = make_unique<SparcOperand>(k_MemoryImm);
366 Op->Mem.OffsetReg = 0;
373 static std::unique_ptr<SparcOperand>
374 MorphToMEMri(unsigned Base, std::unique_ptr<SparcOperand> Op) {
375 const MCExpr *Imm = Op->getImm();
376 Op->Kind = k_MemoryImm;
378 Op->Mem.OffsetReg = 0;
386 bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
387 OperandVector &Operands,
390 bool MatchingInlineAsm) {
392 SmallVector<MCInst, 8> Instructions;
393 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
395 switch (MatchResult) {
399 case Match_Success: {
401 Out.EmitInstruction(Inst, STI);
405 case Match_MissingFeature:
407 "instruction requires a CPU feature not currently enabled");
409 case Match_InvalidOperand: {
410 SMLoc ErrorLoc = IDLoc;
411 if (ErrorInfo != ~0U) {
412 if (ErrorInfo >= Operands.size())
413 return Error(IDLoc, "too few operands for instruction");
415 ErrorLoc = ((SparcOperand &)*Operands[ErrorInfo]).getStartLoc();
416 if (ErrorLoc == SMLoc())
420 return Error(ErrorLoc, "invalid operand for instruction");
422 case Match_MnemonicFail:
423 return Error(IDLoc, "invalid instruction mnemonic");
428 bool SparcAsmParser::
429 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)
431 const AsmToken &Tok = Parser.getTok();
432 StartLoc = Tok.getLoc();
433 EndLoc = Tok.getEndLoc();
435 if (getLexer().getKind() != AsmToken::Percent)
438 unsigned regKind = SparcOperand::rk_None;
439 if (matchRegisterName(Tok, RegNo, regKind)) {
444 return Error(StartLoc, "invalid register name");
447 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
450 bool SparcAsmParser::ParseInstruction(ParseInstructionInfo &Info,
451 StringRef Name, SMLoc NameLoc,
452 OperandVector &Operands) {
454 // First operand in MCInst is instruction mnemonic.
455 Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
457 // apply mnemonic aliases, if any, so that we can parse operands correctly.
458 applyMnemonicAliases(Name, getAvailableFeatures(), 0);
460 if (getLexer().isNot(AsmToken::EndOfStatement)) {
461 // Read the first operand.
462 if (getLexer().is(AsmToken::Comma)) {
463 if (parseBranchModifiers(Operands) != MatchOperand_Success) {
464 SMLoc Loc = getLexer().getLoc();
465 Parser.eatToEndOfStatement();
466 return Error(Loc, "unexpected token");
469 if (parseOperand(Operands, Name) != MatchOperand_Success) {
470 SMLoc Loc = getLexer().getLoc();
471 Parser.eatToEndOfStatement();
472 return Error(Loc, "unexpected token");
475 while (getLexer().is(AsmToken::Comma)) {
476 Parser.Lex(); // Eat the comma.
477 // Parse and remember the operand.
478 if (parseOperand(Operands, Name) != MatchOperand_Success) {
479 SMLoc Loc = getLexer().getLoc();
480 Parser.eatToEndOfStatement();
481 return Error(Loc, "unexpected token");
485 if (getLexer().isNot(AsmToken::EndOfStatement)) {
486 SMLoc Loc = getLexer().getLoc();
487 Parser.eatToEndOfStatement();
488 return Error(Loc, "unexpected token");
490 Parser.Lex(); // Consume the EndOfStatement.
494 bool SparcAsmParser::
495 ParseDirective(AsmToken DirectiveID)
497 StringRef IDVal = DirectiveID.getString();
499 if (IDVal == ".byte")
500 return parseDirectiveWord(1, DirectiveID.getLoc());
502 if (IDVal == ".half")
503 return parseDirectiveWord(2, DirectiveID.getLoc());
505 if (IDVal == ".word")
506 return parseDirectiveWord(4, DirectiveID.getLoc());
508 if (IDVal == ".nword")
509 return parseDirectiveWord(is64Bit() ? 8 : 4, DirectiveID.getLoc());
511 if (is64Bit() && IDVal == ".xword")
512 return parseDirectiveWord(8, DirectiveID.getLoc());
514 if (IDVal == ".register") {
515 // For now, ignore .register directive.
516 Parser.eatToEndOfStatement();
520 // Let the MC layer to handle other directives.
524 bool SparcAsmParser:: parseDirectiveWord(unsigned Size, SMLoc L) {
525 if (getLexer().isNot(AsmToken::EndOfStatement)) {
528 if (getParser().parseExpression(Value))
531 getParser().getStreamer().EmitValue(Value, Size);
533 if (getLexer().is(AsmToken::EndOfStatement))
536 // FIXME: Improve diagnostic.
537 if (getLexer().isNot(AsmToken::Comma))
538 return Error(L, "unexpected token in directive");
546 SparcAsmParser::OperandMatchResultTy
547 SparcAsmParser::parseMEMOperand(OperandVector &Operands) {
550 unsigned BaseReg = 0;
552 if (ParseRegister(BaseReg, S, E)) {
553 return MatchOperand_NoMatch;
556 switch (getLexer().getKind()) {
557 default: return MatchOperand_NoMatch;
559 case AsmToken::Comma:
560 case AsmToken::RBrac:
561 case AsmToken::EndOfStatement:
562 Operands.push_back(SparcOperand::CreateMEMri(BaseReg, nullptr, S, E));
563 return MatchOperand_Success;
565 case AsmToken:: Plus:
566 Parser.Lex(); // Eat the '+'
568 case AsmToken::Minus:
572 std::unique_ptr<SparcOperand> Offset;
573 OperandMatchResultTy ResTy = parseSparcAsmOperand(Offset);
574 if (ResTy != MatchOperand_Success || !Offset)
575 return MatchOperand_NoMatch;
578 Offset->isImm() ? SparcOperand::MorphToMEMri(BaseReg, std::move(Offset))
579 : SparcOperand::MorphToMEMrr(BaseReg, std::move(Offset)));
581 return MatchOperand_Success;
584 SparcAsmParser::OperandMatchResultTy
585 SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
587 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
589 // If there wasn't a custom match, try the generic matcher below. Otherwise,
590 // there was a match, but an error occurred, in which case, just return that
591 // the operand parsing failed.
592 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
595 if (getLexer().is(AsmToken::LBrac)) {
597 Operands.push_back(SparcOperand::CreateToken("[",
598 Parser.getTok().getLoc()));
599 Parser.Lex(); // Eat the [
601 if (Mnemonic == "cas" || Mnemonic == "casx") {
602 SMLoc S = Parser.getTok().getLoc();
603 if (getLexer().getKind() != AsmToken::Percent)
604 return MatchOperand_NoMatch;
605 Parser.Lex(); // eat %
607 unsigned RegNo, RegKind;
608 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
609 return MatchOperand_NoMatch;
611 Parser.Lex(); // Eat the identifier token.
612 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
613 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
614 ResTy = MatchOperand_Success;
616 ResTy = parseMEMOperand(Operands);
619 if (ResTy != MatchOperand_Success)
622 if (!getLexer().is(AsmToken::RBrac))
623 return MatchOperand_ParseFail;
625 Operands.push_back(SparcOperand::CreateToken("]",
626 Parser.getTok().getLoc()));
627 Parser.Lex(); // Eat the ]
628 return MatchOperand_Success;
631 std::unique_ptr<SparcOperand> Op;
633 ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
634 if (ResTy != MatchOperand_Success || !Op)
635 return MatchOperand_ParseFail;
637 // Push the parsed operand into the list of operands
638 Operands.push_back(std::move(Op));
640 return MatchOperand_Success;
643 SparcAsmParser::OperandMatchResultTy
644 SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
647 SMLoc S = Parser.getTok().getLoc();
648 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
652 switch (getLexer().getKind()) {
655 case AsmToken::Percent:
656 Parser.Lex(); // Eat the '%'.
659 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
660 StringRef name = Parser.getTok().getString();
661 Parser.Lex(); // Eat the identifier token.
662 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
665 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
668 Op = SparcOperand::CreateToken("%y", S);
673 Op = SparcOperand::CreateToken("%xcc", S);
675 Op = SparcOperand::CreateToken("%icc", S);
680 if (matchSparcAsmModifiers(EVal, E)) {
681 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
682 Op = SparcOperand::CreateImm(EVal, S, E);
686 case AsmToken::Minus:
687 case AsmToken::Integer:
688 if (!getParser().parseExpression(EVal, E))
689 Op = SparcOperand::CreateImm(EVal, S, E);
692 case AsmToken::Identifier: {
693 StringRef Identifier;
694 if (!getParser().parseIdentifier(Identifier)) {
695 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
696 MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
698 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
701 getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_)
702 Res = SparcMCExpr::Create(SparcMCExpr::VK_Sparc_WPLT30, Res,
704 Op = SparcOperand::CreateImm(Res, S, E);
709 return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
712 SparcAsmParser::OperandMatchResultTy
713 SparcAsmParser::parseBranchModifiers(OperandVector &Operands) {
715 // parse (,a|,pn|,pt)+
717 while (getLexer().is(AsmToken::Comma)) {
719 Parser.Lex(); // Eat the comma
721 if (!getLexer().is(AsmToken::Identifier))
722 return MatchOperand_ParseFail;
723 StringRef modName = Parser.getTok().getString();
724 if (modName == "a" || modName == "pn" || modName == "pt") {
725 Operands.push_back(SparcOperand::CreateToken(modName,
726 Parser.getTok().getLoc()));
727 Parser.Lex(); // eat the identifier.
730 return MatchOperand_Success;
733 bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
739 RegKind = SparcOperand::rk_None;
740 if (Tok.is(AsmToken::Identifier)) {
741 StringRef name = Tok.getString();
744 if (name.equals("fp")) {
746 RegKind = SparcOperand::rk_IntReg;
750 if (name.equals("sp")) {
752 RegKind = SparcOperand::rk_IntReg;
756 if (name.equals("y")) {
758 RegKind = SparcOperand::rk_Y;
762 if (name.equals("icc")) {
764 RegKind = SparcOperand::rk_CCReg;
768 if (name.equals("xcc")) {
769 // FIXME:: check 64bit.
771 RegKind = SparcOperand::rk_CCReg;
776 if (name.substr(0, 3).equals_lower("fcc")
777 && !name.substr(3).getAsInteger(10, intVal)
779 // FIXME: check 64bit and handle %fcc1 - %fcc3
780 RegNo = Sparc::FCC0 + intVal;
781 RegKind = SparcOperand::rk_CCReg;
786 if (name.substr(0, 1).equals_lower("g")
787 && !name.substr(1).getAsInteger(10, intVal)
789 RegNo = IntRegs[intVal];
790 RegKind = SparcOperand::rk_IntReg;
794 if (name.substr(0, 1).equals_lower("o")
795 && !name.substr(1).getAsInteger(10, intVal)
797 RegNo = IntRegs[8 + intVal];
798 RegKind = SparcOperand::rk_IntReg;
801 if (name.substr(0, 1).equals_lower("l")
802 && !name.substr(1).getAsInteger(10, intVal)
804 RegNo = IntRegs[16 + intVal];
805 RegKind = SparcOperand::rk_IntReg;
808 if (name.substr(0, 1).equals_lower("i")
809 && !name.substr(1).getAsInteger(10, intVal)
811 RegNo = IntRegs[24 + intVal];
812 RegKind = SparcOperand::rk_IntReg;
816 if (name.substr(0, 1).equals_lower("f")
817 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
818 RegNo = FloatRegs[intVal];
819 RegKind = SparcOperand::rk_FloatReg;
823 if (name.substr(0, 1).equals_lower("f")
824 && !name.substr(1, 2).getAsInteger(10, intVal)
825 && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) {
827 RegNo = DoubleRegs[intVal/2];
828 RegKind = SparcOperand::rk_DoubleReg;
833 if (name.substr(0, 1).equals_lower("r")
834 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
835 RegNo = IntRegs[intVal];
836 RegKind = SparcOperand::rk_IntReg;
843 static bool hasGOTReference(const MCExpr *Expr) {
844 switch (Expr->getKind()) {
846 if (const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
847 return hasGOTReference(SE->getSubExpr());
850 case MCExpr::Constant:
853 case MCExpr::Binary: {
854 const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
855 return hasGOTReference(BE->getLHS()) || hasGOTReference(BE->getRHS());
858 case MCExpr::SymbolRef: {
859 const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);
860 return (SymRef.getSymbol().getName() == "_GLOBAL_OFFSET_TABLE_");
864 return hasGOTReference(cast<MCUnaryExpr>(Expr)->getSubExpr());
869 bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
872 AsmToken Tok = Parser.getTok();
873 if (!Tok.is(AsmToken::Identifier))
876 StringRef name = Tok.getString();
878 SparcMCExpr::VariantKind VK = SparcMCExpr::parseVariantKind(name);
880 if (VK == SparcMCExpr::VK_Sparc_None)
883 Parser.Lex(); // Eat the identifier.
884 if (Parser.getTok().getKind() != AsmToken::LParen)
887 Parser.Lex(); // Eat the LParen token.
888 const MCExpr *subExpr;
889 if (Parser.parseParenExpression(subExpr, EndLoc))
892 bool isPIC = getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_;
896 case SparcMCExpr::VK_Sparc_LO:
897 VK = (hasGOTReference(subExpr)
898 ? SparcMCExpr::VK_Sparc_PC10
899 : (isPIC ? SparcMCExpr::VK_Sparc_GOT10 : VK));
901 case SparcMCExpr::VK_Sparc_HI:
902 VK = (hasGOTReference(subExpr)
903 ? SparcMCExpr::VK_Sparc_PC22
904 : (isPIC ? SparcMCExpr::VK_Sparc_GOT22 : VK));
908 EVal = SparcMCExpr::Create(VK, subExpr, getContext());
913 extern "C" void LLVMInitializeSparcAsmParser() {
914 RegisterMCAsmParser<SparcAsmParser> A(TheSparcTarget);
915 RegisterMCAsmParser<SparcAsmParser> B(TheSparcV9Target);
918 #define GET_REGISTER_MATCHER
919 #define GET_MATCHER_IMPLEMENTATION
920 #include "SparcGenAsmMatcher.inc"
922 unsigned SparcAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,
924 SparcOperand &Op = (SparcOperand &)GOp;
925 if (Op.isFloatOrDoubleReg()) {
929 if (!Op.isFloatReg() || SparcOperand::MorphToDoubleReg(Op))
930 return MCTargetAsmParser::Match_Success;
933 if (SparcOperand::MorphToQuadReg(Op))
934 return MCTargetAsmParser::Match_Success;
938 return Match_InvalidOperand;