1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIRegisterInfo
13 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
17 #define LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
19 #include "AMDGPURegisterInfo.h"
23 struct SIRegisterInfo : public AMDGPURegisterInfo {
25 SIRegisterInfo(const AMDGPUSubtarget &st);
27 BitVector getReservedRegs(const MachineFunction &MF) const override;
29 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
30 MachineFunction &MF) const override;
32 bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
34 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
35 unsigned FIOperandNum,
36 RegScavenger *RS) const override;
38 /// \brief get the register class of the specified type to use in the
40 const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
42 unsigned getHWRegIndex(unsigned Reg) const override;
44 /// \brief Return the 'base' register class for this register.
45 /// e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR1 -> SReg_32, etc.
46 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
48 /// \returns true if this class contains only SGPR registers
49 bool isSGPRClass(const TargetRegisterClass *RC) const;
51 /// \returns true if this class contains VGPR registers.
52 bool hasVGPRs(const TargetRegisterClass *RC) const;
54 /// \returns A VGPR reg class with the same width as \p SRC
55 const TargetRegisterClass *getEquivalentVGPRClass(
56 const TargetRegisterClass *SRC) const;
58 /// \returns The register class that is used for a sub-register of \p RC for
59 /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
61 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
62 unsigned SubIdx) const;
64 /// \p Channel This is the register channel (e.g. a value from 0-16), not the
66 /// \returns The sub-register of Reg that is in Channel.
67 unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
68 unsigned Channel) const;
70 /// \returns True if operands defined with this register class can accept
71 /// a literal constant (i.e. any 32-bit immediate).
72 bool regClassCanUseLiteralConstant(int RCID) const;
74 /// \returns True if operands defined with this register class can accept
75 /// a literal constant (i.e. any 32-bit immediate).
76 bool regClassCanUseLiteralConstant(const TargetRegisterClass *RC) const;
78 /// \returns True if operands defined with this register class can accept
79 /// an inline constant. i.e. An integer value in the range (-16, 64) or
80 /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
81 bool regClassCanUseInlineConstant(int RCID) const;
83 /// \returns True if operands defined with this register class can accept
84 /// a literal constant. i.e. A value in the range (-16, 64).
85 bool regClassCanUseInlineConstant(const TargetRegisterClass *RC) const;
99 /// \brief Returns the physical register that \p Value is stored in.
100 unsigned getPreloadedValue(const MachineFunction &MF,
101 enum PreloadedValue Value) const;
103 unsigned findUnusedVGPR(const MachineRegisterInfo &MRI) const;
106 } // End namespace llvm