1 //===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI implementation of the TargetRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "SIRegisterInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "SIInstrInfo.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/RegisterScavenging.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/IR/LLVMContext.h"
28 SIRegisterInfo::SIRegisterInfo(const AMDGPUSubtarget &st)
29 : AMDGPURegisterInfo(st)
32 BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
33 BitVector Reserved(getNumRegs());
34 Reserved.set(AMDGPU::EXEC);
35 Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
36 Reserved.set(AMDGPU::FLAT_SCR);
38 // Reserve some VGPRs to use as temp registers in case we have to spill VGPRs
39 Reserved.set(AMDGPU::VGPR255);
40 Reserved.set(AMDGPU::VGPR254);
45 unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
46 MachineFunction &MF) const {
47 return RC->getNumRegs();
50 bool SIRegisterInfo::requiresRegisterScavenging(const MachineFunction &Fn) const {
51 return Fn.getFrameInfo()->hasStackObjects();
54 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
57 case AMDGPU::SI_SPILL_S512_SAVE:
58 case AMDGPU::SI_SPILL_S512_RESTORE:
59 case AMDGPU::SI_SPILL_V512_SAVE:
60 case AMDGPU::SI_SPILL_V512_RESTORE:
62 case AMDGPU::SI_SPILL_S256_SAVE:
63 case AMDGPU::SI_SPILL_S256_RESTORE:
64 case AMDGPU::SI_SPILL_V256_SAVE:
65 case AMDGPU::SI_SPILL_V256_RESTORE:
67 case AMDGPU::SI_SPILL_S128_SAVE:
68 case AMDGPU::SI_SPILL_S128_RESTORE:
69 case AMDGPU::SI_SPILL_V128_SAVE:
70 case AMDGPU::SI_SPILL_V128_RESTORE:
72 case AMDGPU::SI_SPILL_V96_SAVE:
73 case AMDGPU::SI_SPILL_V96_RESTORE:
75 case AMDGPU::SI_SPILL_S64_SAVE:
76 case AMDGPU::SI_SPILL_S64_RESTORE:
77 case AMDGPU::SI_SPILL_V64_SAVE:
78 case AMDGPU::SI_SPILL_V64_RESTORE:
80 case AMDGPU::SI_SPILL_S32_SAVE:
81 case AMDGPU::SI_SPILL_S32_RESTORE:
82 case AMDGPU::SI_SPILL_V32_SAVE:
83 case AMDGPU::SI_SPILL_V32_RESTORE:
85 default: llvm_unreachable("Invalid spill opcode");
89 void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
90 int SPAdj, unsigned FIOperandNum,
91 RegScavenger *RS) const {
92 MachineFunction *MF = MI->getParent()->getParent();
93 MachineBasicBlock *MBB = MI->getParent();
94 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
95 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
96 const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
97 DebugLoc DL = MI->getDebugLoc();
99 MachineOperand &FIOp = MI->getOperand(FIOperandNum);
100 int Index = MI->getOperand(FIOperandNum).getIndex();
102 switch (MI->getOpcode()) {
103 // SGPR register spill
104 case AMDGPU::SI_SPILL_S512_SAVE:
105 case AMDGPU::SI_SPILL_S256_SAVE:
106 case AMDGPU::SI_SPILL_S128_SAVE:
107 case AMDGPU::SI_SPILL_S64_SAVE:
108 case AMDGPU::SI_SPILL_S32_SAVE: {
109 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
111 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
112 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
113 &AMDGPU::SGPR_32RegClass, i);
114 struct SIMachineFunctionInfo::SpilledReg Spill =
115 MFI->getSpilledReg(MF, Index, i);
117 if (Spill.VGPR == AMDGPU::NoRegister) {
118 LLVMContext &Ctx = MF->getFunction()->getContext();
119 Ctx.emitError("Ran out of VGPRs for spilling SGPR");
122 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill.VGPR)
127 MI->eraseFromParent();
131 // SGPR register restore
132 case AMDGPU::SI_SPILL_S512_RESTORE:
133 case AMDGPU::SI_SPILL_S256_RESTORE:
134 case AMDGPU::SI_SPILL_S128_RESTORE:
135 case AMDGPU::SI_SPILL_S64_RESTORE:
136 case AMDGPU::SI_SPILL_S32_RESTORE: {
137 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
139 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
140 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
141 &AMDGPU::SGPR_32RegClass, i);
142 struct SIMachineFunctionInfo::SpilledReg Spill =
143 MFI->getSpilledReg(MF, Index, i);
145 if (Spill.VGPR == AMDGPU::NoRegister) {
146 LLVMContext &Ctx = MF->getFunction()->getContext();
147 Ctx.emitError("Ran out of VGPRs for spilling SGPR");
150 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), SubReg)
155 TII->insertNOPs(MI, 3);
156 MI->eraseFromParent();
160 // VGPR register spill
161 case AMDGPU::SI_SPILL_V512_SAVE:
162 case AMDGPU::SI_SPILL_V256_SAVE:
163 case AMDGPU::SI_SPILL_V128_SAVE:
164 case AMDGPU::SI_SPILL_V96_SAVE:
165 case AMDGPU::SI_SPILL_V64_SAVE:
166 case AMDGPU::SI_SPILL_V32_SAVE: {
167 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
168 unsigned SrcReg = MI->getOperand(0).getReg();
169 int64_t Offset = FrameInfo->getObjectOffset(Index);
170 unsigned Size = NumSubRegs * 4;
171 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
173 for (unsigned i = 0, e = NumSubRegs; i != e; ++i) {
174 unsigned SubReg = NumSubRegs > 1 ?
175 getPhysRegSubReg(SrcReg, &AMDGPU::VGPR_32RegClass, i) :
178 MFI->LDSWaveSpillSize = std::max((unsigned)Offset + 4, (unsigned)MFI->LDSWaveSpillSize);
180 unsigned AddrReg = TII->calculateLDSSpillAddress(*MBB, MI, RS, TmpReg,
183 if (AddrReg == AMDGPU::NoRegister) {
184 LLVMContext &Ctx = MF->getFunction()->getContext();
185 Ctx.emitError("Ran out of VGPRs for spilling VGPRS");
186 AddrReg = AMDGPU::VGPR0;
189 // Store the value in LDS
190 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::DS_WRITE_B32))
192 .addReg(AddrReg, RegState::Kill) // addr
193 .addReg(SubReg) // data0
194 .addImm(0); // offset
197 MI->eraseFromParent();
200 case AMDGPU::SI_SPILL_V32_RESTORE:
201 case AMDGPU::SI_SPILL_V64_RESTORE:
202 case AMDGPU::SI_SPILL_V128_RESTORE:
203 case AMDGPU::SI_SPILL_V256_RESTORE:
204 case AMDGPU::SI_SPILL_V512_RESTORE: {
205 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
206 unsigned DstReg = MI->getOperand(0).getReg();
207 int64_t Offset = FrameInfo->getObjectOffset(Index);
208 unsigned Size = NumSubRegs * 4;
209 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
211 // FIXME: We could use DS_READ_B64 here to optimize for larger registers.
212 for (unsigned i = 0, e = NumSubRegs; i != e; ++i) {
213 unsigned SubReg = NumSubRegs > 1 ?
214 getPhysRegSubReg(DstReg, &AMDGPU::VGPR_32RegClass, i) :
218 unsigned AddrReg = TII->calculateLDSSpillAddress(*MBB, MI, RS, TmpReg,
220 if (AddrReg == AMDGPU::NoRegister) {
221 LLVMContext &Ctx = MF->getFunction()->getContext();
222 Ctx.emitError("Ran out of VGPRs for spilling VGPRs");
223 AddrReg = AMDGPU::VGPR0;
226 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::DS_READ_B32), SubReg)
228 .addReg(AddrReg, RegState::Kill) // addr
231 MI->eraseFromParent();
236 int64_t Offset = FrameInfo->getObjectOffset(Index);
237 FIOp.ChangeToImmediate(Offset);
238 if (!TII->isImmOperandLegal(MI, FIOperandNum, FIOp)) {
239 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VReg_32RegClass, MI, SPAdj);
240 BuildMI(*MBB, MI, MI->getDebugLoc(),
241 TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
243 FIOp.ChangeToRegister(TmpReg, false);
249 const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
251 switch(VT.SimpleTy) {
253 case MVT::i32: return &AMDGPU::VReg_32RegClass;
257 unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
258 return getEncodingValue(Reg) & 0xff;
261 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
262 assert(!TargetRegisterInfo::isVirtualRegister(Reg));
264 const TargetRegisterClass *BaseClasses[] = {
265 &AMDGPU::VReg_32RegClass,
266 &AMDGPU::SReg_32RegClass,
267 &AMDGPU::VReg_64RegClass,
268 &AMDGPU::SReg_64RegClass,
269 &AMDGPU::VReg_96RegClass,
270 &AMDGPU::VReg_128RegClass,
271 &AMDGPU::SReg_128RegClass,
272 &AMDGPU::VReg_256RegClass,
273 &AMDGPU::SReg_256RegClass,
274 &AMDGPU::VReg_512RegClass
277 for (const TargetRegisterClass *BaseClass : BaseClasses) {
278 if (BaseClass->contains(Reg)) {
285 bool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) const {
289 return !hasVGPRs(RC);
292 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
293 return getCommonSubClass(&AMDGPU::VReg_32RegClass, RC) ||
294 getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
295 getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
296 getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
297 getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
298 getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
301 const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
302 const TargetRegisterClass *SRC) const {
305 } else if (SRC == &AMDGPU::SCCRegRegClass) {
306 return &AMDGPU::VCCRegRegClass;
307 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
308 return &AMDGPU::VReg_32RegClass;
309 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
310 return &AMDGPU::VReg_64RegClass;
311 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) {
312 return &AMDGPU::VReg_128RegClass;
313 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) {
314 return &AMDGPU::VReg_256RegClass;
315 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) {
316 return &AMDGPU::VReg_512RegClass;
321 const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
322 const TargetRegisterClass *RC, unsigned SubIdx) const {
323 if (SubIdx == AMDGPU::NoSubRegister)
326 // If this register has a sub-register, we can safely assume it is a 32-bit
327 // register, because all of SI's sub-registers are 32-bit.
328 if (isSGPRClass(RC)) {
329 return &AMDGPU::SGPR_32RegClass;
331 return &AMDGPU::VGPR_32RegClass;
335 unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
336 const TargetRegisterClass *SubRC,
337 unsigned Channel) const {
342 case 0: return AMDGPU::VCC_LO;
343 case 1: return AMDGPU::VCC_HI;
344 default: llvm_unreachable("Invalid SubIdx for VCC");
348 case AMDGPU::FLAT_SCR:
351 return AMDGPU::FLAT_SCR_LO;
353 return AMDGPU::FLAT_SCR_HI;
355 llvm_unreachable("Invalid SubIdx for FLAT_SCR");
362 return AMDGPU::EXEC_LO;
364 return AMDGPU::EXEC_HI;
366 llvm_unreachable("Invalid SubIdx for EXEC");
371 unsigned Index = getHWRegIndex(Reg);
372 return SubRC->getRegister(Index + Channel);
375 bool SIRegisterInfo::regClassCanUseLiteralConstant(int RCID) const {
377 default: return false;
378 case AMDGPU::SSrc_32RegClassID:
379 case AMDGPU::SSrc_64RegClassID:
380 case AMDGPU::VSrc_32RegClassID:
381 case AMDGPU::VSrc_64RegClassID:
386 bool SIRegisterInfo::regClassCanUseLiteralConstant(
387 const TargetRegisterClass *RC) const {
388 return regClassCanUseLiteralConstant(RC->getID());
391 bool SIRegisterInfo::regClassCanUseInlineConstant(int RCID) const {
392 if (regClassCanUseLiteralConstant(RCID))
396 default: return false;
397 case AMDGPU::VCSrc_32RegClassID:
398 case AMDGPU::VCSrc_64RegClassID:
403 bool SIRegisterInfo::regClassCanUseInlineConstant(
404 const TargetRegisterClass *RC) const {
405 return regClassCanUseInlineConstant(RC->getID());
409 unsigned SIRegisterInfo::getPreloadedValue(const MachineFunction &MF,
410 enum PreloadedValue Value) const {
412 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
414 case SIRegisterInfo::TGID_X:
415 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 0);
416 case SIRegisterInfo::TGID_Y:
417 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 1);
418 case SIRegisterInfo::TGID_Z:
419 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 2);
420 case SIRegisterInfo::SCRATCH_WAVE_OFFSET:
421 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 4);
422 case SIRegisterInfo::SCRATCH_PTR:
423 return AMDGPU::SGPR2_SGPR3;
424 case SIRegisterInfo::INPUT_PTR:
425 return AMDGPU::SGPR0_SGPR1;
426 case SIRegisterInfo::TIDIG_X:
427 return AMDGPU::VGPR0;
428 case SIRegisterInfo::TIDIG_Y:
429 return AMDGPU::VGPR1;
430 case SIRegisterInfo::TIDIG_Z:
431 return AMDGPU::VGPR2;
433 llvm_unreachable("unexpected preloaded value type");
436 /// \brief Returns a register that is not used at any point in the function.
437 /// If all registers are used, then this function will return
438 // AMDGPU::NoRegister.
439 unsigned SIRegisterInfo::findUnusedVGPR(const MachineRegisterInfo &MRI) const {
441 const TargetRegisterClass *RC = &AMDGPU::VGPR_32RegClass;
443 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
445 if (!MRI.isPhysRegUsed(*I))
448 return AMDGPU::NoRegister;