1 //===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This pass lowers the pseudo control flow instructions to real
12 /// machine instructions.
14 /// All control flow is handled using predicated instructions and
15 /// a predicate stack. Each Scalar ALU controls the operations of 64 Vector
16 /// ALUs. The Scalar ALU can update the predicate for any of the Vector ALUs
17 /// by writting to the 64-bit EXEC register (each bit corresponds to a
18 /// single vector ALU). Typically, for predicates, a vector ALU will write
19 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
20 /// Vector ALU) and then the ScalarALU will AND the VCC register with the
21 /// EXEC to update the predicates.
24 /// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2
25 /// %SGPR0 = SI_IF %VCC
26 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0
27 /// %SGPR0 = SI_ELSE %SGPR0
28 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR0
33 /// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
34 /// %SGPR0 = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
35 /// S_CBRANCH_EXECZ label0 // This instruction is an optional
36 /// // optimization which allows us to
37 /// // branch if all the bits of
39 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 // Do the IF block of the branch
42 /// %SGPR0 = S_OR_SAVEEXEC_B64 %EXEC // Restore the exec mask for the Then block
43 /// %EXEC = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
44 /// S_BRANCH_EXECZ label1 // Use our branch optimization
45 /// // instruction again.
46 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR // Do the THEN block
48 /// %EXEC = S_OR_B64 %EXEC, %SGPR0 // Re-enable saved exec mask bits
49 //===----------------------------------------------------------------------===//
52 #include "SIInstrInfo.h"
53 #include "SIMachineFunctionInfo.h"
54 #include "llvm/CodeGen/MachineFunction.h"
55 #include "llvm/CodeGen/MachineFunctionPass.h"
56 #include "llvm/CodeGen/MachineInstrBuilder.h"
57 #include "llvm/CodeGen/MachineRegisterInfo.h"
63 class SILowerControlFlowPass : public MachineFunctionPass {
66 static const unsigned SkipThreshold = 12;
69 const TargetRegisterInfo *TRI;
70 const SIInstrInfo *TII;
72 bool shouldSkip(MachineBasicBlock *From, MachineBasicBlock *To);
74 void Skip(MachineInstr &From, MachineOperand &To);
75 void SkipIfDead(MachineInstr &MI);
77 void If(MachineInstr &MI);
78 void Else(MachineInstr &MI);
79 void Break(MachineInstr &MI);
80 void IfBreak(MachineInstr &MI);
81 void ElseBreak(MachineInstr &MI);
82 void Loop(MachineInstr &MI);
83 void EndCf(MachineInstr &MI);
85 void Kill(MachineInstr &MI);
86 void Branch(MachineInstr &MI);
88 void LoadM0(MachineInstr &MI, MachineInstr *MovRel);
89 void IndirectSrc(MachineInstr &MI);
90 void IndirectDst(MachineInstr &MI);
93 SILowerControlFlowPass(TargetMachine &tm) :
94 MachineFunctionPass(ID), TRI(0), TII(0) { }
96 virtual bool runOnMachineFunction(MachineFunction &MF);
98 const char *getPassName() const {
99 return "SI Lower control flow instructions";
104 } // End anonymous namespace
106 char SILowerControlFlowPass::ID = 0;
108 FunctionPass *llvm::createSILowerControlFlowPass(TargetMachine &tm) {
109 return new SILowerControlFlowPass(tm);
112 bool SILowerControlFlowPass::shouldSkip(MachineBasicBlock *From,
113 MachineBasicBlock *To) {
115 unsigned NumInstr = 0;
117 for (MachineBasicBlock *MBB = From; MBB != To && !MBB->succ_empty();
118 MBB = *MBB->succ_begin()) {
120 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
121 NumInstr < SkipThreshold && I != E; ++I) {
123 if (I->isBundle() || !I->isBundled())
124 if (++NumInstr >= SkipThreshold)
132 void SILowerControlFlowPass::Skip(MachineInstr &From, MachineOperand &To) {
134 if (!shouldSkip(*From.getParent()->succ_begin(), To.getMBB()))
137 DebugLoc DL = From.getDebugLoc();
138 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
140 .addReg(AMDGPU::EXEC);
143 void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) {
145 MachineBasicBlock &MBB = *MI.getParent();
146 DebugLoc DL = MI.getDebugLoc();
148 if (MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType !=
150 !shouldSkip(&MBB, &MBB.getParent()->back()))
153 MachineBasicBlock::iterator Insert = &MI;
156 // If the exec mask is non-zero, skip the next two instructions
157 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
159 .addReg(AMDGPU::EXEC);
161 // Exec mask is zero: Export to NULL target...
162 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
164 .addImm(0x09) // V_008DFC_SQ_EXP_NULL
168 .addReg(AMDGPU::VGPR0)
169 .addReg(AMDGPU::VGPR0)
170 .addReg(AMDGPU::VGPR0)
171 .addReg(AMDGPU::VGPR0);
173 // ... and terminate wavefront
174 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
177 void SILowerControlFlowPass::If(MachineInstr &MI) {
178 MachineBasicBlock &MBB = *MI.getParent();
179 DebugLoc DL = MI.getDebugLoc();
180 unsigned Reg = MI.getOperand(0).getReg();
181 unsigned Vcc = MI.getOperand(1).getReg();
183 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
186 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
187 .addReg(AMDGPU::EXEC)
190 Skip(MI, MI.getOperand(2));
192 MI.eraseFromParent();
195 void SILowerControlFlowPass::Else(MachineInstr &MI) {
196 MachineBasicBlock &MBB = *MI.getParent();
197 DebugLoc DL = MI.getDebugLoc();
198 unsigned Dst = MI.getOperand(0).getReg();
199 unsigned Src = MI.getOperand(1).getReg();
201 BuildMI(MBB, MBB.getFirstNonPHI(), DL,
202 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
203 .addReg(Src); // Saved EXEC
205 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
206 .addReg(AMDGPU::EXEC)
209 Skip(MI, MI.getOperand(2));
211 MI.eraseFromParent();
214 void SILowerControlFlowPass::Break(MachineInstr &MI) {
215 MachineBasicBlock &MBB = *MI.getParent();
216 DebugLoc DL = MI.getDebugLoc();
218 unsigned Dst = MI.getOperand(0).getReg();
219 unsigned Src = MI.getOperand(1).getReg();
221 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
222 .addReg(AMDGPU::EXEC)
225 MI.eraseFromParent();
228 void SILowerControlFlowPass::IfBreak(MachineInstr &MI) {
229 MachineBasicBlock &MBB = *MI.getParent();
230 DebugLoc DL = MI.getDebugLoc();
232 unsigned Dst = MI.getOperand(0).getReg();
233 unsigned Vcc = MI.getOperand(1).getReg();
234 unsigned Src = MI.getOperand(2).getReg();
236 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
240 MI.eraseFromParent();
243 void SILowerControlFlowPass::ElseBreak(MachineInstr &MI) {
244 MachineBasicBlock &MBB = *MI.getParent();
245 DebugLoc DL = MI.getDebugLoc();
247 unsigned Dst = MI.getOperand(0).getReg();
248 unsigned Saved = MI.getOperand(1).getReg();
249 unsigned Src = MI.getOperand(2).getReg();
251 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
255 MI.eraseFromParent();
258 void SILowerControlFlowPass::Loop(MachineInstr &MI) {
259 MachineBasicBlock &MBB = *MI.getParent();
260 DebugLoc DL = MI.getDebugLoc();
261 unsigned Src = MI.getOperand(0).getReg();
263 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
264 .addReg(AMDGPU::EXEC)
267 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
268 .addOperand(MI.getOperand(1))
269 .addReg(AMDGPU::EXEC);
271 MI.eraseFromParent();
274 void SILowerControlFlowPass::EndCf(MachineInstr &MI) {
275 MachineBasicBlock &MBB = *MI.getParent();
276 DebugLoc DL = MI.getDebugLoc();
277 unsigned Reg = MI.getOperand(0).getReg();
279 BuildMI(MBB, MBB.getFirstNonPHI(), DL,
280 TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC)
281 .addReg(AMDGPU::EXEC)
284 MI.eraseFromParent();
287 void SILowerControlFlowPass::Branch(MachineInstr &MI) {
288 if (MI.getOperand(0).getMBB() == MI.getParent()->getNextNode())
289 MI.eraseFromParent();
291 // If these aren't equal, this is probably an infinite loop.
294 void SILowerControlFlowPass::Kill(MachineInstr &MI) {
295 MachineBasicBlock &MBB = *MI.getParent();
296 DebugLoc DL = MI.getDebugLoc();
298 // Kill is only allowed in pixel / geometry shaders
299 assert(MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
301 MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
302 ShaderType::GEOMETRY);
304 // Clear this pixel from the exec mask if the operand is negative
305 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
307 .addOperand(MI.getOperand(0));
309 MI.eraseFromParent();
312 void SILowerControlFlowPass::LoadM0(MachineInstr &MI, MachineInstr *MovRel) {
314 MachineBasicBlock &MBB = *MI.getParent();
315 DebugLoc DL = MI.getDebugLoc();
316 MachineBasicBlock::iterator I = MI;
318 unsigned Save = MI.getOperand(1).getReg();
319 unsigned Idx = MI.getOperand(3).getReg();
321 if (AMDGPU::SReg_32RegClass.contains(Idx)) {
322 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
324 MBB.insert(I, MovRel);
325 MI.eraseFromParent();
329 assert(AMDGPU::SReg_64RegClass.contains(Save));
330 assert(AMDGPU::VReg_32RegClass.contains(Idx));
332 // Save the EXEC mask
333 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), Save)
334 .addReg(AMDGPU::EXEC);
336 // Read the next variant into VCC (lower 32 bits) <- also loop target
337 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32_e32), AMDGPU::VCC)
340 // Move index from VCC into M0
341 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
342 .addReg(AMDGPU::VCC);
344 // Compare the just read M0 value to all possible Idx values
345 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e32), AMDGPU::VCC)
349 // Update EXEC, save the original EXEC value to VCC
350 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC)
351 .addReg(AMDGPU::VCC);
353 // Do the actual move
354 MBB.insert(I, MovRel);
356 // Update EXEC, switch all done bits to 0 and all todo bits to 1
357 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
358 .addReg(AMDGPU::EXEC)
359 .addReg(AMDGPU::VCC);
361 // Loop back to V_READFIRSTLANE_B32 if there are still variants to cover
362 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
364 .addReg(AMDGPU::EXEC);
367 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
370 MI.eraseFromParent();
373 void SILowerControlFlowPass::IndirectSrc(MachineInstr &MI) {
375 MachineBasicBlock &MBB = *MI.getParent();
376 DebugLoc DL = MI.getDebugLoc();
378 unsigned Dst = MI.getOperand(0).getReg();
379 unsigned Vec = MI.getOperand(2).getReg();
380 unsigned Off = MI.getOperand(4).getImm();
381 unsigned SubReg = TRI->getSubReg(Vec, AMDGPU::sub0);
385 MachineInstr *MovRel =
386 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
387 .addReg(SubReg + Off)
388 .addReg(AMDGPU::M0, RegState::Implicit)
389 .addReg(Vec, RegState::Implicit);
394 void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) {
396 MachineBasicBlock &MBB = *MI.getParent();
397 DebugLoc DL = MI.getDebugLoc();
399 unsigned Dst = MI.getOperand(0).getReg();
400 unsigned Off = MI.getOperand(4).getImm();
401 unsigned Val = MI.getOperand(5).getReg();
402 unsigned SubReg = TRI->getSubReg(Dst, AMDGPU::sub0);
406 MachineInstr *MovRel =
407 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32))
408 .addReg(SubReg + Off, RegState::Define)
410 .addReg(AMDGPU::M0, RegState::Implicit)
411 .addReg(Dst, RegState::Implicit);
416 bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
417 TII = static_cast<const SIInstrInfo*>(MF.getTarget().getInstrInfo());
418 TRI = MF.getTarget().getRegisterInfo();
419 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
421 bool HaveKill = false;
423 bool NeedWQM = false;
426 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
429 MachineBasicBlock &MBB = *BI;
430 for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
431 I != MBB.end(); I = Next) {
433 Next = llvm::next(I);
434 MachineInstr &MI = *I;
435 if (TII->isDS(MI.getOpcode())) {
440 switch (MI.getOpcode()) {
447 case AMDGPU::SI_ELSE:
451 case AMDGPU::SI_BREAK:
455 case AMDGPU::SI_IF_BREAK:
459 case AMDGPU::SI_ELSE_BREAK:
463 case AMDGPU::SI_LOOP:
468 case AMDGPU::SI_END_CF:
469 if (--Depth == 0 && HaveKill) {
476 case AMDGPU::SI_KILL:
484 case AMDGPU::S_BRANCH:
488 case AMDGPU::SI_INDIRECT_SRC:
492 case AMDGPU::SI_INDIRECT_DST_V1:
493 case AMDGPU::SI_INDIRECT_DST_V2:
494 case AMDGPU::SI_INDIRECT_DST_V4:
495 case AMDGPU::SI_INDIRECT_DST_V8:
496 case AMDGPU::SI_INDIRECT_DST_V16:
500 case AMDGPU::V_INTERP_P1_F32:
501 case AMDGPU::V_INTERP_P2_F32:
502 case AMDGPU::V_INTERP_MOV_F32:
511 MachineBasicBlock &MBB = MF.front();
512 // Initialize M0 to a value that won't cause LDS access to be discarded
513 // due to offset clamping
514 BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_MOV_B32),
515 AMDGPU::M0).addImm(0xffffffff);
518 if (NeedWQM && MFI->ShaderType == ShaderType::PIXEL) {
519 MachineBasicBlock &MBB = MF.front();
520 BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64),
521 AMDGPU::EXEC).addReg(AMDGPU::EXEC);