1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file was originally auto-generated from a GPU register header file and
10 // all the instruction definitions were originally commented out. Instructions
11 // that are not yet supported remain commented out.
12 //===----------------------------------------------------------------------===//
19 def INTERP : InterpSlots;
21 def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
25 def SendMsgImm : Operand<i32> {
26 let PrintMethod = "printSendMsg";
29 def isGCN : Predicate<"Subtarget.getGeneration() "
30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
31 def isSICI : Predicate<
32 "Subtarget.getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
33 "Subtarget.getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
35 def isCI : Predicate<"Subtarget.getGeneration() "
36 ">= AMDGPUSubtarget::SEA_ISLANDS">;
37 def isVI : Predicate <
38 "Subtarget.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS"
41 def HasFlatAddressSpace : Predicate<"Subtarget.hasFlatAddressSpace()">;
43 def SWaitMatchClass : AsmOperandClass {
44 let Name = "SWaitCnt";
45 let RenderMethod = "addImmOperands";
46 let ParserMethod = "parseSWaitCntOps";
49 def WAIT_FLAG : InstFlag<"printWaitFlag"> {
50 let ParserMatchClass = SWaitMatchClass;
53 let SubtargetPredicate = isGCN in {
55 //===----------------------------------------------------------------------===//
57 //===----------------------------------------------------------------------===//
61 //===----------------------------------------------------------------------===//
63 //===----------------------------------------------------------------------===//
67 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit
68 // SMRD instructions, because the SGPR_32 register class does not include M0
69 // and writing to M0 from an SMRD instruction will hang the GPU.
70 defm S_LOAD_DWORD : SMRD_Helper <0x00, "s_load_dword", SReg_64, SGPR_32>;
71 defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "s_load_dwordx2", SReg_64, SReg_64>;
72 defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "s_load_dwordx4", SReg_64, SReg_128>;
73 defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "s_load_dwordx8", SReg_64, SReg_256>;
74 defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "s_load_dwordx16", SReg_64, SReg_512>;
76 defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
77 0x08, "s_buffer_load_dword", SReg_128, SGPR_32
80 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
81 0x09, "s_buffer_load_dwordx2", SReg_128, SReg_64
84 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
85 0x0a, "s_buffer_load_dwordx4", SReg_128, SReg_128
88 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
89 0x0b, "s_buffer_load_dwordx8", SReg_128, SReg_256
92 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
93 0x0c, "s_buffer_load_dwordx16", SReg_128, SReg_512
98 //def S_MEMTIME : SMRD_ <0x0000001e, "s_memtime", []>;
99 //def S_DCACHE_INV : SMRD_ <0x0000001f, "s_dcache_inv", []>;
101 //===----------------------------------------------------------------------===//
103 //===----------------------------------------------------------------------===//
105 let isMoveImm = 1 in {
106 let isReMaterializable = 1 in {
107 defm S_MOV_B32 : SOP1_32 <sop1<0x03, 0x00>, "s_mov_b32", []>;
108 defm S_MOV_B64 : SOP1_64 <sop1<0x04, 0x01>, "s_mov_b64", []>;
109 } // let isRematerializeable = 1
111 let Uses = [SCC] in {
112 defm S_CMOV_B32 : SOP1_32 <sop1<0x05, 0x02>, "s_cmov_b32", []>;
113 defm S_CMOV_B64 : SOP1_64 <sop1<0x06, 0x03>, "s_cmov_b64", []>;
114 } // End Uses = [SCC]
115 } // End isMoveImm = 1
117 let Defs = [SCC] in {
118 defm S_NOT_B32 : SOP1_32 <sop1<0x07, 0x04>, "s_not_b32",
119 [(set i32:$dst, (not i32:$src0))]
122 defm S_NOT_B64 : SOP1_64 <sop1<0x08, 0x05>, "s_not_b64",
123 [(set i64:$dst, (not i64:$src0))]
125 defm S_WQM_B32 : SOP1_32 <sop1<0x09, 0x06>, "s_wqm_b32", []>;
126 defm S_WQM_B64 : SOP1_64 <sop1<0x0a, 0x07>, "s_wqm_b64", []>;
127 } // End Defs = [SCC]
130 defm S_BREV_B32 : SOP1_32 <sop1<0x0b, 0x08>, "s_brev_b32",
131 [(set i32:$dst, (AMDGPUbrev i32:$src0))]
133 defm S_BREV_B64 : SOP1_64 <sop1<0x0c, 0x09>, "s_brev_b64", []>;
135 let Defs = [SCC] in {
136 //defm S_BCNT0_I32_B32 : SOP1_BCNT0 <sop1<0x0d, 0x0a>, "s_bcnt0_i32_b32", []>;
137 //defm S_BCNT0_I32_B64 : SOP1_BCNT0 <sop1<0x0e, 0x0b>, "s_bcnt0_i32_b64", []>;
138 defm S_BCNT1_I32_B32 : SOP1_32 <sop1<0x0f, 0x0c>, "s_bcnt1_i32_b32",
139 [(set i32:$dst, (ctpop i32:$src0))]
141 defm S_BCNT1_I32_B64 : SOP1_32_64 <sop1<0x10, 0x0d>, "s_bcnt1_i32_b64", []>;
142 } // End Defs = [SCC]
144 //defm S_FF0_I32_B32 : SOP1_32 <sop1<0x11, 0x0e>, "s_ff0_i32_b32", []>;
145 //defm S_FF0_I32_B64 : SOP1_FF0 <sop1<0x12, 0x0f>, "s_ff0_i32_b64", []>;
146 defm S_FF1_I32_B32 : SOP1_32 <sop1<0x13, 0x10>, "s_ff1_i32_b32",
147 [(set i32:$dst, (cttz_zero_undef i32:$src0))]
149 ////defm S_FF1_I32_B64 : SOP1_FF1 <sop1<0x14, 0x11>, "s_ff1_i32_b64", []>;
151 defm S_FLBIT_I32_B32 : SOP1_32 <sop1<0x15, 0x12>, "s_flbit_i32_b32",
152 [(set i32:$dst, (ctlz_zero_undef i32:$src0))]
155 //defm S_FLBIT_I32_B64 : SOP1_32 <sop1<0x16, 0x13>, "s_flbit_i32_b64", []>;
156 defm S_FLBIT_I32 : SOP1_32 <sop1<0x17, 0x14>, "s_flbit_i32", []>;
157 //defm S_FLBIT_I32_I64 : SOP1_32 <sop1<0x18, 0x15>, "s_flbit_i32_i64", []>;
158 defm S_SEXT_I32_I8 : SOP1_32 <sop1<0x19, 0x16>, "s_sext_i32_i8",
159 [(set i32:$dst, (sext_inreg i32:$src0, i8))]
161 defm S_SEXT_I32_I16 : SOP1_32 <sop1<0x1a, 0x17>, "s_sext_i32_i16",
162 [(set i32:$dst, (sext_inreg i32:$src0, i16))]
165 ////defm S_BITSET0_B32 : SOP1_BITSET0 <sop1<0x1b, 0x18>, "s_bitset0_b32", []>;
166 ////defm S_BITSET0_B64 : SOP1_BITSET0 <sop1<0x1c, 0x19>, "s_bitset0_b64", []>;
167 ////defm S_BITSET1_B32 : SOP1_BITSET1 <sop1<0x1d, 0x1a>, "s_bitset1_b32", []>;
168 ////defm S_BITSET1_B64 : SOP1_BITSET1 <sop1<0x1e, 0x1b>, "s_bitset1_b64", []>;
169 defm S_GETPC_B64 : SOP1_64_0 <sop1<0x1f, 0x1c>, "s_getpc_b64", []>;
170 defm S_SETPC_B64 : SOP1_64 <sop1<0x20, 0x1d>, "s_setpc_b64", []>;
171 defm S_SWAPPC_B64 : SOP1_64 <sop1<0x21, 0x1e>, "s_swappc_b64", []>;
172 defm S_RFE_B64 : SOP1_64 <sop1<0x22, 0x1f>, "s_rfe_b64", []>;
174 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] in {
176 defm S_AND_SAVEEXEC_B64 : SOP1_64 <sop1<0x24, 0x20>, "s_and_saveexec_b64", []>;
177 defm S_OR_SAVEEXEC_B64 : SOP1_64 <sop1<0x25, 0x21>, "s_or_saveexec_b64", []>;
178 defm S_XOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x26, 0x22>, "s_xor_saveexec_b64", []>;
179 defm S_ANDN2_SAVEEXEC_B64 : SOP1_64 <sop1<0x27, 0x23>, "s_andn2_saveexec_b64", []>;
180 defm S_ORN2_SAVEEXEC_B64 : SOP1_64 <sop1<0x28, 0x24>, "s_orn2_saveexec_b64", []>;
181 defm S_NAND_SAVEEXEC_B64 : SOP1_64 <sop1<0x29, 0x25>, "s_nand_saveexec_b64", []>;
182 defm S_NOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x2a, 0x26>, "s_nor_saveexec_b64", []>;
183 defm S_XNOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x2b, 0x27>, "s_xnor_saveexec_b64", []>;
185 } // End hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC]
187 defm S_QUADMASK_B32 : SOP1_32 <sop1<0x2c, 0x28>, "s_quadmask_b32", []>;
188 defm S_QUADMASK_B64 : SOP1_64 <sop1<0x2d, 0x29>, "s_quadmask_b64", []>;
189 defm S_MOVRELS_B32 : SOP1_32 <sop1<0x2e, 0x2a>, "s_movrels_b32", []>;
190 defm S_MOVRELS_B64 : SOP1_64 <sop1<0x2f, 0x2b>, "s_movrels_b64", []>;
191 defm S_MOVRELD_B32 : SOP1_32 <sop1<0x30, 0x2c>, "s_movreld_b32", []>;
192 defm S_MOVRELD_B64 : SOP1_64 <sop1<0x31, 0x2d>, "s_movreld_b64", []>;
193 //defm S_CBRANCH_JOIN : SOP1_ <sop1<0x32, 0x2e>, "s_cbranch_join", []>;
194 defm S_MOV_REGRD_B32 : SOP1_32 <sop1<0x33, 0x2f>, "s_mov_regrd_b32", []>;
195 let Defs = [SCC] in {
196 defm S_ABS_I32 : SOP1_32 <sop1<0x34, 0x30>, "s_abs_i32", []>;
197 } // End Defs = [SCC]
198 defm S_MOV_FED_B32 : SOP1_32 <sop1<0x35, 0x31>, "s_mov_fed_b32", []>;
200 //===----------------------------------------------------------------------===//
202 //===----------------------------------------------------------------------===//
204 let Defs = [SCC] in { // Carry out goes to SCC
205 let isCommutable = 1 in {
206 defm S_ADD_U32 : SOP2_32 <sop2<0x00>, "s_add_u32", []>;
207 defm S_ADD_I32 : SOP2_32 <sop2<0x02>, "s_add_i32",
208 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))]
210 } // End isCommutable = 1
212 defm S_SUB_U32 : SOP2_32 <sop2<0x01>, "s_sub_u32", []>;
213 defm S_SUB_I32 : SOP2_32 <sop2<0x03>, "s_sub_i32",
214 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))]
217 let Uses = [SCC] in { // Carry in comes from SCC
218 let isCommutable = 1 in {
219 defm S_ADDC_U32 : SOP2_32 <sop2<0x04>, "s_addc_u32",
220 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
221 } // End isCommutable = 1
223 defm S_SUBB_U32 : SOP2_32 <sop2<0x05>, "s_subb_u32",
224 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
225 } // End Uses = [SCC]
227 defm S_MIN_I32 : SOP2_32 <sop2<0x06>, "s_min_i32",
228 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]
230 defm S_MIN_U32 : SOP2_32 <sop2<0x07>, "s_min_u32",
231 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]
233 defm S_MAX_I32 : SOP2_32 <sop2<0x08>, "s_max_i32",
234 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]
236 defm S_MAX_U32 : SOP2_32 <sop2<0x09>, "s_max_u32",
237 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]
239 } // End Defs = [SCC]
241 defm S_CSELECT_B32 : SOP2_SELECT_32 <sop2<0x0a>, "s_cselect_b32", []>;
243 let Uses = [SCC] in {
244 defm S_CSELECT_B64 : SOP2_64 <sop2<0x0b>, "s_cselect_b64", []>;
245 } // End Uses = [SCC]
247 let Defs = [SCC] in {
248 defm S_AND_B32 : SOP2_32 <sop2<0x0e, 0x0c>, "s_and_b32",
249 [(set i32:$dst, (and i32:$src0, i32:$src1))]
252 defm S_AND_B64 : SOP2_64 <sop2<0x0f, 0x0d>, "s_and_b64",
253 [(set i64:$dst, (and i64:$src0, i64:$src1))]
256 defm S_OR_B32 : SOP2_32 <sop2<0x10, 0x0e>, "s_or_b32",
257 [(set i32:$dst, (or i32:$src0, i32:$src1))]
260 defm S_OR_B64 : SOP2_64 <sop2<0x11, 0x0f>, "s_or_b64",
261 [(set i64:$dst, (or i64:$src0, i64:$src1))]
264 defm S_XOR_B32 : SOP2_32 <sop2<0x12, 0x10>, "s_xor_b32",
265 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
268 defm S_XOR_B64 : SOP2_64 <sop2<0x13, 0x11>, "s_xor_b64",
269 [(set i64:$dst, (xor i64:$src0, i64:$src1))]
271 defm S_ANDN2_B32 : SOP2_32 <sop2<0x14, 0x12>, "s_andn2_b32", []>;
272 defm S_ANDN2_B64 : SOP2_64 <sop2<0x15, 0x13>, "s_andn2_b64", []>;
273 defm S_ORN2_B32 : SOP2_32 <sop2<0x16, 0x14>, "s_orn2_b32", []>;
274 defm S_ORN2_B64 : SOP2_64 <sop2<0x17, 0x15>, "s_orn2_b64", []>;
275 defm S_NAND_B32 : SOP2_32 <sop2<0x18, 0x16>, "s_nand_b32", []>;
276 defm S_NAND_B64 : SOP2_64 <sop2<0x19, 0x17>, "s_nand_b64", []>;
277 defm S_NOR_B32 : SOP2_32 <sop2<0x1a, 0x18>, "s_nor_b32", []>;
278 defm S_NOR_B64 : SOP2_64 <sop2<0x1b, 0x19>, "s_nor_b64", []>;
279 defm S_XNOR_B32 : SOP2_32 <sop2<0x1c, 0x1a>, "s_xnor_b32", []>;
280 defm S_XNOR_B64 : SOP2_64 <sop2<0x1d, 0x1b>, "s_xnor_b64", []>;
281 } // End Defs = [SCC]
283 // Use added complexity so these patterns are preferred to the VALU patterns.
284 let AddedComplexity = 1 in {
285 let Defs = [SCC] in {
287 defm S_LSHL_B32 : SOP2_32 <sop2<0x1e, 0x1c>, "s_lshl_b32",
288 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
290 defm S_LSHL_B64 : SOP2_64_32 <sop2<0x1f, 0x1d>, "s_lshl_b64",
291 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
293 defm S_LSHR_B32 : SOP2_32 <sop2<0x20, 0x1e>, "s_lshr_b32",
294 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
296 defm S_LSHR_B64 : SOP2_64_32 <sop2<0x21, 0x1f>, "s_lshr_b64",
297 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
299 defm S_ASHR_I32 : SOP2_32 <sop2<0x22, 0x20>, "s_ashr_i32",
300 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
302 defm S_ASHR_I64 : SOP2_64_32 <sop2<0x23, 0x21>, "s_ashr_i64",
303 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
305 } // End Defs = [SCC]
307 defm S_BFM_B32 : SOP2_32 <sop2<0x24, 0x22>, "s_bfm_b32", []>;
308 defm S_BFM_B64 : SOP2_64 <sop2<0x25, 0x23>, "s_bfm_b64", []>;
309 defm S_MUL_I32 : SOP2_32 <sop2<0x26, 0x24>, "s_mul_i32",
310 [(set i32:$dst, (mul i32:$src0, i32:$src1))]
313 } // End AddedComplexity = 1
315 let Defs = [SCC] in {
316 defm S_BFE_U32 : SOP2_32 <sop2<0x27, 0x25>, "s_bfe_u32", []>;
317 defm S_BFE_I32 : SOP2_32 <sop2<0x28, 0x26>, "s_bfe_i32", []>;
318 defm S_BFE_U64 : SOP2_64 <sop2<0x29, 0x27>, "s_bfe_u64", []>;
319 defm S_BFE_I64 : SOP2_64_32 <sop2<0x2a, 0x28>, "s_bfe_i64", []>;
320 } // End Defs = [SCC]
322 //defm S_CBRANCH_G_FORK : SOP2_ <sop2<0x2b, 0x29>, "s_cbranch_g_fork", []>;
323 let Defs = [SCC] in {
324 defm S_ABSDIFF_I32 : SOP2_32 <sop2<0x2c, 0x2a>, "s_absdiff_i32", []>;
325 } // End Defs = [SCC]
327 //===----------------------------------------------------------------------===//
329 //===----------------------------------------------------------------------===//
331 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "s_cmp_eq_i32">;
332 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "s_cmp_lg_i32">;
333 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "s_cmp_gt_i32">;
334 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "s_cmp_ge_i32">;
335 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "s_cmp_lt_i32">;
336 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "s_cmp_le_i32">;
337 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "s_cmp_eq_u32">;
338 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "s_cmp_lg_u32">;
339 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "s_cmp_gt_u32">;
340 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "s_cmp_ge_u32">;
341 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "s_cmp_lt_u32">;
342 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "s_cmp_le_u32">;
343 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "s_bitcmp0_b32", []>;
344 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "s_bitcmp1_b32", []>;
345 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "s_bitcmp0_b64", []>;
346 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "s_bitcmp1_b64", []>;
347 //def S_SETVSKIP : SOPC_ <0x00000010, "s_setvskip", []>;
349 //===----------------------------------------------------------------------===//
351 //===----------------------------------------------------------------------===//
353 let isReMaterializable = 1 in {
354 defm S_MOVK_I32 : SOPK_32 <sopk<0x00>, "s_movk_i32", []>;
355 } // End isReMaterializable = 1
356 let Uses = [SCC] in {
357 defm S_CMOVK_I32 : SOPK_32 <sopk<0x02, 0x01>, "s_cmovk_i32", []>;
360 let isCompare = 1 in {
363 This instruction is disabled for now until we can figure out how to teach
364 the instruction selector to correctly use the S_CMP* vs V_CMP*
367 When this instruction is enabled the code generator sometimes produces this
370 SCC = S_CMPK_EQ_I32 SGPR0, imm
372 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
374 defm S_CMPK_EQ_I32 : SOPK_SCC <sopk<0x03, 0x02>, "s_cmpk_eq_i32",
375 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
379 defm S_CMPK_LG_I32 : SOPK_SCC <sopk<0x04, 0x03>, "s_cmpk_lg_i32", []>;
380 defm S_CMPK_GT_I32 : SOPK_SCC <sopk<0x05, 0x04>, "s_cmpk_gt_i32", []>;
381 defm S_CMPK_GE_I32 : SOPK_SCC <sopk<0x06, 0x05>, "s_cmpk_ge_i32", []>;
382 defm S_CMPK_LT_I32 : SOPK_SCC <sopk<0x07, 0x06>, "s_cmpk_lt_i32", []>;
383 defm S_CMPK_LE_I32 : SOPK_SCC <sopk<0x08, 0x07>, "s_cmpk_le_i32", []>;
384 defm S_CMPK_EQ_U32 : SOPK_SCC <sopk<0x09, 0x08>, "s_cmpk_eq_u32", []>;
385 defm S_CMPK_LG_U32 : SOPK_SCC <sopk<0x0a, 0x09>, "s_cmpk_lg_u32", []>;
386 defm S_CMPK_GT_U32 : SOPK_SCC <sopk<0x0b, 0x0a>, "s_cmpk_gt_u32", []>;
387 defm S_CMPK_GE_U32 : SOPK_SCC <sopk<0x0c, 0x0b>, "s_cmpk_ge_u32", []>;
388 defm S_CMPK_LT_U32 : SOPK_SCC <sopk<0x0d, 0x0c>, "s_cmpk_lt_u32", []>;
389 defm S_CMPK_LE_U32 : SOPK_SCC <sopk<0x0e, 0x0d>, "s_cmpk_le_u32", []>;
390 } // End isCompare = 1
392 let isCommutable = 1 in {
393 let Defs = [SCC], isCommutable = 1 in {
394 defm S_ADDK_I32 : SOPK_32 <sopk<0x0f, 0x0e>, "s_addk_i32", []>;
396 defm S_MULK_I32 : SOPK_32 <sopk<0x10, 0x0f>, "s_mulk_i32", []>;
399 //defm S_CBRANCH_I_FORK : SOPK_ <sopk<0x11, 0x10>, "s_cbranch_i_fork", []>;
400 defm S_GETREG_B32 : SOPK_32 <sopk<0x12, 0x11>, "s_getreg_b32", []>;
401 defm S_SETREG_B32 : SOPK_32 <sopk<0x13, 0x12>, "s_setreg_b32", []>;
402 defm S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32", []>;
403 //defm S_SETREG_IMM32_B32 : SOPK_32 <sopk<0x15, 0x14>, "s_setreg_imm32_b32", []>;
405 //===----------------------------------------------------------------------===//
407 //===----------------------------------------------------------------------===//
409 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;
411 let isTerminator = 1 in {
413 def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm",
420 let isBranch = 1 in {
421 def S_BRANCH : SOPP <
422 0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16",
427 let DisableEncoding = "$scc" in {
428 def S_CBRANCH_SCC0 : SOPP <
429 0x00000004, (ins sopp_brtarget:$simm16, SCCReg:$scc),
430 "s_cbranch_scc0 $simm16"
432 def S_CBRANCH_SCC1 : SOPP <
433 0x00000005, (ins sopp_brtarget:$simm16, SCCReg:$scc),
434 "s_cbranch_scc1 $simm16"
436 } // End DisableEncoding = "$scc"
438 def S_CBRANCH_VCCZ : SOPP <
439 0x00000006, (ins sopp_brtarget:$simm16, VCCReg:$vcc),
440 "s_cbranch_vccz $simm16"
442 def S_CBRANCH_VCCNZ : SOPP <
443 0x00000007, (ins sopp_brtarget:$simm16, VCCReg:$vcc),
444 "s_cbranch_vccnz $simm16"
447 let DisableEncoding = "$exec" in {
448 def S_CBRANCH_EXECZ : SOPP <
449 0x00000008, (ins sopp_brtarget:$simm16, EXECReg:$exec),
450 "s_cbranch_execz $simm16"
452 def S_CBRANCH_EXECNZ : SOPP <
453 0x00000009, (ins sopp_brtarget:$simm16, EXECReg:$exec),
454 "s_cbranch_execnz $simm16"
456 } // End DisableEncoding = "$exec"
459 } // End isBranch = 1
460 } // End isTerminator = 1
462 let hasSideEffects = 1 in {
463 def S_BARRIER : SOPP <0x0000000a, (ins), "s_barrier",
464 [(int_AMDGPU_barrier_local)]
473 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16">;
474 def S_SETHALT : SOPP <0x0000000d, (ins i16imm:$simm16), "s_sethalt $simm16">;
475 def S_SLEEP : SOPP <0x0000000e, (ins i16imm:$simm16), "s_sleep $simm16">;
476 def S_SETPRIO : SOPP <0x0000000f, (ins i16imm:$sim16), "s_setprio $sim16">;
478 let Uses = [EXEC] in {
479 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "s_sendmsg $simm16",
480 [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
482 let DisableEncoding = "$m0";
484 } // End Uses = [EXEC]
486 def S_SENDMSGHALT : SOPP <0x00000011, (ins i16imm:$simm16), "s_sendmsghalt $simm16">;
487 def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16">;
488 def S_ICACHE_INV : SOPP <0x00000013, (ins), "s_icache_inv"> {
491 def S_INCPERFLEVEL : SOPP <0x00000014, (ins i16imm:$simm16), "s_incperflevel $simm16">;
492 def S_DECPERFLEVEL : SOPP <0x00000015, (ins i16imm:$simm16), "s_decperflevel $simm16">;
493 def S_TTRACEDATA : SOPP <0x00000016, (ins), "s_ttracedata"> {
496 } // End hasSideEffects
498 //===----------------------------------------------------------------------===//
500 //===----------------------------------------------------------------------===//
502 let isCompare = 1 in {
504 defm V_CMP_F_F32 : VOPC_F32 <vopc<0x0, 0x40>, "v_cmp_f_f32">;
505 defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1, 0x41>, "v_cmp_lt_f32", COND_OLT>;
506 defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2, 0x42>, "v_cmp_eq_f32", COND_OEQ>;
507 defm V_CMP_LE_F32 : VOPC_F32 <vopc<0x3, 0x43>, "v_cmp_le_f32", COND_OLE>;
508 defm V_CMP_GT_F32 : VOPC_F32 <vopc<0x4, 0x44>, "v_cmp_gt_f32", COND_OGT>;
509 defm V_CMP_LG_F32 : VOPC_F32 <vopc<0x5, 0x45>, "v_cmp_lg_f32", COND_ONE>;
510 defm V_CMP_GE_F32 : VOPC_F32 <vopc<0x6, 0x46>, "v_cmp_ge_f32", COND_OGE>;
511 defm V_CMP_O_F32 : VOPC_F32 <vopc<0x7, 0x47>, "v_cmp_o_f32", COND_O>;
512 defm V_CMP_U_F32 : VOPC_F32 <vopc<0x8, 0x48>, "v_cmp_u_f32", COND_UO>;
513 defm V_CMP_NGE_F32 : VOPC_F32 <vopc<0x9, 0x49>, "v_cmp_nge_f32", COND_ULT>;
514 defm V_CMP_NLG_F32 : VOPC_F32 <vopc<0xa, 0x4a>, "v_cmp_nlg_f32", COND_UEQ>;
515 defm V_CMP_NGT_F32 : VOPC_F32 <vopc<0xb, 0x4b>, "v_cmp_ngt_f32", COND_ULE>;
516 defm V_CMP_NLE_F32 : VOPC_F32 <vopc<0xc, 0x4c>, "v_cmp_nle_f32", COND_UGT>;
517 defm V_CMP_NEQ_F32 : VOPC_F32 <vopc<0xd, 0x4d>, "v_cmp_neq_f32", COND_UNE>;
518 defm V_CMP_NLT_F32 : VOPC_F32 <vopc<0xe, 0x4e>, "v_cmp_nlt_f32", COND_UGE>;
519 defm V_CMP_TRU_F32 : VOPC_F32 <vopc<0xf, 0x4f>, "v_cmp_tru_f32">;
521 let hasSideEffects = 1 in {
523 defm V_CMPX_F_F32 : VOPCX_F32 <vopc<0x10, 0x50>, "v_cmpx_f_f32">;
524 defm V_CMPX_LT_F32 : VOPCX_F32 <vopc<0x11, 0x51>, "v_cmpx_lt_f32">;
525 defm V_CMPX_EQ_F32 : VOPCX_F32 <vopc<0x12, 0x52>, "v_cmpx_eq_f32">;
526 defm V_CMPX_LE_F32 : VOPCX_F32 <vopc<0x13, 0x53>, "v_cmpx_le_f32">;
527 defm V_CMPX_GT_F32 : VOPCX_F32 <vopc<0x14, 0x54>, "v_cmpx_gt_f32">;
528 defm V_CMPX_LG_F32 : VOPCX_F32 <vopc<0x15, 0x55>, "v_cmpx_lg_f32">;
529 defm V_CMPX_GE_F32 : VOPCX_F32 <vopc<0x16, 0x56>, "v_cmpx_ge_f32">;
530 defm V_CMPX_O_F32 : VOPCX_F32 <vopc<0x17, 0x57>, "v_cmpx_o_f32">;
531 defm V_CMPX_U_F32 : VOPCX_F32 <vopc<0x18, 0x58>, "v_cmpx_u_f32">;
532 defm V_CMPX_NGE_F32 : VOPCX_F32 <vopc<0x19, 0x59>, "v_cmpx_nge_f32">;
533 defm V_CMPX_NLG_F32 : VOPCX_F32 <vopc<0x1a, 0x5a>, "v_cmpx_nlg_f32">;
534 defm V_CMPX_NGT_F32 : VOPCX_F32 <vopc<0x1b, 0x5b>, "v_cmpx_ngt_f32">;
535 defm V_CMPX_NLE_F32 : VOPCX_F32 <vopc<0x1c, 0x5c>, "v_cmpx_nle_f32">;
536 defm V_CMPX_NEQ_F32 : VOPCX_F32 <vopc<0x1d, 0x5d>, "v_cmpx_neq_f32">;
537 defm V_CMPX_NLT_F32 : VOPCX_F32 <vopc<0x1e, 0x5e>, "v_cmpx_nlt_f32">;
538 defm V_CMPX_TRU_F32 : VOPCX_F32 <vopc<0x1f, 0x5f>, "v_cmpx_tru_f32">;
540 } // End hasSideEffects = 1
542 defm V_CMP_F_F64 : VOPC_F64 <vopc<0x20, 0x60>, "v_cmp_f_f64">;
543 defm V_CMP_LT_F64 : VOPC_F64 <vopc<0x21, 0x61>, "v_cmp_lt_f64", COND_OLT>;
544 defm V_CMP_EQ_F64 : VOPC_F64 <vopc<0x22, 0x62>, "v_cmp_eq_f64", COND_OEQ>;
545 defm V_CMP_LE_F64 : VOPC_F64 <vopc<0x23, 0x63>, "v_cmp_le_f64", COND_OLE>;
546 defm V_CMP_GT_F64 : VOPC_F64 <vopc<0x24, 0x64>, "v_cmp_gt_f64", COND_OGT>;
547 defm V_CMP_LG_F64 : VOPC_F64 <vopc<0x25, 0x65>, "v_cmp_lg_f64", COND_ONE>;
548 defm V_CMP_GE_F64 : VOPC_F64 <vopc<0x26, 0x66>, "v_cmp_ge_f64", COND_OGE>;
549 defm V_CMP_O_F64 : VOPC_F64 <vopc<0x27, 0x67>, "v_cmp_o_f64", COND_O>;
550 defm V_CMP_U_F64 : VOPC_F64 <vopc<0x28, 0x68>, "v_cmp_u_f64", COND_UO>;
551 defm V_CMP_NGE_F64 : VOPC_F64 <vopc<0x29, 0x69>, "v_cmp_nge_f64", COND_ULT>;
552 defm V_CMP_NLG_F64 : VOPC_F64 <vopc<0x2a, 0x6a>, "v_cmp_nlg_f64", COND_UEQ>;
553 defm V_CMP_NGT_F64 : VOPC_F64 <vopc<0x2b, 0x6b>, "v_cmp_ngt_f64", COND_ULE>;
554 defm V_CMP_NLE_F64 : VOPC_F64 <vopc<0x2c, 0x6c>, "v_cmp_nle_f64", COND_UGT>;
555 defm V_CMP_NEQ_F64 : VOPC_F64 <vopc<0x2d, 0x6d>, "v_cmp_neq_f64", COND_UNE>;
556 defm V_CMP_NLT_F64 : VOPC_F64 <vopc<0x2e, 0x6e>, "v_cmp_nlt_f64", COND_UGE>;
557 defm V_CMP_TRU_F64 : VOPC_F64 <vopc<0x2f, 0x6f>, "v_cmp_tru_f64">;
559 let hasSideEffects = 1 in {
561 defm V_CMPX_F_F64 : VOPCX_F64 <vopc<0x30, 0x70>, "v_cmpx_f_f64">;
562 defm V_CMPX_LT_F64 : VOPCX_F64 <vopc<0x31, 0x71>, "v_cmpx_lt_f64">;
563 defm V_CMPX_EQ_F64 : VOPCX_F64 <vopc<0x32, 0x72>, "v_cmpx_eq_f64">;
564 defm V_CMPX_LE_F64 : VOPCX_F64 <vopc<0x33, 0x73>, "v_cmpx_le_f64">;
565 defm V_CMPX_GT_F64 : VOPCX_F64 <vopc<0x34, 0x74>, "v_cmpx_gt_f64">;
566 defm V_CMPX_LG_F64 : VOPCX_F64 <vopc<0x35, 0x75>, "v_cmpx_lg_f64">;
567 defm V_CMPX_GE_F64 : VOPCX_F64 <vopc<0x36, 0x76>, "v_cmpx_ge_f64">;
568 defm V_CMPX_O_F64 : VOPCX_F64 <vopc<0x37, 0x77>, "v_cmpx_o_f64">;
569 defm V_CMPX_U_F64 : VOPCX_F64 <vopc<0x38, 0x78>, "v_cmpx_u_f64">;
570 defm V_CMPX_NGE_F64 : VOPCX_F64 <vopc<0x39, 0x79>, "v_cmpx_nge_f64">;
571 defm V_CMPX_NLG_F64 : VOPCX_F64 <vopc<0x3a, 0x7a>, "v_cmpx_nlg_f64">;
572 defm V_CMPX_NGT_F64 : VOPCX_F64 <vopc<0x3b, 0x7b>, "v_cmpx_ngt_f64">;
573 defm V_CMPX_NLE_F64 : VOPCX_F64 <vopc<0x3c, 0x7c>, "v_cmpx_nle_f64">;
574 defm V_CMPX_NEQ_F64 : VOPCX_F64 <vopc<0x3d, 0x7d>, "v_cmpx_neq_f64">;
575 defm V_CMPX_NLT_F64 : VOPCX_F64 <vopc<0x3e, 0x7e>, "v_cmpx_nlt_f64">;
576 defm V_CMPX_TRU_F64 : VOPCX_F64 <vopc<0x3f, 0x7f>, "v_cmpx_tru_f64">;
578 } // End hasSideEffects = 1
580 let SubtargetPredicate = isSICI in {
582 defm V_CMPS_F_F32 : VOPC_F32 <vopc<0x40>, "v_cmps_f_f32">;
583 defm V_CMPS_LT_F32 : VOPC_F32 <vopc<0x41>, "v_cmps_lt_f32">;
584 defm V_CMPS_EQ_F32 : VOPC_F32 <vopc<0x42>, "v_cmps_eq_f32">;
585 defm V_CMPS_LE_F32 : VOPC_F32 <vopc<0x43>, "v_cmps_le_f32">;
586 defm V_CMPS_GT_F32 : VOPC_F32 <vopc<0x44>, "v_cmps_gt_f32">;
587 defm V_CMPS_LG_F32 : VOPC_F32 <vopc<0x45>, "v_cmps_lg_f32">;
588 defm V_CMPS_GE_F32 : VOPC_F32 <vopc<0x46>, "v_cmps_ge_f32">;
589 defm V_CMPS_O_F32 : VOPC_F32 <vopc<0x47>, "v_cmps_o_f32">;
590 defm V_CMPS_U_F32 : VOPC_F32 <vopc<0x48>, "v_cmps_u_f32">;
591 defm V_CMPS_NGE_F32 : VOPC_F32 <vopc<0x49>, "v_cmps_nge_f32">;
592 defm V_CMPS_NLG_F32 : VOPC_F32 <vopc<0x4a>, "v_cmps_nlg_f32">;
593 defm V_CMPS_NGT_F32 : VOPC_F32 <vopc<0x4b>, "v_cmps_ngt_f32">;
594 defm V_CMPS_NLE_F32 : VOPC_F32 <vopc<0x4c>, "v_cmps_nle_f32">;
595 defm V_CMPS_NEQ_F32 : VOPC_F32 <vopc<0x4d>, "v_cmps_neq_f32">;
596 defm V_CMPS_NLT_F32 : VOPC_F32 <vopc<0x4e>, "v_cmps_nlt_f32">;
597 defm V_CMPS_TRU_F32 : VOPC_F32 <vopc<0x4f>, "v_cmps_tru_f32">;
599 let hasSideEffects = 1 in {
601 defm V_CMPSX_F_F32 : VOPCX_F32 <vopc<0x50>, "v_cmpsx_f_f32">;
602 defm V_CMPSX_LT_F32 : VOPCX_F32 <vopc<0x51>, "v_cmpsx_lt_f32">;
603 defm V_CMPSX_EQ_F32 : VOPCX_F32 <vopc<0x52>, "v_cmpsx_eq_f32">;
604 defm V_CMPSX_LE_F32 : VOPCX_F32 <vopc<0x53>, "v_cmpsx_le_f32">;
605 defm V_CMPSX_GT_F32 : VOPCX_F32 <vopc<0x54>, "v_cmpsx_gt_f32">;
606 defm V_CMPSX_LG_F32 : VOPCX_F32 <vopc<0x55>, "v_cmpsx_lg_f32">;
607 defm V_CMPSX_GE_F32 : VOPCX_F32 <vopc<0x56>, "v_cmpsx_ge_f32">;
608 defm V_CMPSX_O_F32 : VOPCX_F32 <vopc<0x57>, "v_cmpsx_o_f32">;
609 defm V_CMPSX_U_F32 : VOPCX_F32 <vopc<0x58>, "v_cmpsx_u_f32">;
610 defm V_CMPSX_NGE_F32 : VOPCX_F32 <vopc<0x59>, "v_cmpsx_nge_f32">;
611 defm V_CMPSX_NLG_F32 : VOPCX_F32 <vopc<0x5a>, "v_cmpsx_nlg_f32">;
612 defm V_CMPSX_NGT_F32 : VOPCX_F32 <vopc<0x5b>, "v_cmpsx_ngt_f32">;
613 defm V_CMPSX_NLE_F32 : VOPCX_F32 <vopc<0x5c>, "v_cmpsx_nle_f32">;
614 defm V_CMPSX_NEQ_F32 : VOPCX_F32 <vopc<0x5d>, "v_cmpsx_neq_f32">;
615 defm V_CMPSX_NLT_F32 : VOPCX_F32 <vopc<0x5e>, "v_cmpsx_nlt_f32">;
616 defm V_CMPSX_TRU_F32 : VOPCX_F32 <vopc<0x5f>, "v_cmpsx_tru_f32">;
618 } // End hasSideEffects = 1
620 defm V_CMPS_F_F64 : VOPC_F64 <vopc<0x60>, "v_cmps_f_f64">;
621 defm V_CMPS_LT_F64 : VOPC_F64 <vopc<0x61>, "v_cmps_lt_f64">;
622 defm V_CMPS_EQ_F64 : VOPC_F64 <vopc<0x62>, "v_cmps_eq_f64">;
623 defm V_CMPS_LE_F64 : VOPC_F64 <vopc<0x63>, "v_cmps_le_f64">;
624 defm V_CMPS_GT_F64 : VOPC_F64 <vopc<0x64>, "v_cmps_gt_f64">;
625 defm V_CMPS_LG_F64 : VOPC_F64 <vopc<0x65>, "v_cmps_lg_f64">;
626 defm V_CMPS_GE_F64 : VOPC_F64 <vopc<0x66>, "v_cmps_ge_f64">;
627 defm V_CMPS_O_F64 : VOPC_F64 <vopc<0x67>, "v_cmps_o_f64">;
628 defm V_CMPS_U_F64 : VOPC_F64 <vopc<0x68>, "v_cmps_u_f64">;
629 defm V_CMPS_NGE_F64 : VOPC_F64 <vopc<0x69>, "v_cmps_nge_f64">;
630 defm V_CMPS_NLG_F64 : VOPC_F64 <vopc<0x6a>, "v_cmps_nlg_f64">;
631 defm V_CMPS_NGT_F64 : VOPC_F64 <vopc<0x6b>, "v_cmps_ngt_f64">;
632 defm V_CMPS_NLE_F64 : VOPC_F64 <vopc<0x6c>, "v_cmps_nle_f64">;
633 defm V_CMPS_NEQ_F64 : VOPC_F64 <vopc<0x6d>, "v_cmps_neq_f64">;
634 defm V_CMPS_NLT_F64 : VOPC_F64 <vopc<0x6e>, "v_cmps_nlt_f64">;
635 defm V_CMPS_TRU_F64 : VOPC_F64 <vopc<0x6f>, "v_cmps_tru_f64">;
637 let hasSideEffects = 1, Defs = [EXEC] in {
639 defm V_CMPSX_F_F64 : VOPC_F64 <vopc<0x70>, "v_cmpsx_f_f64">;
640 defm V_CMPSX_LT_F64 : VOPC_F64 <vopc<0x71>, "v_cmpsx_lt_f64">;
641 defm V_CMPSX_EQ_F64 : VOPC_F64 <vopc<0x72>, "v_cmpsx_eq_f64">;
642 defm V_CMPSX_LE_F64 : VOPC_F64 <vopc<0x73>, "v_cmpsx_le_f64">;
643 defm V_CMPSX_GT_F64 : VOPC_F64 <vopc<0x74>, "v_cmpsx_gt_f64">;
644 defm V_CMPSX_LG_F64 : VOPC_F64 <vopc<0x75>, "v_cmpsx_lg_f64">;
645 defm V_CMPSX_GE_F64 : VOPC_F64 <vopc<0x76>, "v_cmpsx_ge_f64">;
646 defm V_CMPSX_O_F64 : VOPC_F64 <vopc<0x77>, "v_cmpsx_o_f64">;
647 defm V_CMPSX_U_F64 : VOPC_F64 <vopc<0x78>, "v_cmpsx_u_f64">;
648 defm V_CMPSX_NGE_F64 : VOPC_F64 <vopc<0x79>, "v_cmpsx_nge_f64">;
649 defm V_CMPSX_NLG_F64 : VOPC_F64 <vopc<0x7a>, "v_cmpsx_nlg_f64">;
650 defm V_CMPSX_NGT_F64 : VOPC_F64 <vopc<0x7b>, "v_cmpsx_ngt_f64">;
651 defm V_CMPSX_NLE_F64 : VOPC_F64 <vopc<0x7c>, "v_cmpsx_nle_f64">;
652 defm V_CMPSX_NEQ_F64 : VOPC_F64 <vopc<0x7d>, "v_cmpsx_neq_f64">;
653 defm V_CMPSX_NLT_F64 : VOPC_F64 <vopc<0x7e>, "v_cmpsx_nlt_f64">;
654 defm V_CMPSX_TRU_F64 : VOPC_F64 <vopc<0x7f>, "v_cmpsx_tru_f64">;
656 } // End hasSideEffects = 1, Defs = [EXEC]
658 } // End SubtargetPredicate = isSICI
660 defm V_CMP_F_I32 : VOPC_I32 <vopc<0x80, 0xc0>, "v_cmp_f_i32">;
661 defm V_CMP_LT_I32 : VOPC_I32 <vopc<0x81, 0xc1>, "v_cmp_lt_i32", COND_SLT>;
662 defm V_CMP_EQ_I32 : VOPC_I32 <vopc<0x82, 0xc2>, "v_cmp_eq_i32", COND_EQ>;
663 defm V_CMP_LE_I32 : VOPC_I32 <vopc<0x83, 0xc3>, "v_cmp_le_i32", COND_SLE>;
664 defm V_CMP_GT_I32 : VOPC_I32 <vopc<0x84, 0xc4>, "v_cmp_gt_i32", COND_SGT>;
665 defm V_CMP_NE_I32 : VOPC_I32 <vopc<0x85, 0xc5>, "v_cmp_ne_i32", COND_NE>;
666 defm V_CMP_GE_I32 : VOPC_I32 <vopc<0x86, 0xc6>, "v_cmp_ge_i32", COND_SGE>;
667 defm V_CMP_T_I32 : VOPC_I32 <vopc<0x87, 0xc7>, "v_cmp_t_i32">;
669 let hasSideEffects = 1 in {
671 defm V_CMPX_F_I32 : VOPCX_I32 <vopc<0x90, 0xd0>, "v_cmpx_f_i32">;
672 defm V_CMPX_LT_I32 : VOPCX_I32 <vopc<0x91, 0xd1>, "v_cmpx_lt_i32">;
673 defm V_CMPX_EQ_I32 : VOPCX_I32 <vopc<0x92, 0xd2>, "v_cmpx_eq_i32">;
674 defm V_CMPX_LE_I32 : VOPCX_I32 <vopc<0x93, 0xd3>, "v_cmpx_le_i32">;
675 defm V_CMPX_GT_I32 : VOPCX_I32 <vopc<0x94, 0xd4>, "v_cmpx_gt_i32">;
676 defm V_CMPX_NE_I32 : VOPCX_I32 <vopc<0x95, 0xd5>, "v_cmpx_ne_i32">;
677 defm V_CMPX_GE_I32 : VOPCX_I32 <vopc<0x96, 0xd6>, "v_cmpx_ge_i32">;
678 defm V_CMPX_T_I32 : VOPCX_I32 <vopc<0x97, 0xd7>, "v_cmpx_t_i32">;
680 } // End hasSideEffects = 1
682 defm V_CMP_F_I64 : VOPC_I64 <vopc<0xa0, 0xe0>, "v_cmp_f_i64">;
683 defm V_CMP_LT_I64 : VOPC_I64 <vopc<0xa1, 0xe1>, "v_cmp_lt_i64", COND_SLT>;
684 defm V_CMP_EQ_I64 : VOPC_I64 <vopc<0xa2, 0xe2>, "v_cmp_eq_i64", COND_EQ>;
685 defm V_CMP_LE_I64 : VOPC_I64 <vopc<0xa3, 0xe3>, "v_cmp_le_i64", COND_SLE>;
686 defm V_CMP_GT_I64 : VOPC_I64 <vopc<0xa4, 0xe4>, "v_cmp_gt_i64", COND_SGT>;
687 defm V_CMP_NE_I64 : VOPC_I64 <vopc<0xa5, 0xe5>, "v_cmp_ne_i64", COND_NE>;
688 defm V_CMP_GE_I64 : VOPC_I64 <vopc<0xa6, 0xe6>, "v_cmp_ge_i64", COND_SGE>;
689 defm V_CMP_T_I64 : VOPC_I64 <vopc<0xa7, 0xe7>, "v_cmp_t_i64">;
691 let hasSideEffects = 1 in {
693 defm V_CMPX_F_I64 : VOPCX_I64 <vopc<0xb0, 0xf0>, "v_cmpx_f_i64">;
694 defm V_CMPX_LT_I64 : VOPCX_I64 <vopc<0xb1, 0xf1>, "v_cmpx_lt_i64">;
695 defm V_CMPX_EQ_I64 : VOPCX_I64 <vopc<0xb2, 0xf2>, "v_cmpx_eq_i64">;
696 defm V_CMPX_LE_I64 : VOPCX_I64 <vopc<0xb3, 0xf3>, "v_cmpx_le_i64">;
697 defm V_CMPX_GT_I64 : VOPCX_I64 <vopc<0xb4, 0xf4>, "v_cmpx_gt_i64">;
698 defm V_CMPX_NE_I64 : VOPCX_I64 <vopc<0xb5, 0xf5>, "v_cmpx_ne_i64">;
699 defm V_CMPX_GE_I64 : VOPCX_I64 <vopc<0xb6, 0xf6>, "v_cmpx_ge_i64">;
700 defm V_CMPX_T_I64 : VOPCX_I64 <vopc<0xb7, 0xf7>, "v_cmpx_t_i64">;
702 } // End hasSideEffects = 1
704 defm V_CMP_F_U32 : VOPC_I32 <vopc<0xc0, 0xc8>, "v_cmp_f_u32">;
705 defm V_CMP_LT_U32 : VOPC_I32 <vopc<0xc1, 0xc9>, "v_cmp_lt_u32", COND_ULT>;
706 defm V_CMP_EQ_U32 : VOPC_I32 <vopc<0xc2, 0xca>, "v_cmp_eq_u32", COND_EQ>;
707 defm V_CMP_LE_U32 : VOPC_I32 <vopc<0xc3, 0xcb>, "v_cmp_le_u32", COND_ULE>;
708 defm V_CMP_GT_U32 : VOPC_I32 <vopc<0xc4, 0xcc>, "v_cmp_gt_u32", COND_UGT>;
709 defm V_CMP_NE_U32 : VOPC_I32 <vopc<0xc5, 0xcd>, "v_cmp_ne_u32", COND_NE>;
710 defm V_CMP_GE_U32 : VOPC_I32 <vopc<0xc6, 0xce>, "v_cmp_ge_u32", COND_UGE>;
711 defm V_CMP_T_U32 : VOPC_I32 <vopc<0xc7, 0xcf>, "v_cmp_t_u32">;
713 let hasSideEffects = 1 in {
715 defm V_CMPX_F_U32 : VOPCX_I32 <vopc<0xd0, 0xd8>, "v_cmpx_f_u32">;
716 defm V_CMPX_LT_U32 : VOPCX_I32 <vopc<0xd1, 0xd9>, "v_cmpx_lt_u32">;
717 defm V_CMPX_EQ_U32 : VOPCX_I32 <vopc<0xd2, 0xda>, "v_cmpx_eq_u32">;
718 defm V_CMPX_LE_U32 : VOPCX_I32 <vopc<0xd3, 0xdb>, "v_cmpx_le_u32">;
719 defm V_CMPX_GT_U32 : VOPCX_I32 <vopc<0xd4, 0xdc>, "v_cmpx_gt_u32">;
720 defm V_CMPX_NE_U32 : VOPCX_I32 <vopc<0xd5, 0xdd>, "v_cmpx_ne_u32">;
721 defm V_CMPX_GE_U32 : VOPCX_I32 <vopc<0xd6, 0xde>, "v_cmpx_ge_u32">;
722 defm V_CMPX_T_U32 : VOPCX_I32 <vopc<0xd7, 0xdf>, "v_cmpx_t_u32">;
724 } // End hasSideEffects = 1
726 defm V_CMP_F_U64 : VOPC_I64 <vopc<0xe0, 0xe8>, "v_cmp_f_u64">;
727 defm V_CMP_LT_U64 : VOPC_I64 <vopc<0xe1, 0xe9>, "v_cmp_lt_u64", COND_ULT>;
728 defm V_CMP_EQ_U64 : VOPC_I64 <vopc<0xe2, 0xea>, "v_cmp_eq_u64", COND_EQ>;
729 defm V_CMP_LE_U64 : VOPC_I64 <vopc<0xe3, 0xeb>, "v_cmp_le_u64", COND_ULE>;
730 defm V_CMP_GT_U64 : VOPC_I64 <vopc<0xe4, 0xec>, "v_cmp_gt_u64", COND_UGT>;
731 defm V_CMP_NE_U64 : VOPC_I64 <vopc<0xe5, 0xed>, "v_cmp_ne_u64", COND_NE>;
732 defm V_CMP_GE_U64 : VOPC_I64 <vopc<0xe6, 0xee>, "v_cmp_ge_u64", COND_UGE>;
733 defm V_CMP_T_U64 : VOPC_I64 <vopc<0xe7, 0xef>, "v_cmp_t_u64">;
735 let hasSideEffects = 1 in {
737 defm V_CMPX_F_U64 : VOPCX_I64 <vopc<0xf0, 0xf8>, "v_cmpx_f_u64">;
738 defm V_CMPX_LT_U64 : VOPCX_I64 <vopc<0xf1, 0xf9>, "v_cmpx_lt_u64">;
739 defm V_CMPX_EQ_U64 : VOPCX_I64 <vopc<0xf2, 0xfa>, "v_cmpx_eq_u64">;
740 defm V_CMPX_LE_U64 : VOPCX_I64 <vopc<0xf3, 0xfb>, "v_cmpx_le_u64">;
741 defm V_CMPX_GT_U64 : VOPCX_I64 <vopc<0xf4, 0xfc>, "v_cmpx_gt_u64">;
742 defm V_CMPX_NE_U64 : VOPCX_I64 <vopc<0xf5, 0xfd>, "v_cmpx_ne_u64">;
743 defm V_CMPX_GE_U64 : VOPCX_I64 <vopc<0xf6, 0xfe>, "v_cmpx_ge_u64">;
744 defm V_CMPX_T_U64 : VOPCX_I64 <vopc<0xf7, 0xff>, "v_cmpx_t_u64">;
746 } // End hasSideEffects = 1
748 defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <vopc<0x88, 0x10>, "v_cmp_class_f32">;
750 let hasSideEffects = 1 in {
751 defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <vopc<0x98, 0x11>, "v_cmpx_class_f32">;
752 } // End hasSideEffects = 1
754 defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <vopc<0xa8, 0x12>, "v_cmp_class_f64">;
756 let hasSideEffects = 1 in {
757 defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <vopc<0xb8, 0x13>, "v_cmpx_class_f64">;
758 } // End hasSideEffects = 1
760 } // End isCompare = 1
762 //===----------------------------------------------------------------------===//
764 //===----------------------------------------------------------------------===//
767 def DS_ADD_U32 : DS_1A1D_NORET <0x0, "ds_add_u32", VGPR_32>;
768 def DS_SUB_U32 : DS_1A1D_NORET <0x1, "ds_sub_u32", VGPR_32>;
769 def DS_RSUB_U32 : DS_1A1D_NORET <0x2, "ds_rsub_u32", VGPR_32>;
770 def DS_INC_U32 : DS_1A1D_NORET <0x3, "ds_inc_u32", VGPR_32>;
771 def DS_DEC_U32 : DS_1A1D_NORET <0x4, "ds_dec_u32", VGPR_32>;
772 def DS_MIN_I32 : DS_1A1D_NORET <0x5, "ds_min_i32", VGPR_32>;
773 def DS_MAX_I32 : DS_1A1D_NORET <0x6, "ds_max_i32", VGPR_32>;
774 def DS_MIN_U32 : DS_1A1D_NORET <0x7, "ds_min_u32", VGPR_32>;
775 def DS_MAX_U32 : DS_1A1D_NORET <0x8, "ds_max_u32", VGPR_32>;
776 def DS_AND_B32 : DS_1A1D_NORET <0x9, "ds_and_b32", VGPR_32>;
777 def DS_OR_B32 : DS_1A1D_NORET <0xa, "ds_or_b32", VGPR_32>;
778 def DS_XOR_B32 : DS_1A1D_NORET <0xb, "ds_xor_b32", VGPR_32>;
779 def DS_MSKOR_B32 : DS_1A1D_NORET <0xc, "ds_mskor_b32", VGPR_32>;
780 def DS_CMPST_B32 : DS_1A2D_NORET <0x10, "ds_cmpst_b32", VGPR_32>;
781 def DS_CMPST_F32 : DS_1A2D_NORET <0x11, "ds_cmpst_f32", VGPR_32>;
782 def DS_MIN_F32 : DS_1A1D_NORET <0x12, "ds_min_f32", VGPR_32>;
783 def DS_MAX_F32 : DS_1A1D_NORET <0x13, "ds_max_f32", VGPR_32>;
785 def DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
786 def DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
787 def DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
788 def DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
789 def DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">;
790 def DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "ds_min_rtn_i32", VGPR_32, "ds_min_i32">;
791 def DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
792 def DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "ds_min_rtn_u32", VGPR_32, "ds_min_u32">;
793 def DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "ds_max_rtn_u32", VGPR_32, "ds_max_u32">;
794 def DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "ds_and_rtn_b32", VGPR_32, "ds_and_b32">;
795 def DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "ds_or_rtn_b32", VGPR_32, "ds_or_b32">;
796 def DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">;
797 def DS_MSKOR_RTN_B32 : DS_1A1D_RET <0x2c, "ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">;
798 def DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "ds_wrxchg_rtn_b32", VGPR_32>;
799 //def DS_WRXCHG2_RTN_B32 : DS_2A0D_RET <0x2e, "ds_wrxchg2_rtn_b32", VGPR_32, "ds_wrxchg2_b32">;
800 //def DS_WRXCHG2ST64_RTN_B32 : DS_2A0D_RET <0x2f, "ds_wrxchg2_rtn_b32", VGPR_32, "ds_wrxchg2st64_b32">;
801 def DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">;
802 def DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">;
803 def DS_MIN_RTN_F32 : DS_1A1D_RET <0x32, "ds_min_rtn_f32", VGPR_32, "ds_min_f32">;
804 def DS_MAX_RTN_F32 : DS_1A1D_RET <0x33, "ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
806 let SubtargetPredicate = isCI in {
807 def DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "ds_wrap_rtn_f32", VGPR_32, "ds_wrap_f32">;
811 def DS_ADD_U64 : DS_1A1D_NORET <0x40, "ds_add_u64", VReg_64>;
812 def DS_SUB_U64 : DS_1A1D_NORET <0x41, "ds_sub_u64", VReg_64>;
813 def DS_RSUB_U64 : DS_1A1D_NORET <0x42, "ds_rsub_u64", VReg_64>;
814 def DS_INC_U64 : DS_1A1D_NORET <0x43, "ds_inc_u64", VReg_64>;
815 def DS_DEC_U64 : DS_1A1D_NORET <0x44, "ds_dec_u64", VReg_64>;
816 def DS_MIN_I64 : DS_1A1D_NORET <0x45, "ds_min_i64", VReg_64>;
817 def DS_MAX_I64 : DS_1A1D_NORET <0x46, "ds_max_i64", VReg_64>;
818 def DS_MIN_U64 : DS_1A1D_NORET <0x47, "ds_min_u64", VReg_64>;
819 def DS_MAX_U64 : DS_1A1D_NORET <0x48, "ds_max_u64", VReg_64>;
820 def DS_AND_B64 : DS_1A1D_NORET <0x49, "ds_and_b64", VReg_64>;
821 def DS_OR_B64 : DS_1A1D_NORET <0x4a, "ds_or_b64", VReg_64>;
822 def DS_XOR_B64 : DS_1A1D_NORET <0x4b, "ds_xor_b64", VReg_64>;
823 def DS_MSKOR_B64 : DS_1A1D_NORET <0x4c, "ds_mskor_b64", VReg_64>;
824 def DS_CMPST_B64 : DS_1A2D_NORET <0x50, "ds_cmpst_b64", VReg_64>;
825 def DS_CMPST_F64 : DS_1A2D_NORET <0x51, "ds_cmpst_f64", VReg_64>;
826 def DS_MIN_F64 : DS_1A1D_NORET <0x52, "ds_min_f64", VReg_64>;
827 def DS_MAX_F64 : DS_1A1D_NORET <0x53, "ds_max_f64", VReg_64>;
829 def DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "ds_add_rtn_u64", VReg_64, "ds_add_u64">;
830 def DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "ds_sub_rtn_u64", VReg_64, "ds_sub_u64">;
831 def DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">;
832 def DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "ds_inc_rtn_u64", VReg_64, "ds_inc_u64">;
833 def DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "ds_dec_rtn_u64", VReg_64, "ds_dec_u64">;
834 def DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "ds_min_rtn_i64", VReg_64, "ds_min_i64">;
835 def DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "ds_max_rtn_i64", VReg_64, "ds_max_i64">;
836 def DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "ds_min_rtn_u64", VReg_64, "ds_min_u64">;
837 def DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "ds_max_rtn_u64", VReg_64, "ds_max_u64">;
838 def DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "ds_and_rtn_b64", VReg_64, "ds_and_b64">;
839 def DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "ds_or_rtn_b64", VReg_64, "ds_or_b64">;
840 def DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "ds_xor_rtn_b64", VReg_64, "ds_xor_b64">;
841 def DS_MSKOR_RTN_B64 : DS_1A1D_RET <0x6c, "ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">;
842 def DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "ds_wrxchg_rtn_b64", VReg_64, "ds_wrxchg_b64">;
843 //def DS_WRXCHG2_RTN_B64 : DS_2A0D_RET <0x6e, "ds_wrxchg2_rtn_b64", VReg_64, "ds_wrxchg2_b64">;
844 //def DS_WRXCHG2ST64_RTN_B64 : DS_2A0D_RET <0x6f, "ds_wrxchg2_rtn_b64", VReg_64, "ds_wrxchg2st64_b64">;
845 def DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">;
846 def DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">;
847 def DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "ds_min_f64", VReg_64, "ds_min_f64">;
848 def DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "ds_max_f64", VReg_64, "ds_max_f64">;
850 //let SubtargetPredicate = isCI in {
851 // DS_CONDXCHG32_RTN_B64
852 // DS_CONDXCHG32_RTN_B128
855 // TODO: _SRC2_* forms
857 defm DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "ds_write_b32", VGPR_32>;
858 defm DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "ds_write_b8", VGPR_32>;
859 defm DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "ds_write_b16", VGPR_32>;
860 defm DS_WRITE_B64 : DS_Store_Helper <0x00000004d, "ds_write_b64", VReg_64>;
862 defm DS_READ_B32 : DS_Load_Helper <0x00000036, "ds_read_b32", VGPR_32>;
863 defm DS_READ_I8 : DS_Load_Helper <0x00000039, "ds_read_i8", VGPR_32>;
864 defm DS_READ_U8 : DS_Load_Helper <0x0000003a, "ds_read_u8", VGPR_32>;
865 defm DS_READ_I16 : DS_Load_Helper <0x0000003b, "ds_read_i16", VGPR_32>;
866 defm DS_READ_U16 : DS_Load_Helper <0x0000003c, "ds_read_u16", VGPR_32>;
867 defm DS_READ_B64 : DS_Load_Helper <0x00000076, "ds_read_b64", VReg_64>;
870 defm DS_WRITE2_B32 : DS_Store2_Helper <0x0000000E, "ds_write2_b32", VGPR_32>;
871 defm DS_WRITE2ST64_B32 : DS_Store2_Helper <0x0000000F, "ds_write2st64_b32", VGPR_32>;
872 defm DS_WRITE2_B64 : DS_Store2_Helper <0x0000004E, "ds_write2_b64", VReg_64>;
873 defm DS_WRITE2ST64_B64 : DS_Store2_Helper <0x0000004F, "ds_write2st64_b64", VReg_64>;
875 defm DS_READ2_B32 : DS_Load2_Helper <0x00000037, "ds_read2_b32", VReg_64>;
876 defm DS_READ2ST64_B32 : DS_Load2_Helper <0x00000038, "ds_read2st64_b32", VReg_64>;
877 defm DS_READ2_B64 : DS_Load2_Helper <0x00000075, "ds_read2_b64", VReg_128>;
878 defm DS_READ2ST64_B64 : DS_Load2_Helper <0x00000076, "ds_read2st64_b64", VReg_128>;
880 //===----------------------------------------------------------------------===//
881 // MUBUF Instructions
882 //===----------------------------------------------------------------------===//
884 let SubtargetPredicate = isSICI in {
886 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "buffer_load_format_x", []>;
887 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "buffer_load_format_xy", []>;
888 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "buffer_load_format_xyz", []>;
889 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "buffer_load_format_xyzw", VReg_128>;
890 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "buffer_store_format_x", []>;
891 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "buffer_store_format_xy", []>;
892 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "buffer_store_format_xyz", []>;
893 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "buffer_store_format_xyzw", []>;
894 defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <
895 0x00000008, "buffer_load_ubyte", VGPR_32, i32, az_extloadi8_global
897 defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <
898 0x00000009, "buffer_load_sbyte", VGPR_32, i32, sextloadi8_global
900 defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <
901 0x0000000a, "buffer_load_ushort", VGPR_32, i32, az_extloadi16_global
903 defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <
904 0x0000000b, "buffer_load_sshort", VGPR_32, i32, sextloadi16_global
906 defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <
907 0x0000000c, "buffer_load_dword", VGPR_32, i32, global_load
909 defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <
910 0x0000000d, "buffer_load_dwordx2", VReg_64, v2i32, global_load
912 defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <
913 0x0000000e, "buffer_load_dwordx4", VReg_128, v4i32, global_load
916 defm BUFFER_STORE_BYTE : MUBUF_Store_Helper <
917 0x00000018, "buffer_store_byte", VGPR_32, i32, truncstorei8_global
920 defm BUFFER_STORE_SHORT : MUBUF_Store_Helper <
921 0x0000001a, "buffer_store_short", VGPR_32, i32, truncstorei16_global
924 defm BUFFER_STORE_DWORD : MUBUF_Store_Helper <
925 0x0000001c, "buffer_store_dword", VGPR_32, i32, global_store
928 defm BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
929 0x0000001d, "buffer_store_dwordx2", VReg_64, v2i32, global_store
932 defm BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
933 0x0000001e, "buffer_store_dwordx4", VReg_128, v4i32, global_store
935 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "buffer_atomic_swap", []>;
936 defm BUFFER_ATOMIC_SWAP : MUBUF_Atomic <
937 0x00000030, "buffer_atomic_swap", VGPR_32, i32, atomic_swap_global
939 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "buffer_atomic_cmpswap", []>;
940 defm BUFFER_ATOMIC_ADD : MUBUF_Atomic <
941 0x00000032, "buffer_atomic_add", VGPR_32, i32, atomic_add_global
943 defm BUFFER_ATOMIC_SUB : MUBUF_Atomic <
944 0x00000033, "buffer_atomic_sub", VGPR_32, i32, atomic_sub_global
946 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "buffer_atomic_rsub", []>;
947 defm BUFFER_ATOMIC_SMIN : MUBUF_Atomic <
948 0x00000035, "buffer_atomic_smin", VGPR_32, i32, atomic_min_global
950 defm BUFFER_ATOMIC_UMIN : MUBUF_Atomic <
951 0x00000036, "buffer_atomic_umin", VGPR_32, i32, atomic_umin_global
953 defm BUFFER_ATOMIC_SMAX : MUBUF_Atomic <
954 0x00000037, "buffer_atomic_smax", VGPR_32, i32, atomic_max_global
956 defm BUFFER_ATOMIC_UMAX : MUBUF_Atomic <
957 0x00000038, "buffer_atomic_umax", VGPR_32, i32, atomic_umax_global
959 defm BUFFER_ATOMIC_AND : MUBUF_Atomic <
960 0x00000039, "buffer_atomic_and", VGPR_32, i32, atomic_and_global
962 defm BUFFER_ATOMIC_OR : MUBUF_Atomic <
963 0x0000003a, "buffer_atomic_or", VGPR_32, i32, atomic_or_global
965 defm BUFFER_ATOMIC_XOR : MUBUF_Atomic <
966 0x0000003b, "buffer_atomic_xor", VGPR_32, i32, atomic_xor_global
968 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "buffer_atomic_inc", []>;
969 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "buffer_atomic_dec", []>;
970 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "buffer_atomic_fcmpswap", []>;
971 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "buffer_atomic_fmin", []>;
972 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "buffer_atomic_fmax", []>;
973 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "buffer_atomic_swap_x2", []>;
974 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "buffer_atomic_cmpswap_x2", []>;
975 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "buffer_atomic_add_x2", []>;
976 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "buffer_atomic_sub_x2", []>;
977 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "buffer_atomic_rsub_x2", []>;
978 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "buffer_atomic_smin_x2", []>;
979 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "buffer_atomic_umin_x2", []>;
980 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "buffer_atomic_smax_x2", []>;
981 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "buffer_atomic_umax_x2", []>;
982 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "buffer_atomic_and_x2", []>;
983 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "buffer_atomic_or_x2", []>;
984 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "buffer_atomic_xor_x2", []>;
985 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "buffer_atomic_inc_x2", []>;
986 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "buffer_atomic_dec_x2", []>;
987 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "buffer_atomic_fcmpswap_x2", []>;
988 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "buffer_atomic_fmin_x2", []>;
989 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "buffer_atomic_fmax_x2", []>;
990 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "buffer_wbinvl1_sc", []>;
991 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "buffer_wbinvl1", []>;
993 } // End SubtargetPredicate = isSICI
995 //===----------------------------------------------------------------------===//
996 // MTBUF Instructions
997 //===----------------------------------------------------------------------===//
999 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "tbuffer_load_format_x", []>;
1000 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "tbuffer_load_format_xy", []>;
1001 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "tbuffer_load_format_xyz", []>;
1002 defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "tbuffer_load_format_xyzw", VReg_128>;
1003 defm TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "tbuffer_store_format_x", VGPR_32>;
1004 defm TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "tbuffer_store_format_xy", VReg_64>;
1005 defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "tbuffer_store_format_xyz", VReg_128>;
1006 defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "tbuffer_store_format_xyzw", VReg_128>;
1008 //===----------------------------------------------------------------------===//
1009 // MIMG Instructions
1010 //===----------------------------------------------------------------------===//
1012 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load">;
1013 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip">;
1014 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"image_load_pck", 0x00000002>;
1015 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"image_load_pck_sgn", 0x00000003>;
1016 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"image_load_mip_pck", 0x00000004>;
1017 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"image_load_mip_pck_sgn", 0x00000005>;
1018 //def IMAGE_STORE : MIMG_NoPattern_ <"image_store", 0x00000008>;
1019 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"image_store_mip", 0x00000009>;
1020 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"image_store_pck", 0x0000000a>;
1021 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"image_store_mip_pck", 0x0000000b>;
1022 defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo">;
1023 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"image_atomic_swap", 0x0000000f>;
1024 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"image_atomic_cmpswap", 0x00000010>;
1025 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"image_atomic_add", 0x00000011>;
1026 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"image_atomic_sub", 0x00000012>;
1027 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>;
1028 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"image_atomic_smin", 0x00000014>;
1029 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"image_atomic_umin", 0x00000015>;
1030 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"image_atomic_smax", 0x00000016>;
1031 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"image_atomic_umax", 0x00000017>;
1032 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"image_atomic_and", 0x00000018>;
1033 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"image_atomic_or", 0x00000019>;
1034 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"image_atomic_xor", 0x0000001a>;
1035 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"image_atomic_inc", 0x0000001b>;
1036 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"image_atomic_dec", 0x0000001c>;
1037 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d>;
1038 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>;
1039 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>;
1040 defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "image_sample">;
1041 defm IMAGE_SAMPLE_CL : MIMG_Sampler <0x00000021, "image_sample_cl">;
1042 defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "image_sample_d">;
1043 defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "image_sample_d_cl">;
1044 defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "image_sample_l">;
1045 defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "image_sample_b">;
1046 defm IMAGE_SAMPLE_B_CL : MIMG_Sampler <0x00000026, "image_sample_b_cl">;
1047 defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "image_sample_lz">;
1048 defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "image_sample_c">;
1049 defm IMAGE_SAMPLE_C_CL : MIMG_Sampler <0x00000029, "image_sample_c_cl">;
1050 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "image_sample_c_d">;
1051 defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "image_sample_c_d_cl">;
1052 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "image_sample_c_l">;
1053 defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "image_sample_c_b">;
1054 defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler <0x0000002e, "image_sample_c_b_cl">;
1055 defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "image_sample_c_lz">;
1056 defm IMAGE_SAMPLE_O : MIMG_Sampler <0x00000030, "image_sample_o">;
1057 defm IMAGE_SAMPLE_CL_O : MIMG_Sampler <0x00000031, "image_sample_cl_o">;
1058 defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "image_sample_d_o">;
1059 defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "image_sample_d_cl_o">;
1060 defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "image_sample_l_o">;
1061 defm IMAGE_SAMPLE_B_O : MIMG_Sampler <0x00000035, "image_sample_b_o">;
1062 defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler <0x00000036, "image_sample_b_cl_o">;
1063 defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "image_sample_lz_o">;
1064 defm IMAGE_SAMPLE_C_O : MIMG_Sampler <0x00000038, "image_sample_c_o">;
1065 defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler <0x00000039, "image_sample_c_cl_o">;
1066 defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "image_sample_c_d_o">;
1067 defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "image_sample_c_d_cl_o">;
1068 defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "image_sample_c_l_o">;
1069 defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler <0x0000003d, "image_sample_c_b_o">;
1070 defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler <0x0000003e, "image_sample_c_b_cl_o">;
1071 defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "image_sample_c_lz_o">;
1072 defm IMAGE_GATHER4 : MIMG_Gather <0x00000040, "image_gather4">;
1073 defm IMAGE_GATHER4_CL : MIMG_Gather <0x00000041, "image_gather4_cl">;
1074 defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "image_gather4_l">;
1075 defm IMAGE_GATHER4_B : MIMG_Gather <0x00000045, "image_gather4_b">;
1076 defm IMAGE_GATHER4_B_CL : MIMG_Gather <0x00000046, "image_gather4_b_cl">;
1077 defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "image_gather4_lz">;
1078 defm IMAGE_GATHER4_C : MIMG_Gather <0x00000048, "image_gather4_c">;
1079 defm IMAGE_GATHER4_C_CL : MIMG_Gather <0x00000049, "image_gather4_c_cl">;
1080 defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "image_gather4_c_l">;
1081 defm IMAGE_GATHER4_C_B : MIMG_Gather <0x0000004d, "image_gather4_c_b">;
1082 defm IMAGE_GATHER4_C_B_CL : MIMG_Gather <0x0000004e, "image_gather4_c_b_cl">;
1083 defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "image_gather4_c_lz">;
1084 defm IMAGE_GATHER4_O : MIMG_Gather <0x00000050, "image_gather4_o">;
1085 defm IMAGE_GATHER4_CL_O : MIMG_Gather <0x00000051, "image_gather4_cl_o">;
1086 defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "image_gather4_l_o">;
1087 defm IMAGE_GATHER4_B_O : MIMG_Gather <0x00000055, "image_gather4_b_o">;
1088 defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "image_gather4_b_cl_o">;
1089 defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "image_gather4_lz_o">;
1090 defm IMAGE_GATHER4_C_O : MIMG_Gather <0x00000058, "image_gather4_c_o">;
1091 defm IMAGE_GATHER4_C_CL_O : MIMG_Gather <0x00000059, "image_gather4_c_cl_o">;
1092 defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "image_gather4_c_l_o">;
1093 defm IMAGE_GATHER4_C_B_O : MIMG_Gather <0x0000005d, "image_gather4_c_b_o">;
1094 defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather <0x0000005e, "image_gather4_c_b_cl_o">;
1095 defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "image_gather4_c_lz_o">;
1096 defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, "image_get_lod">;
1097 defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "image_sample_cd">;
1098 defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "image_sample_cd_cl">;
1099 defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "image_sample_c_cd">;
1100 defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "image_sample_c_cd_cl">;
1101 defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "image_sample_cd_o">;
1102 defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "image_sample_cd_cl_o">;
1103 defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "image_sample_c_cd_o">;
1104 defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "image_sample_c_cd_cl_o">;
1105 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>;
1106 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>;
1108 //===----------------------------------------------------------------------===//
1109 // Flat Instructions
1110 //===----------------------------------------------------------------------===//
1112 let Predicates = [HasFlatAddressSpace] in {
1113 def FLAT_LOAD_UBYTE : FLAT_Load_Helper <0x00000008, "flat_load_ubyte", VGPR_32>;
1114 def FLAT_LOAD_SBYTE : FLAT_Load_Helper <0x00000009, "flat_load_sbyte", VGPR_32>;
1115 def FLAT_LOAD_USHORT : FLAT_Load_Helper <0x0000000a, "flat_load_ushort", VGPR_32>;
1116 def FLAT_LOAD_SSHORT : FLAT_Load_Helper <0x0000000b, "flat_load_sshort", VGPR_32>;
1117 def FLAT_LOAD_DWORD : FLAT_Load_Helper <0x0000000c, "flat_load_dword", VGPR_32>;
1118 def FLAT_LOAD_DWORDX2 : FLAT_Load_Helper <0x0000000d, "flat_load_dwordx2", VReg_64>;
1119 def FLAT_LOAD_DWORDX4 : FLAT_Load_Helper <0x0000000e, "flat_load_dwordx4", VReg_128>;
1120 def FLAT_LOAD_DWORDX3 : FLAT_Load_Helper <0x00000010, "flat_load_dwordx3", VReg_96>;
1122 def FLAT_STORE_BYTE : FLAT_Store_Helper <
1123 0x00000018, "flat_store_byte", VGPR_32
1126 def FLAT_STORE_SHORT : FLAT_Store_Helper <
1127 0x0000001a, "flat_store_short", VGPR_32
1130 def FLAT_STORE_DWORD : FLAT_Store_Helper <
1131 0x0000001c, "flat_store_dword", VGPR_32
1134 def FLAT_STORE_DWORDX2 : FLAT_Store_Helper <
1135 0x0000001d, "flat_store_dwordx2", VReg_64
1138 def FLAT_STORE_DWORDX4 : FLAT_Store_Helper <
1139 0x0000001e, "flat_store_dwordx4", VReg_128
1142 def FLAT_STORE_DWORDX3 : FLAT_Store_Helper <
1143 0x0000001e, "flat_store_dwordx3", VReg_96
1146 //def FLAT_ATOMIC_SWAP : FLAT_ <0x00000030, "flat_atomic_swap", []>;
1147 //def FLAT_ATOMIC_CMPSWAP : FLAT_ <0x00000031, "flat_atomic_cmpswap", []>;
1148 //def FLAT_ATOMIC_ADD : FLAT_ <0x00000032, "flat_atomic_add", []>;
1149 //def FLAT_ATOMIC_SUB : FLAT_ <0x00000033, "flat_atomic_sub", []>;
1150 //def FLAT_ATOMIC_RSUB : FLAT_ <0x00000034, "flat_atomic_rsub", []>;
1151 //def FLAT_ATOMIC_SMIN : FLAT_ <0x00000035, "flat_atomic_smin", []>;
1152 //def FLAT_ATOMIC_UMIN : FLAT_ <0x00000036, "flat_atomic_umin", []>;
1153 //def FLAT_ATOMIC_SMAX : FLAT_ <0x00000037, "flat_atomic_smax", []>;
1154 //def FLAT_ATOMIC_UMAX : FLAT_ <0x00000038, "flat_atomic_umax", []>;
1155 //def FLAT_ATOMIC_AND : FLAT_ <0x00000039, "flat_atomic_and", []>;
1156 //def FLAT_ATOMIC_OR : FLAT_ <0x0000003a, "flat_atomic_or", []>;
1157 //def FLAT_ATOMIC_XOR : FLAT_ <0x0000003b, "flat_atomic_xor", []>;
1158 //def FLAT_ATOMIC_INC : FLAT_ <0x0000003c, "flat_atomic_inc", []>;
1159 //def FLAT_ATOMIC_DEC : FLAT_ <0x0000003d, "flat_atomic_dec", []>;
1160 //def FLAT_ATOMIC_FCMPSWAP : FLAT_ <0x0000003e, "flat_atomic_fcmpswap", []>;
1161 //def FLAT_ATOMIC_FMIN : FLAT_ <0x0000003f, "flat_atomic_fmin", []>;
1162 //def FLAT_ATOMIC_FMAX : FLAT_ <0x00000040, "flat_atomic_fmax", []>;
1163 //def FLAT_ATOMIC_SWAP_X2 : FLAT_X2 <0x00000050, "flat_atomic_swap_x2", []>;
1164 //def FLAT_ATOMIC_CMPSWAP_X2 : FLAT_X2 <0x00000051, "flat_atomic_cmpswap_x2", []>;
1165 //def FLAT_ATOMIC_ADD_X2 : FLAT_X2 <0x00000052, "flat_atomic_add_x2", []>;
1166 //def FLAT_ATOMIC_SUB_X2 : FLAT_X2 <0x00000053, "flat_atomic_sub_x2", []>;
1167 //def FLAT_ATOMIC_RSUB_X2 : FLAT_X2 <0x00000054, "flat_atomic_rsub_x2", []>;
1168 //def FLAT_ATOMIC_SMIN_X2 : FLAT_X2 <0x00000055, "flat_atomic_smin_x2", []>;
1169 //def FLAT_ATOMIC_UMIN_X2 : FLAT_X2 <0x00000056, "flat_atomic_umin_x2", []>;
1170 //def FLAT_ATOMIC_SMAX_X2 : FLAT_X2 <0x00000057, "flat_atomic_smax_x2", []>;
1171 //def FLAT_ATOMIC_UMAX_X2 : FLAT_X2 <0x00000058, "flat_atomic_umax_x2", []>;
1172 //def FLAT_ATOMIC_AND_X2 : FLAT_X2 <0x00000059, "flat_atomic_and_x2", []>;
1173 //def FLAT_ATOMIC_OR_X2 : FLAT_X2 <0x0000005a, "flat_atomic_or_x2", []>;
1174 //def FLAT_ATOMIC_XOR_X2 : FLAT_X2 <0x0000005b, "flat_atomic_xor_x2", []>;
1175 //def FLAT_ATOMIC_INC_X2 : FLAT_X2 <0x0000005c, "flat_atomic_inc_x2", []>;
1176 //def FLAT_ATOMIC_DEC_X2 : FLAT_X2 <0x0000005d, "flat_atomic_dec_x2", []>;
1177 //def FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_X2 <0x0000005e, "flat_atomic_fcmpswap_x2", []>;
1178 //def FLAT_ATOMIC_FMIN_X2 : FLAT_X2 <0x0000005f, "flat_atomic_fmin_x2", []>;
1179 //def FLAT_ATOMIC_FMAX_X2 : FLAT_X2 <0x00000060, "flat_atomic_fmax_x2", []>;
1181 } // End HasFlatAddressSpace predicate
1182 //===----------------------------------------------------------------------===//
1183 // VOP1 Instructions
1184 //===----------------------------------------------------------------------===//
1186 //def V_NOP : VOP1_ <0x00000000, "v_nop", []>;
1188 let isMoveImm = 1 in {
1189 defm V_MOV_B32 : VOP1Inst <vop1<0x1>, "v_mov_b32", VOP_I32_I32>;
1190 } // End isMoveImm = 1
1192 let Uses = [EXEC] in {
1194 // FIXME: Specify SchedRW for READFIRSTLANE_B32
1196 def V_READFIRSTLANE_B32 : VOP1 <
1198 (outs SReg_32:$vdst),
1199 (ins VGPR_32:$src0),
1200 "v_readfirstlane_b32 $vdst, $src0",
1206 let SchedRW = [WriteQuarterRate32] in {
1208 defm V_CVT_I32_F64 : VOP1Inst <vop1<0x3>, "v_cvt_i32_f64",
1209 VOP_I32_F64, fp_to_sint
1211 defm V_CVT_F64_I32 : VOP1Inst <vop1<0x4>, "v_cvt_f64_i32",
1212 VOP_F64_I32, sint_to_fp
1214 defm V_CVT_F32_I32 : VOP1Inst <vop1<0x5>, "v_cvt_f32_i32",
1215 VOP_F32_I32, sint_to_fp
1217 defm V_CVT_F32_U32 : VOP1Inst <vop1<0x6>, "v_cvt_f32_u32",
1218 VOP_F32_I32, uint_to_fp
1220 defm V_CVT_U32_F32 : VOP1Inst <vop1<0x7>, "v_cvt_u32_f32",
1221 VOP_I32_F32, fp_to_uint
1223 defm V_CVT_I32_F32 : VOP1Inst <vop1<0x8>, "v_cvt_i32_f32",
1224 VOP_I32_F32, fp_to_sint
1226 defm V_MOV_FED_B32 : VOP1Inst <vop1<0x9>, "v_mov_fed_b32", VOP_I32_I32>;
1227 defm V_CVT_F16_F32 : VOP1Inst <vop1<0xa>, "v_cvt_f16_f32",
1228 VOP_I32_F32, fp_to_f16
1230 defm V_CVT_F32_F16 : VOP1Inst <vop1<0xb>, "v_cvt_f32_f16",
1231 VOP_F32_I32, f16_to_fp
1233 defm V_CVT_RPI_I32_F32 : VOP1Inst <vop1<0xc>, "v_cvt_rpi_i32_f32",
1234 VOP_I32_F32, cvt_rpi_i32_f32>;
1235 defm V_CVT_FLR_I32_F32 : VOP1Inst <vop1<0xd>, "v_cvt_flr_i32_f32",
1236 VOP_I32_F32, cvt_flr_i32_f32>;
1237 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "v_cvt_off_f32_i4", []>;
1238 defm V_CVT_F32_F64 : VOP1Inst <vop1<0xf>, "v_cvt_f32_f64",
1241 defm V_CVT_F64_F32 : VOP1Inst <vop1<0x10>, "v_cvt_f64_f32",
1242 VOP_F64_F32, fextend
1244 defm V_CVT_F32_UBYTE0 : VOP1Inst <vop1<0x11>, "v_cvt_f32_ubyte0",
1245 VOP_F32_I32, AMDGPUcvt_f32_ubyte0
1247 defm V_CVT_F32_UBYTE1 : VOP1Inst <vop1<0x12>, "v_cvt_f32_ubyte1",
1248 VOP_F32_I32, AMDGPUcvt_f32_ubyte1
1250 defm V_CVT_F32_UBYTE2 : VOP1Inst <vop1<0x13>, "v_cvt_f32_ubyte2",
1251 VOP_F32_I32, AMDGPUcvt_f32_ubyte2
1253 defm V_CVT_F32_UBYTE3 : VOP1Inst <vop1<0x14>, "v_cvt_f32_ubyte3",
1254 VOP_F32_I32, AMDGPUcvt_f32_ubyte3
1256 defm V_CVT_U32_F64 : VOP1Inst <vop1<0x15>, "v_cvt_u32_f64",
1257 VOP_I32_F64, fp_to_uint
1259 defm V_CVT_F64_U32 : VOP1Inst <vop1<0x16>, "v_cvt_f64_u32",
1260 VOP_F64_I32, uint_to_fp
1263 } // let SchedRW = [WriteQuarterRate32]
1265 defm V_FRACT_F32 : VOP1Inst <vop1<0x20, 0x1b>, "v_fract_f32",
1266 VOP_F32_F32, AMDGPUfract
1268 defm V_TRUNC_F32 : VOP1Inst <vop1<0x21, 0x1c>, "v_trunc_f32",
1271 defm V_CEIL_F32 : VOP1Inst <vop1<0x22, 0x1d>, "v_ceil_f32",
1274 defm V_RNDNE_F32 : VOP1Inst <vop1<0x23, 0x1e>, "v_rndne_f32",
1277 defm V_FLOOR_F32 : VOP1Inst <vop1<0x24, 0x1f>, "v_floor_f32",
1280 defm V_EXP_F32 : VOP1Inst <vop1<0x25, 0x20>, "v_exp_f32",
1284 let SchedRW = [WriteQuarterRate32] in {
1286 defm V_LOG_F32 : VOP1Inst <vop1<0x27, 0x21>, "v_log_f32",
1289 defm V_RCP_F32 : VOP1Inst <vop1<0x2a, 0x22>, "v_rcp_f32",
1290 VOP_F32_F32, AMDGPUrcp
1292 defm V_RCP_IFLAG_F32 : VOP1Inst <vop1<0x2b, 0x23>, "v_rcp_iflag_f32",
1295 defm V_RSQ_F32 : VOP1Inst <vop1<0x2e, 0x24>, "v_rsq_f32",
1296 VOP_F32_F32, AMDGPUrsq
1299 } //let SchedRW = [WriteQuarterRate32]
1301 let SchedRW = [WriteDouble] in {
1303 defm V_RCP_F64 : VOP1Inst <vop1<0x2f, 0x25>, "v_rcp_f64",
1304 VOP_F64_F64, AMDGPUrcp
1306 defm V_RSQ_F64 : VOP1Inst <vop1<0x31, 0x26>, "v_rsq_f64",
1307 VOP_F64_F64, AMDGPUrsq
1310 } // let SchedRW = [WriteDouble];
1312 defm V_SQRT_F32 : VOP1Inst <vop1<0x33, 0x27>, "v_sqrt_f32",
1316 let SchedRW = [WriteDouble] in {
1318 defm V_SQRT_F64 : VOP1Inst <vop1<0x34, 0x28>, "v_sqrt_f64",
1322 } // let SchedRW = [WriteDouble]
1324 defm V_SIN_F32 : VOP1Inst <vop1<0x35, 0x29>, "v_sin_f32",
1325 VOP_F32_F32, AMDGPUsin
1327 defm V_COS_F32 : VOP1Inst <vop1<0x36, 0x2a>, "v_cos_f32",
1328 VOP_F32_F32, AMDGPUcos
1330 defm V_NOT_B32 : VOP1Inst <vop1<0x37, 0x2b>, "v_not_b32", VOP_I32_I32>;
1331 defm V_BFREV_B32 : VOP1Inst <vop1<0x38, 0x2c>, "v_bfrev_b32", VOP_I32_I32>;
1332 defm V_FFBH_U32 : VOP1Inst <vop1<0x39, 0x2d>, "v_ffbh_u32", VOP_I32_I32>;
1333 defm V_FFBL_B32 : VOP1Inst <vop1<0x3a, 0x2e>, "v_ffbl_b32", VOP_I32_I32>;
1334 defm V_FFBH_I32 : VOP1Inst <vop1<0x3b, 0x2f>, "v_ffbh_i32", VOP_I32_I32>;
1335 //defm V_FREXP_EXP_I32_F64 : VOPInst <0x0000003c, "v_frexp_exp_i32_f64", VOP_I32_F32>;
1336 defm V_FREXP_MANT_F64 : VOP1Inst <vop1<0x3d, 0x31>, "v_frexp_mant_f64",
1339 defm V_FRACT_F64 : VOP1Inst <vop1<0x3e, 0x32>, "v_fract_f64", VOP_F64_F64>;
1340 //defm V_FREXP_EXP_I32_F32 : VOPInst <0x0000003f, "v_frexp_exp_i32_f32", VOP_I32_F32>;
1341 defm V_FREXP_MANT_F32 : VOP1Inst <vop1<0x40, 0x34>, "v_frexp_mant_f32",
1344 //def V_CLREXCP : VOP1_ <0x00000041, "v_clrexcp", []>;
1345 defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42, 0x36>, "v_movreld_b32", VOP_I32_I32>;
1346 defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43, 0x37>, "v_movrels_b32", VOP_I32_I32>;
1347 defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44, 0x38>, "v_movrelsd_b32", VOP_I32_I32>;
1349 // These instruction only exist on SI and CI
1350 let SubtargetPredicate = isSICI in {
1352 let SchedRW = [WriteQuarterRate32] in {
1354 defm V_LOG_CLAMP_F32 : VOP1InstSI <vop1<0x26>, "v_log_clamp_f32", VOP_F32_F32>;
1355 defm V_RCP_CLAMP_F32 : VOP1InstSI <vop1<0x28>, "v_rcp_clamp_f32", VOP_F32_F32>;
1356 defm V_RCP_LEGACY_F32 : VOP1InstSI <vop1<0x29>, "v_rcp_legacy_f32", VOP_F32_F32>;
1357 defm V_RSQ_CLAMP_F32 : VOP1InstSI <vop1<0x2c>, "v_rsq_clamp_f32",
1358 VOP_F32_F32, AMDGPUrsq_clamped
1360 defm V_RSQ_LEGACY_F32 : VOP1InstSI <vop1<0x2d>, "v_rsq_legacy_f32",
1361 VOP_F32_F32, AMDGPUrsq_legacy
1364 } // End let SchedRW = [WriteQuarterRate32]
1366 let SchedRW = [WriteDouble] in {
1368 defm V_RCP_CLAMP_F64 : VOP1InstSI <vop1<0x30>, "v_rcp_clamp_f64", VOP_F64_F64>;
1369 defm V_RSQ_CLAMP_F64 : VOP1InstSI <vop1<0x32>, "v_rsq_clamp_f64",
1370 VOP_F64_F64, AMDGPUrsq_clamped
1373 } // End SchedRW = [WriteDouble]
1375 } // End SubtargetPredicate = isSICI
1377 //===----------------------------------------------------------------------===//
1378 // VINTRP Instructions
1379 //===----------------------------------------------------------------------===//
1381 // FIXME: Specify SchedRW for VINTRP insturctions.
1382 defm V_INTERP_P1_F32 : VINTRP_m <
1383 0x00000000, "v_interp_p1_f32",
1384 (outs VGPR_32:$dst),
1385 (ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1386 "v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [$m0]",
1389 defm V_INTERP_P2_F32 : VINTRP_m <
1390 0x00000001, "v_interp_p2_f32",
1391 (outs VGPR_32:$dst),
1392 (ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1393 "v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
1397 defm V_INTERP_MOV_F32 : VINTRP_m <
1398 0x00000002, "v_interp_mov_f32",
1399 (outs VGPR_32:$dst),
1400 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1401 "v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [$m0]",
1404 //===----------------------------------------------------------------------===//
1405 // VOP2 Instructions
1406 //===----------------------------------------------------------------------===//
1408 defm V_CNDMASK_B32_e64 : VOP3_m_nosrcmod <vop3<0x100>, (outs VGPR_32:$dst),
1409 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2),
1410 "v_cndmask_b32_e64 $dst, $src0, $src1, $src2",
1411 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))],
1412 "v_cndmask_b32_e64", 3
1416 let isCommutable = 1 in {
1417 defm V_ADD_F32 : VOP2Inst <vop2<0x3, 0x1>, "v_add_f32",
1418 VOP_F32_F32_F32, fadd
1421 defm V_SUB_F32 : VOP2Inst <vop2<0x4, 0x2>, "v_sub_f32", VOP_F32_F32_F32, fsub>;
1422 defm V_SUBREV_F32 : VOP2Inst <vop2<0x5, 0x3>, "v_subrev_f32",
1423 VOP_F32_F32_F32, null_frag, "v_sub_f32"
1425 } // End isCommutable = 1
1427 let isCommutable = 1 in {
1429 defm V_MUL_LEGACY_F32 : VOP2Inst <vop2<0x7, 0x4>, "v_mul_legacy_f32",
1430 VOP_F32_F32_F32, int_AMDGPU_mul
1433 defm V_MUL_F32 : VOP2Inst <vop2<0x8, 0x5>, "v_mul_f32",
1434 VOP_F32_F32_F32, fmul
1437 defm V_MUL_I32_I24 : VOP2Inst <vop2<0x9, 0x6>, "v_mul_i32_i24",
1438 VOP_I32_I32_I32, AMDGPUmul_i24
1440 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "v_mul_hi_i32_i24", []>;
1441 defm V_MUL_U32_U24 : VOP2Inst <vop2<0xb, 0x8>, "v_mul_u32_u24",
1442 VOP_I32_I32_I32, AMDGPUmul_u24
1444 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "v_mul_hi_u32_u24", []>;
1446 defm V_MIN_F32 : VOP2Inst <vop2<0xf, 0xa>, "v_min_f32", VOP_F32_F32_F32,
1448 defm V_MAX_F32 : VOP2Inst <vop2<0x10, 0xb>, "v_max_f32", VOP_F32_F32_F32,
1450 defm V_MIN_I32 : VOP2Inst <vop2<0x11, 0xc>, "v_min_i32", VOP_I32_I32_I32,
1453 defm V_MAX_I32 : VOP2Inst <vop2<0x12, 0xd>, "v_max_i32", VOP_I32_I32_I32,
1456 defm V_MIN_U32 : VOP2Inst <vop2<0x13, 0xe>, "v_min_u32", VOP_I32_I32_I32,
1459 defm V_MAX_U32 : VOP2Inst <vop2<0x14, 0xf>, "v_max_u32", VOP_I32_I32_I32,
1463 // No non-Rev Op on VI
1464 defm V_LSHRREV_B32 : VOP2Inst <
1465 vop2<0x16, 0x10>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag,
1466 "v_lshr_b32", "v_lshrrev_b32"
1469 // No non-Rev OP on VI
1470 defm V_ASHRREV_I32 : VOP2Inst <
1471 vop2<0x18, 0x11>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag,
1472 "v_ashr_i32", "v_ashrrev_i32"
1475 // No non-Rev OP on VI
1476 defm V_LSHLREV_B32 : VOP2Inst <
1477 vop2<0x1a, 0x12>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag,
1478 "v_lshl_b32", "v_lshlrev_b32"
1481 defm V_AND_B32 : VOP2Inst <vop2<0x1b, 0x13>, "v_and_b32",
1482 VOP_I32_I32_I32, and>;
1483 defm V_OR_B32 : VOP2Inst <vop2<0x1c, 0x14>, "v_or_b32",
1486 defm V_XOR_B32 : VOP2Inst <vop2<0x1d, 0x15>, "v_xor_b32",
1487 VOP_I32_I32_I32, xor
1490 defm V_MAC_F32 : VOP2Inst <vop2<0x1f, 0x16>, "v_mac_f32", VOP_F32_F32_F32>;
1491 } // End isCommutable = 1
1493 defm V_MADMK_F32 : VOP2Inst <vop2<0x20, 0x17>, "v_madmk_f32", VOP_F32_F32_F32>;
1495 let isCommutable = 1 in {
1496 defm V_MADAK_F32 : VOP2Inst <vop2<0x21, 0x18>, "v_madak_f32", VOP_F32_F32_F32>;
1497 } // End isCommutable = 1
1499 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
1500 // No patterns so that the scalar instructions are always selected.
1501 // The scalar versions will be replaced with vector when needed later.
1503 // V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in VI,
1504 // but the VI instructions behave the same as the SI versions.
1505 defm V_ADD_I32 : VOP2bInst <vop2<0x25, 0x19>, "v_add_i32",
1506 VOP_I32_I32_I32, add
1508 defm V_SUB_I32 : VOP2bInst <vop2<0x26, 0x1a>, "v_sub_i32",
1509 VOP_I32_I32_I32, sub
1512 defm V_SUBREV_I32 : VOP2bInst <vop2<0x27, 0x1b>, "v_subrev_i32",
1513 VOP_I32_I32_I32, null_frag, "v_sub_i32"
1516 let Uses = [VCC] in { // Carry-in comes from VCC
1517 defm V_ADDC_U32 : VOP2bInst <vop2<0x28, 0x1c>, "v_addc_u32",
1518 VOP_I32_I32_I32_VCC, adde
1520 defm V_SUBB_U32 : VOP2bInst <vop2<0x29, 0x1d>, "v_subb_u32",
1521 VOP_I32_I32_I32_VCC, sube
1523 defm V_SUBBREV_U32 : VOP2bInst <vop2<0x2a, 0x1e>, "v_subbrev_u32",
1524 VOP_I32_I32_I32_VCC, null_frag, "v_subb_u32"
1527 } // End Uses = [VCC]
1528 } // End isCommutable = 1, Defs = [VCC]
1530 defm V_READLANE_B32 : VOP2SI_3VI_m <
1531 vop3 <0x001, 0x289>,
1533 (outs SReg_32:$vdst),
1534 (ins VGPR_32:$src0, SSrc_32:$vsrc1),
1535 "v_readlane_b32 $vdst, $src0, $vsrc1"
1538 defm V_WRITELANE_B32 : VOP2SI_3VI_m <
1539 vop3 <0x002, 0x28a>,
1541 (outs VGPR_32:$vdst),
1542 (ins SReg_32:$src0, SSrc_32:$vsrc1),
1543 "v_writelane_b32 $vdst, $src0, $vsrc1"
1546 // These instructions only exist on SI and CI
1547 let SubtargetPredicate = isSICI in {
1549 let isCommutable = 1 in {
1550 defm V_MAC_LEGACY_F32 : VOP2Inst <vop2<0x6>, "v_mac_legacy_f32",
1553 } // End isCommutable = 1
1555 defm V_MIN_LEGACY_F32 : VOP2Inst <vop2<0xd>, "v_min_legacy_f32",
1556 VOP_F32_F32_F32, AMDGPUfmin_legacy
1558 defm V_MAX_LEGACY_F32 : VOP2Inst <vop2<0xe>, "v_max_legacy_f32",
1559 VOP_F32_F32_F32, AMDGPUfmax_legacy
1562 let isCommutable = 1 in {
1563 defm V_LSHR_B32 : VOP2Inst <vop2<0x15>, "v_lshr_b32", VOP_I32_I32_I32, srl>;
1564 defm V_ASHR_I32 : VOP2Inst <vop2<0x17>, "v_ashr_i32",
1565 VOP_I32_I32_I32, sra
1568 let hasPostISelHook = 1 in {
1569 defm V_LSHL_B32 : VOP2Inst <vop2<0x19>, "v_lshl_b32", VOP_I32_I32_I32, shl>;
1572 } // End isCommutable = 1
1573 } // End let SubtargetPredicate = SICI
1575 defm V_BFM_B32 : VOP2_VI3_Inst <vop23<0x1e, 0x293>, "v_bfm_b32", VOP_I32_I32_I32,
1578 defm V_BCNT_U32_B32 : VOP2_VI3_Inst <vop23<0x22, 0x28b>, "v_bcnt_u32_b32",
1581 defm V_MBCNT_LO_U32_B32 : VOP2_VI3_Inst <vop23<0x23, 0x28c>, "v_mbcnt_lo_u32_b32",
1584 defm V_MBCNT_HI_U32_B32 : VOP2_VI3_Inst <vop23<0x24, 0x28d>, "v_mbcnt_hi_u32_b32",
1587 defm V_LDEXP_F32 : VOP2_VI3_Inst <vop23<0x2b, 0x288>, "v_ldexp_f32",
1588 VOP_F32_F32_I32, AMDGPUldexp
1591 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "v_cvt_pkaccum_u8_f32", []>;
1592 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "v_cvt_pknorm_i16_f32", []>;
1593 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "v_cvt_pknorm_u16_f32", []>;
1594 defm V_CVT_PKRTZ_F16_F32 : VOP2_VI3_Inst <vop23<0x2f, 0x296>, "v_cvt_pkrtz_f16_f32",
1595 VOP_I32_F32_F32, int_SI_packf16
1597 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "v_cvt_pk_u16_u32", []>;
1598 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "v_cvt_pk_i16_i32", []>;
1600 //===----------------------------------------------------------------------===//
1601 // VOP3 Instructions
1602 //===----------------------------------------------------------------------===//
1604 let isCommutable = 1 in {
1605 defm V_MAD_LEGACY_F32 : VOP3Inst <vop3<0x140, 0x1c0>, "v_mad_legacy_f32",
1609 defm V_MAD_F32 : VOP3Inst <vop3<0x141, 0x1c1>, "v_mad_f32",
1610 VOP_F32_F32_F32_F32, fmad
1613 defm V_MAD_I32_I24 : VOP3Inst <vop3<0x142, 0x1c2>, "v_mad_i32_i24",
1614 VOP_I32_I32_I32_I32, AMDGPUmad_i24
1616 defm V_MAD_U32_U24 : VOP3Inst <vop3<0x143, 0x1c3>, "v_mad_u32_u24",
1617 VOP_I32_I32_I32_I32, AMDGPUmad_u24
1619 } // End isCommutable = 1
1621 defm V_CUBEID_F32 : VOP3Inst <vop3<0x144, 0x1c4>, "v_cubeid_f32",
1624 defm V_CUBESC_F32 : VOP3Inst <vop3<0x145, 0x1c5>, "v_cubesc_f32",
1627 defm V_CUBETC_F32 : VOP3Inst <vop3<0x146, 0x1c6>, "v_cubetc_f32",
1630 defm V_CUBEMA_F32 : VOP3Inst <vop3<0x147, 0x1c7>, "v_cubema_f32",
1634 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
1635 defm V_BFE_U32 : VOP3Inst <vop3<0x148, 0x1c8>, "v_bfe_u32",
1636 VOP_I32_I32_I32_I32, AMDGPUbfe_u32
1638 defm V_BFE_I32 : VOP3Inst <vop3<0x149, 0x1c9>, "v_bfe_i32",
1639 VOP_I32_I32_I32_I32, AMDGPUbfe_i32
1643 defm V_BFI_B32 : VOP3Inst <vop3<0x14a, 0x1ca>, "v_bfi_b32",
1644 VOP_I32_I32_I32_I32, AMDGPUbfi
1647 let isCommutable = 1 in {
1648 defm V_FMA_F32 : VOP3Inst <vop3<0x14b, 0x1cb>, "v_fma_f32",
1649 VOP_F32_F32_F32_F32, fma
1651 defm V_FMA_F64 : VOP3Inst <vop3<0x14c, 0x1cc>, "v_fma_f64",
1652 VOP_F64_F64_F64_F64, fma
1654 } // End isCommutable = 1
1656 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "v_lerp_u8", []>;
1657 defm V_ALIGNBIT_B32 : VOP3Inst <vop3<0x14e, 0x1ce>, "v_alignbit_b32",
1660 defm V_ALIGNBYTE_B32 : VOP3Inst <vop3<0x14f, 0x1cf>, "v_alignbyte_b32",
1664 defm V_MIN3_F32 : VOP3Inst <vop3<0x151>, "v_min3_f32",
1665 VOP_F32_F32_F32_F32, AMDGPUfmin3>;
1667 defm V_MIN3_I32 : VOP3Inst <vop3<0x152>, "v_min3_i32",
1668 VOP_I32_I32_I32_I32, AMDGPUsmin3
1670 defm V_MIN3_U32 : VOP3Inst <vop3<0x153>, "v_min3_u32",
1671 VOP_I32_I32_I32_I32, AMDGPUumin3
1673 defm V_MAX3_F32 : VOP3Inst <vop3<0x154>, "v_max3_f32",
1674 VOP_F32_F32_F32_F32, AMDGPUfmax3
1676 defm V_MAX3_I32 : VOP3Inst <vop3<0x155>, "v_max3_i32",
1677 VOP_I32_I32_I32_I32, AMDGPUsmax3
1679 defm V_MAX3_U32 : VOP3Inst <vop3<0x156>, "v_max3_u32",
1680 VOP_I32_I32_I32_I32, AMDGPUumax3
1682 //def V_MED3_F32 : VOP3_MED3 <0x00000157, "v_med3_f32", []>;
1683 //def V_MED3_I32 : VOP3_MED3 <0x00000158, "v_med3_i32", []>;
1684 //def V_MED3_U32 : VOP3_MED3 <0x00000159, "v_med3_u32", []>;
1685 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "v_sad_u8", []>;
1686 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "v_sad_hi_u8", []>;
1687 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "v_sad_u16", []>;
1688 defm V_SAD_U32 : VOP3Inst <vop3<0x15d, 0x1dc>, "v_sad_u32",
1691 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "v_cvt_pk_u8_f32", []>;
1692 defm V_DIV_FIXUP_F32 : VOP3Inst <
1693 vop3<0x15f, 0x1de>, "v_div_fixup_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup
1696 let SchedRW = [WriteDouble] in {
1698 defm V_DIV_FIXUP_F64 : VOP3Inst <
1699 vop3<0x160, 0x1df>, "v_div_fixup_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup
1702 } // let SchedRW = [WriteDouble]
1704 let SchedRW = [WriteDouble] in {
1705 let isCommutable = 1 in {
1707 defm V_ADD_F64 : VOP3Inst <vop3<0x164, 0x280>, "v_add_f64",
1708 VOP_F64_F64_F64, fadd
1710 defm V_MUL_F64 : VOP3Inst <vop3<0x165, 0x281>, "v_mul_f64",
1711 VOP_F64_F64_F64, fmul
1714 defm V_MIN_F64 : VOP3Inst <vop3<0x166, 0x282>, "v_min_f64",
1715 VOP_F64_F64_F64, fminnum
1717 defm V_MAX_F64 : VOP3Inst <vop3<0x167, 0x283>, "v_max_f64",
1718 VOP_F64_F64_F64, fmaxnum
1721 } // isCommutable = 1
1723 defm V_LDEXP_F64 : VOP3Inst <vop3<0x168, 0x284>, "v_ldexp_f64",
1724 VOP_F64_F64_I32, AMDGPUldexp
1727 } // let SchedRW = [WriteDouble]
1729 let isCommutable = 1, SchedRW = [WriteQuarterRate32] in {
1731 defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169, 0x285>, "v_mul_lo_u32",
1734 defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a, 0x286>, "v_mul_hi_u32",
1738 defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b, 0x285>, "v_mul_lo_i32",
1741 defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32",
1745 } // isCommutable = 1, SchedRW = [WriteQuarterRate32]
1747 defm V_DIV_SCALE_F32 : VOP3b_32 <vop3<0x16d, 0x1e0>, "v_div_scale_f32", []>;
1749 let SchedRW = [WriteDouble] in {
1750 // Double precision division pre-scale.
1751 defm V_DIV_SCALE_F64 : VOP3b_64 <vop3<0x16e, 0x1e1>, "v_div_scale_f64", []>;
1752 } // let SchedRW = [WriteDouble]
1754 let isCommutable = 1 in {
1755 defm V_DIV_FMAS_F32 : VOP3Inst <vop3<0x16f, 0x1e2>, "v_div_fmas_f32",
1756 VOP_F32_F32_F32_F32, AMDGPUdiv_fmas
1758 let SchedRW = [WriteDouble] in {
1759 defm V_DIV_FMAS_F64 : VOP3Inst <vop3<0x170, 0x1e3>, "v_div_fmas_f64",
1760 VOP_F64_F64_F64_F64, AMDGPUdiv_fmas
1762 } // End SchedRW = [WriteDouble]
1763 } // End isCommutable = 1
1765 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "v_msad_u8", []>;
1766 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "v_qsad_u8", []>;
1767 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "v_mqsad_u8", []>;
1769 let SchedRW = [WriteDouble] in {
1770 defm V_TRIG_PREOP_F64 : VOP3Inst <
1771 vop3<0x174, 0x292>, "v_trig_preop_f64", VOP_F64_F64_I32, AMDGPUtrig_preop
1774 } // let SchedRW = [WriteDouble]
1776 // These instructions only exist on SI and CI
1777 let SubtargetPredicate = isSICI in {
1779 defm V_LSHL_B64 : VOP3Inst <vop3<0x161>, "v_lshl_b64",
1780 VOP_I64_I64_I32, shl
1783 defm V_LSHR_B64 : VOP3Inst <vop3<0x162>, "v_lshr_b64",
1784 VOP_I64_I64_I32, srl
1787 defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "v_ashr_i64",
1788 VOP_I64_I64_I32, sra
1791 defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "v_mullit_f32",
1792 VOP_F32_F32_F32_F32>;
1794 } // End SubtargetPredicate = isSICI
1796 //===----------------------------------------------------------------------===//
1797 // Pseudo Instructions
1798 //===----------------------------------------------------------------------===//
1799 let isCodeGenOnly = 1, isPseudo = 1 in {
1801 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
1802 // 64-bit vector move instruction. This is mainly used by the SIFoldOperands
1803 // pass to enable folding of inline immediates.
1804 def V_MOV_B64_PSEUDO : InstSI <(outs VReg_64:$dst), (ins VSrc_64:$src0), "", []>;
1805 } // end let hasSideEffects = 0, mayLoad = 0, mayStore = 0
1807 let hasSideEffects = 1 in {
1808 def SGPR_USE : InstSI <(outs),(ins), "", []>;
1811 // SI pseudo instructions. These are used by the CFG structurizer pass
1812 // and should be lowered to ISA instructions prior to codegen.
1814 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
1815 Uses = [EXEC], Defs = [EXEC] in {
1817 let isBranch = 1, isTerminator = 1 in {
1820 (outs SReg_64:$dst),
1821 (ins SReg_64:$vcc, brtarget:$target),
1823 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
1826 def SI_ELSE : InstSI <
1827 (outs SReg_64:$dst),
1828 (ins SReg_64:$src, brtarget:$target),
1830 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]
1832 let Constraints = "$src = $dst";
1835 def SI_LOOP : InstSI <
1837 (ins SReg_64:$saved, brtarget:$target),
1838 "si_loop $saved, $target",
1839 [(int_SI_loop i64:$saved, bb:$target)]
1842 } // end isBranch = 1, isTerminator = 1
1844 def SI_BREAK : InstSI <
1845 (outs SReg_64:$dst),
1847 "si_else $dst, $src",
1848 [(set i64:$dst, (int_SI_break i64:$src))]
1851 def SI_IF_BREAK : InstSI <
1852 (outs SReg_64:$dst),
1853 (ins SReg_64:$vcc, SReg_64:$src),
1854 "si_if_break $dst, $vcc, $src",
1855 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))]
1858 def SI_ELSE_BREAK : InstSI <
1859 (outs SReg_64:$dst),
1860 (ins SReg_64:$src0, SReg_64:$src1),
1861 "si_else_break $dst, $src0, $src1",
1862 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))]
1865 def SI_END_CF : InstSI <
1867 (ins SReg_64:$saved),
1869 [(int_SI_end_cf i64:$saved)]
1872 def SI_KILL : InstSI <
1876 [(int_AMDGPU_kill f32:$src)]
1879 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
1880 // Uses = [EXEC], Defs = [EXEC]
1882 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
1884 //defm SI_ : RegisterLoadStore <VGPR_32, FRAMEri, ADDRIndirect>;
1886 let UseNamedOperandTable = 1 in {
1888 def SI_RegisterLoad : InstSI <
1889 (outs VGPR_32:$dst, SReg_64:$temp),
1890 (ins FRAMEri32:$addr, i32imm:$chan),
1893 let isRegisterLoad = 1;
1897 class SIRegStore<dag outs> : InstSI <
1899 (ins VGPR_32:$val, FRAMEri32:$addr, i32imm:$chan),
1902 let isRegisterStore = 1;
1906 let usesCustomInserter = 1 in {
1907 def SI_RegisterStorePseudo : SIRegStore<(outs)>;
1908 } // End usesCustomInserter = 1
1909 def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>;
1912 } // End UseNamedOperandTable = 1
1914 def SI_INDIRECT_SRC : InstSI <
1915 (outs VGPR_32:$dst, SReg_64:$temp),
1916 (ins unknown:$src, VSrc_32:$idx, i32imm:$off),
1917 "si_indirect_src $dst, $temp, $src, $idx, $off",
1921 class SI_INDIRECT_DST<RegisterClass rc> : InstSI <
1922 (outs rc:$dst, SReg_64:$temp),
1923 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VGPR_32:$val),
1924 "si_indirect_dst $dst, $temp, $src, $idx, $off, $val",
1927 let Constraints = "$src = $dst";
1930 def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VGPR_32>;
1931 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
1932 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
1933 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
1934 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
1936 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
1938 let usesCustomInserter = 1 in {
1940 def V_SUB_F64 : InstSI <
1941 (outs VReg_64:$dst),
1942 (ins VReg_64:$src0, VReg_64:$src1),
1943 "v_sub_f64 $dst, $src0, $src1",
1944 [(set f64:$dst, (fsub f64:$src0, f64:$src1))]
1947 } // end usesCustomInserter
1949 multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
1951 let UseNamedOperandTable = 1 in {
1952 def _SAVE : InstSI <
1954 (ins sgpr_class:$src, i32imm:$frame_idx, SReg_128:$scratch_rsrc,
1955 SReg_32:$scratch_offset),
1959 def _RESTORE : InstSI <
1960 (outs sgpr_class:$dst),
1961 (ins i32imm:$frame_idx, SReg_128:$scratch_rsrc, SReg_32:$scratch_offset),
1964 } // End UseNamedOperandTable = 1
1967 defm SI_SPILL_S32 : SI_SPILL_SGPR <SReg_32>;
1968 defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
1969 defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
1970 defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
1971 defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
1973 multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> {
1974 let UseNamedOperandTable = 1 in {
1975 def _SAVE : InstSI <
1977 (ins vgpr_class:$src, i32imm:$frame_idx, SReg_128:$scratch_rsrc,
1978 SReg_32:$scratch_offset),
1982 def _RESTORE : InstSI <
1983 (outs vgpr_class:$dst),
1984 (ins i32imm:$frame_idx, SReg_128:$scratch_rsrc, SReg_32:$scratch_offset),
1987 } // End UseNamedOperandTable = 1
1990 defm SI_SPILL_V32 : SI_SPILL_VGPR <VGPR_32>;
1991 defm SI_SPILL_V64 : SI_SPILL_VGPR <VReg_64>;
1992 defm SI_SPILL_V96 : SI_SPILL_VGPR <VReg_96>;
1993 defm SI_SPILL_V128 : SI_SPILL_VGPR <VReg_128>;
1994 defm SI_SPILL_V256 : SI_SPILL_VGPR <VReg_256>;
1995 defm SI_SPILL_V512 : SI_SPILL_VGPR <VReg_512>;
1997 let Defs = [SCC] in {
1999 def SI_CONSTDATA_PTR : InstSI <
2000 (outs SReg_64:$dst),
2002 "", [(set SReg_64:$dst, (i64 SIconstdata_ptr))]
2005 } // End Defs = [SCC]
2007 } // end IsCodeGenOnly, isPseudo
2009 } // end SubtargetPredicate = isGCN
2011 let Predicates = [isGCN] in {
2014 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2),
2015 (V_CNDMASK_B32_e64 $src2, $src1,
2016 (V_CMP_GT_F32_e64 SRCMODS.NONE, 0, SRCMODS.NONE, $src0,
2017 DSTCLAMP.NONE, DSTOMOD.NONE))
2022 (SI_KILL 0xbf800000)
2025 let Predicates = [isSICI] in {
2027 /* int_SI_vs_load_input */
2029 (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
2030 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
2033 } // End Predicates = [isSICI]
2037 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
2038 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
2039 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
2040 $src0, $src1, $src2, $src3)
2043 //===----------------------------------------------------------------------===//
2045 //===----------------------------------------------------------------------===//
2047 multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
2049 // 1. SI-CI: Offset as 8bit DWORD immediate
2051 (constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))),
2052 (vt (Instr_IMM $sbase, (as_dword_i32imm $offset)))
2055 // 2. Offset loaded in an 32bit SGPR
2057 (constant_load (add i64:$sbase, (i64 IMM32bit:$offset))),
2058 (vt (Instr_SGPR $sbase, (S_MOV_B32 (i32 (as_i32imm $offset)))))
2061 // 3. No offset at all
2063 (constant_load i64:$sbase),
2064 (vt (Instr_IMM $sbase, 0))
2068 multiclass SMRD_Pattern_vi <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
2070 // 1. VI: Offset as 20bit immediate in bytes
2072 (constant_load (add i64:$sbase, (i64 IMM20bit:$offset))),
2073 (vt (Instr_IMM $sbase, (as_i32imm $offset)))
2076 // 2. Offset loaded in an 32bit SGPR
2078 (constant_load (add i64:$sbase, (i64 IMM32bit:$offset))),
2079 (vt (Instr_SGPR $sbase, (S_MOV_B32 (i32 (as_i32imm $offset)))))
2082 // 3. No offset at all
2084 (constant_load i64:$sbase),
2085 (vt (Instr_IMM $sbase, 0))
2089 let Predicates = [isSICI] in {
2090 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
2091 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
2092 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
2093 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
2094 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
2095 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
2096 defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
2097 } // End Predicates = [isSICI]
2099 let Predicates = [isVI] in {
2100 defm : SMRD_Pattern_vi <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
2101 defm : SMRD_Pattern_vi <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
2102 defm : SMRD_Pattern_vi <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
2103 defm : SMRD_Pattern_vi <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
2104 defm : SMRD_Pattern_vi <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
2105 defm : SMRD_Pattern_vi <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
2106 defm : SMRD_Pattern_vi <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
2107 } // End Predicates = [isVI]
2109 let Predicates = [isSICI] in {
2111 // 1. Offset as 8bit DWORD immediate
2113 (SIload_constant v4i32:$sbase, IMM8bitDWORD:$offset),
2114 (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset))
2117 } // End Predicates = [isSICI]
2119 // 2. Offset loaded in an 32bit SGPR
2121 (SIload_constant v4i32:$sbase, imm:$offset),
2122 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
2125 //===----------------------------------------------------------------------===//
2127 //===----------------------------------------------------------------------===//
2130 (i64 (ctpop i64:$src)),
2131 (i64 (REG_SEQUENCE SReg_64,
2132 (S_BCNT1_I32_B64 $src), sub0,
2133 (S_MOV_B32 0), sub1))
2136 //===----------------------------------------------------------------------===//
2138 //===----------------------------------------------------------------------===//
2140 // V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector
2141 // case, the sgpr-copies pass will fix this to use the vector version.
2143 (i32 (addc i32:$src0, i32:$src1)),
2144 (S_ADD_U32 $src0, $src1)
2147 //===----------------------------------------------------------------------===//
2149 //===----------------------------------------------------------------------===//
2152 (int_AMDGPU_barrier_global),
2156 //===----------------------------------------------------------------------===//
2158 //===----------------------------------------------------------------------===//
2160 let Predicates = [UnsafeFPMath] in {
2161 def : RcpPat<V_RCP_F64_e32, f64>;
2162 defm : RsqPat<V_RSQ_F64_e32, f64>;
2163 defm : RsqPat<V_RSQ_F32_e32, f32>;
2166 //===----------------------------------------------------------------------===//
2168 //===----------------------------------------------------------------------===//
2171 (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)),
2172 (V_BCNT_U32_B32_e64 $popcnt, $val)
2175 /********** ======================= **********/
2176 /********** Image sampling patterns **********/
2177 /********** ======================= **********/
2180 class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
2181 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm,
2182 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
2183 (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
2184 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
2185 $addr, $rsrc, $sampler)
2188 multiclass SampleRawPatterns<SDPatternOperator name, string opcode> {
2189 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
2190 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
2191 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
2192 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>;
2193 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>;
2197 class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
2198 (name vt:$addr, v8i32:$rsrc, i32:$dmask, i32:$unorm,
2199 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
2200 (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
2201 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
2205 multiclass ImagePatterns<SDPatternOperator name, string opcode> {
2206 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
2207 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
2208 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
2212 defm : SampleRawPatterns<int_SI_image_sample, "IMAGE_SAMPLE">;
2213 defm : SampleRawPatterns<int_SI_image_sample_cl, "IMAGE_SAMPLE_CL">;
2214 defm : SampleRawPatterns<int_SI_image_sample_d, "IMAGE_SAMPLE_D">;
2215 defm : SampleRawPatterns<int_SI_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">;
2216 defm : SampleRawPatterns<int_SI_image_sample_l, "IMAGE_SAMPLE_L">;
2217 defm : SampleRawPatterns<int_SI_image_sample_b, "IMAGE_SAMPLE_B">;
2218 defm : SampleRawPatterns<int_SI_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">;
2219 defm : SampleRawPatterns<int_SI_image_sample_lz, "IMAGE_SAMPLE_LZ">;
2220 defm : SampleRawPatterns<int_SI_image_sample_cd, "IMAGE_SAMPLE_CD">;
2221 defm : SampleRawPatterns<int_SI_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">;
2223 // Sample with comparison
2224 defm : SampleRawPatterns<int_SI_image_sample_c, "IMAGE_SAMPLE_C">;
2225 defm : SampleRawPatterns<int_SI_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">;
2226 defm : SampleRawPatterns<int_SI_image_sample_c_d, "IMAGE_SAMPLE_C_D">;
2227 defm : SampleRawPatterns<int_SI_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">;
2228 defm : SampleRawPatterns<int_SI_image_sample_c_l, "IMAGE_SAMPLE_C_L">;
2229 defm : SampleRawPatterns<int_SI_image_sample_c_b, "IMAGE_SAMPLE_C_B">;
2230 defm : SampleRawPatterns<int_SI_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">;
2231 defm : SampleRawPatterns<int_SI_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">;
2232 defm : SampleRawPatterns<int_SI_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">;
2233 defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">;
2235 // Sample with offsets
2236 defm : SampleRawPatterns<int_SI_image_sample_o, "IMAGE_SAMPLE_O">;
2237 defm : SampleRawPatterns<int_SI_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">;
2238 defm : SampleRawPatterns<int_SI_image_sample_d_o, "IMAGE_SAMPLE_D_O">;
2239 defm : SampleRawPatterns<int_SI_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">;
2240 defm : SampleRawPatterns<int_SI_image_sample_l_o, "IMAGE_SAMPLE_L_O">;
2241 defm : SampleRawPatterns<int_SI_image_sample_b_o, "IMAGE_SAMPLE_B_O">;
2242 defm : SampleRawPatterns<int_SI_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">;
2243 defm : SampleRawPatterns<int_SI_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">;
2244 defm : SampleRawPatterns<int_SI_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">;
2245 defm : SampleRawPatterns<int_SI_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">;
2247 // Sample with comparison and offsets
2248 defm : SampleRawPatterns<int_SI_image_sample_c_o, "IMAGE_SAMPLE_C_O">;
2249 defm : SampleRawPatterns<int_SI_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">;
2250 defm : SampleRawPatterns<int_SI_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">;
2251 defm : SampleRawPatterns<int_SI_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">;
2252 defm : SampleRawPatterns<int_SI_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">;
2253 defm : SampleRawPatterns<int_SI_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">;
2254 defm : SampleRawPatterns<int_SI_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">;
2255 defm : SampleRawPatterns<int_SI_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">;
2256 defm : SampleRawPatterns<int_SI_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">;
2257 defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">;
2260 // Only the variants which make sense are defined.
2261 def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V2, v2i32>;
2262 def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V4, v4i32>;
2263 def : SampleRawPattern<int_SI_gather4_cl, IMAGE_GATHER4_CL_V4_V4, v4i32>;
2264 def : SampleRawPattern<int_SI_gather4_l, IMAGE_GATHER4_L_V4_V4, v4i32>;
2265 def : SampleRawPattern<int_SI_gather4_b, IMAGE_GATHER4_B_V4_V4, v4i32>;
2266 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V4, v4i32>;
2267 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>;
2268 def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V2, v2i32>;
2269 def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V4, v4i32>;
2271 def : SampleRawPattern<int_SI_gather4_c, IMAGE_GATHER4_C_V4_V4, v4i32>;
2272 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V4, v4i32>;
2273 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>;
2274 def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V4, v4i32>;
2275 def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8i32>;
2276 def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V4, v4i32>;
2277 def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8i32>;
2278 def : SampleRawPattern<int_SI_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8i32>;
2279 def : SampleRawPattern<int_SI_gather4_c_lz, IMAGE_GATHER4_C_LZ_V4_V4, v4i32>;
2281 def : SampleRawPattern<int_SI_gather4_o, IMAGE_GATHER4_O_V4_V4, v4i32>;
2282 def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V4, v4i32>;
2283 def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8i32>;
2284 def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V4, v4i32>;
2285 def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8i32>;
2286 def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V4, v4i32>;
2287 def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8i32>;
2288 def : SampleRawPattern<int_SI_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8i32>;
2289 def : SampleRawPattern<int_SI_gather4_lz_o, IMAGE_GATHER4_LZ_O_V4_V4, v4i32>;
2291 def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V4, v4i32>;
2292 def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V8, v8i32>;
2293 def : SampleRawPattern<int_SI_gather4_c_cl_o, IMAGE_GATHER4_C_CL_O_V4_V8, v8i32>;
2294 def : SampleRawPattern<int_SI_gather4_c_l_o, IMAGE_GATHER4_C_L_O_V4_V8, v8i32>;
2295 def : SampleRawPattern<int_SI_gather4_c_b_o, IMAGE_GATHER4_C_B_O_V4_V8, v8i32>;
2296 def : SampleRawPattern<int_SI_gather4_c_b_cl_o, IMAGE_GATHER4_C_B_CL_O_V4_V8, v8i32>;
2297 def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V4, v4i32>;
2298 def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V8, v8i32>;
2300 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V1, i32>;
2301 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V2, v2i32>;
2302 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V4, v4i32>;
2304 def : ImagePattern<int_SI_getresinfo, IMAGE_GET_RESINFO_V4_V1, i32>;
2305 defm : ImagePatterns<int_SI_image_load, "IMAGE_LOAD">;
2306 defm : ImagePatterns<int_SI_image_load_mip, "IMAGE_LOAD_MIP">;
2308 /* SIsample for simple 1D texture lookup */
2310 (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2311 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2314 class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2315 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2316 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2319 class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2320 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT),
2321 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2324 class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2325 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY),
2326 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2329 class SampleShadowPattern<SDNode name, MIMG opcode,
2330 ValueType vt> : Pat <
2331 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW),
2332 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2335 class SampleShadowArrayPattern<SDNode name, MIMG opcode,
2336 ValueType vt> : Pat <
2337 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
2338 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2341 /* SIsample* for texture lookups consuming more address parameters */
2342 multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
2343 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
2344 MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
2345 def : SamplePattern <SIsample, sample, addr_type>;
2346 def : SampleRectPattern <SIsample, sample, addr_type>;
2347 def : SampleArrayPattern <SIsample, sample, addr_type>;
2348 def : SampleShadowPattern <SIsample, sample_c, addr_type>;
2349 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
2351 def : SamplePattern <SIsamplel, sample_l, addr_type>;
2352 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
2353 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
2354 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
2356 def : SamplePattern <SIsampleb, sample_b, addr_type>;
2357 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
2358 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
2359 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
2361 def : SamplePattern <SIsampled, sample_d, addr_type>;
2362 def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
2363 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
2364 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
2367 defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
2368 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
2369 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
2370 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
2372 defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
2373 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
2374 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
2375 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
2377 defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
2378 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
2379 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
2380 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
2382 defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
2383 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
2384 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
2385 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
2388 /* int_SI_imageload for texture fetches consuming varying address parameters */
2389 class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2390 (name addr_type:$addr, v32i8:$rsrc, imm),
2391 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
2394 class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2395 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
2396 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
2399 class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2400 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
2401 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
2404 class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2405 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
2406 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
2409 multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> {
2410 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>;
2411 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>;
2414 multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> {
2415 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>;
2416 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>;
2419 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>;
2420 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>;
2422 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>;
2423 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>;
2425 /* Image resource information */
2427 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm),
2428 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2432 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY),
2433 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2437 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA),
2438 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2441 /********** ============================================ **********/
2442 /********** Extraction, Insertion, Building and Casting **********/
2443 /********** ============================================ **********/
2445 foreach Index = 0-2 in {
2446 def Extract_Element_v2i32_#Index : Extract_Element <
2447 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
2449 def Insert_Element_v2i32_#Index : Insert_Element <
2450 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
2453 def Extract_Element_v2f32_#Index : Extract_Element <
2454 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
2456 def Insert_Element_v2f32_#Index : Insert_Element <
2457 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
2461 foreach Index = 0-3 in {
2462 def Extract_Element_v4i32_#Index : Extract_Element <
2463 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
2465 def Insert_Element_v4i32_#Index : Insert_Element <
2466 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
2469 def Extract_Element_v4f32_#Index : Extract_Element <
2470 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
2472 def Insert_Element_v4f32_#Index : Insert_Element <
2473 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
2477 foreach Index = 0-7 in {
2478 def Extract_Element_v8i32_#Index : Extract_Element <
2479 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
2481 def Insert_Element_v8i32_#Index : Insert_Element <
2482 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
2485 def Extract_Element_v8f32_#Index : Extract_Element <
2486 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
2488 def Insert_Element_v8f32_#Index : Insert_Element <
2489 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
2493 foreach Index = 0-15 in {
2494 def Extract_Element_v16i32_#Index : Extract_Element <
2495 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
2497 def Insert_Element_v16i32_#Index : Insert_Element <
2498 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
2501 def Extract_Element_v16f32_#Index : Extract_Element <
2502 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
2504 def Insert_Element_v16f32_#Index : Insert_Element <
2505 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
2509 def : BitConvert <i32, f32, SReg_32>;
2510 def : BitConvert <i32, f32, VGPR_32>;
2512 def : BitConvert <f32, i32, SReg_32>;
2513 def : BitConvert <f32, i32, VGPR_32>;
2515 def : BitConvert <i64, f64, VReg_64>;
2517 def : BitConvert <f64, i64, VReg_64>;
2519 def : BitConvert <v2f32, v2i32, VReg_64>;
2520 def : BitConvert <v2i32, v2f32, VReg_64>;
2521 def : BitConvert <v2i32, i64, VReg_64>;
2522 def : BitConvert <i64, v2i32, VReg_64>;
2523 def : BitConvert <v2f32, i64, VReg_64>;
2524 def : BitConvert <i64, v2f32, VReg_64>;
2525 def : BitConvert <v2i32, f64, VReg_64>;
2526 def : BitConvert <f64, v2i32, VReg_64>;
2527 def : BitConvert <v4f32, v4i32, VReg_128>;
2528 def : BitConvert <v4i32, v4f32, VReg_128>;
2530 def : BitConvert <v8f32, v8i32, SReg_256>;
2531 def : BitConvert <v8i32, v8f32, SReg_256>;
2532 def : BitConvert <v8i32, v32i8, SReg_256>;
2533 def : BitConvert <v32i8, v8i32, SReg_256>;
2534 def : BitConvert <v8i32, v32i8, VReg_256>;
2535 def : BitConvert <v8i32, v8f32, VReg_256>;
2536 def : BitConvert <v8f32, v8i32, VReg_256>;
2537 def : BitConvert <v32i8, v8i32, VReg_256>;
2539 def : BitConvert <v16i32, v16f32, VReg_512>;
2540 def : BitConvert <v16f32, v16i32, VReg_512>;
2542 /********** =================== **********/
2543 /********** Src & Dst modifiers **********/
2544 /********** =================== **********/
2547 (AMDGPUclamp (VOP3Mods0Clamp f32:$src0, i32:$src0_modifiers, i32:$omod),
2548 (f32 FP_ZERO), (f32 FP_ONE)),
2549 (V_ADD_F32_e64 $src0_modifiers, $src0, 0, 0, 1, $omod)
2552 /********** ================================ **********/
2553 /********** Floating point absolute/negative **********/
2554 /********** ================================ **********/
2556 // Prevent expanding both fneg and fabs.
2558 // FIXME: Should use S_OR_B32
2560 (fneg (fabs f32:$src)),
2561 (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
2564 // FIXME: Should use S_OR_B32
2566 (fneg (fabs f64:$src)),
2567 (REG_SEQUENCE VReg_64,
2568 (i32 (EXTRACT_SUBREG f64:$src, sub0)),
2570 (V_OR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2571 (V_MOV_B32_e32 0x80000000)), // Set sign bit.
2577 (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff))
2582 (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000))
2587 (REG_SEQUENCE VReg_64,
2588 (i32 (EXTRACT_SUBREG f64:$src, sub0)),
2590 (V_AND_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2591 (V_MOV_B32_e32 0x7fffffff)), // Set sign bit.
2597 (REG_SEQUENCE VReg_64,
2598 (i32 (EXTRACT_SUBREG f64:$src, sub0)),
2600 (V_XOR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2601 (V_MOV_B32_e32 0x80000000)),
2605 /********** ================== **********/
2606 /********** Immediate Patterns **********/
2607 /********** ================== **********/
2610 (SGPRImm<(i32 imm)>:$imm),
2611 (S_MOV_B32 imm:$imm)
2615 (SGPRImm<(f32 fpimm)>:$imm),
2616 (S_MOV_B32 (f32 (bitcast_fpimm_to_i32 $imm)))
2621 (V_MOV_B32_e32 imm:$imm)
2626 (V_MOV_B32_e32 (f32 (bitcast_fpimm_to_i32 $imm)))
2630 (i64 InlineImm<i64>:$imm),
2631 (S_MOV_B64 InlineImm<i64>:$imm)
2634 // XXX - Should this use a s_cmp to set SCC?
2636 // Set to sign-extended 64-bit value (true = -1, false = 0)
2639 (S_MOV_B64 (i64 (as_i64imm $imm)))
2643 (f64 InlineFPImm<f64>:$imm),
2644 (S_MOV_B64 (f64 (bitcast_fpimm_to_i64 InlineFPImm<f64>:$imm)))
2647 /********** ===================== **********/
2648 /********** Interpolation Paterns **********/
2649 /********** ===================== **********/
2651 // The value of $params is constant through out the entire kernel.
2652 // We need to use S_MOV_B32 $params, because CSE ignores copies, so
2653 // without it we end up with a lot of redundant moves.
2656 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params),
2657 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, (S_MOV_B32 $params))
2661 (int_SI_fs_interp imm:$attr_chan, imm:$attr, i32:$params, v2i32:$ij),
2662 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0),
2663 imm:$attr_chan, imm:$attr, (S_MOV_B32 $params)),
2664 (EXTRACT_SUBREG $ij, sub1),
2665 imm:$attr_chan, imm:$attr, (S_MOV_B32 $params))
2668 /********** ================== **********/
2669 /********** Intrinsic Patterns **********/
2670 /********** ================== **********/
2672 /* llvm.AMDGPU.pow */
2673 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
2676 (int_AMDGPU_div f32:$src0, f32:$src1),
2677 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1))
2681 (fdiv f64:$src0, f64:$src1),
2682 (V_MUL_F64 0 /* src0_modifiers */, $src0,
2683 0 /* src1_modifiers */, (V_RCP_F64_e32 $src1),
2684 0 /* clamp */, 0 /* omod */)
2688 (int_AMDGPU_cube v4f32:$src),
2689 (REG_SEQUENCE VReg_128,
2690 (V_CUBETC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
2691 0 /* src1_modifiers */, (EXTRACT_SUBREG $src, sub1),
2692 0 /* src2_modifiers */, (EXTRACT_SUBREG $src, sub2),
2693 0 /* clamp */, 0 /* omod */), sub0,
2694 (V_CUBESC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
2695 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2696 0 /* src2_modifiers */,(EXTRACT_SUBREG $src, sub2),
2697 0 /* clamp */, 0 /* omod */), sub1,
2698 (V_CUBEMA_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
2699 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2700 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
2701 0 /* clamp */, 0 /* omod */), sub2,
2702 (V_CUBEID_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
2703 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2704 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
2705 0 /* clamp */, 0 /* omod */), sub3)
2709 (i32 (sext i1:$src0)),
2710 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
2713 class Ext32Pat <SDNode ext> : Pat <
2714 (i32 (ext i1:$src0)),
2715 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
2718 def : Ext32Pat <zext>;
2719 def : Ext32Pat <anyext>;
2721 let Predicates = [isSICI] in {
2723 // Offset in an 32Bit VGPR
2725 (SIload_constant v4i32:$sbase, i32:$voff),
2726 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0, 0)
2729 } // End Predicates = [isSICI]
2731 // The multiplication scales from [0,1] to the unsigned integer range
2733 (AMDGPUurecip i32:$src0),
2735 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
2736 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
2741 (V_MBCNT_HI_U32_B32_e64 0xffffffff,
2742 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0))
2745 //===----------------------------------------------------------------------===//
2747 //===----------------------------------------------------------------------===//
2749 def : IMad24Pat<V_MAD_I32_I24>;
2750 def : UMad24Pat<V_MAD_U32_U24>;
2753 (mulhu i32:$src0, i32:$src1),
2754 (V_MUL_HI_U32 $src0, $src1)
2758 (mulhs i32:$src0, i32:$src1),
2759 (V_MUL_HI_I32 $src0, $src1)
2762 def : Vop3ModPat<V_MAD_F32, VOP_F32_F32_F32_F32, AMDGPUmad>;
2765 defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>;
2766 def : ROTRPattern <V_ALIGNBIT_B32>;
2768 /********** ======================= **********/
2769 /********** Load/Store Patterns **********/
2770 /********** ======================= **********/
2772 class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat <
2773 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
2774 (inst (i1 0), $ptr, (as_i16imm $offset), (S_MOV_B32 -1))
2777 def : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
2778 def : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
2779 def : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
2780 def : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
2781 def : DSReadPat <DS_READ_B32, i32, local_load>;
2783 let AddedComplexity = 100 in {
2785 def : DSReadPat <DS_READ_B64, v2i32, local_load_aligned8bytes>;
2787 } // End AddedComplexity = 100
2790 (v2i32 (local_load (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
2792 (DS_READ2_B32 (i1 0), $ptr, $offset0, $offset1, (S_MOV_B32 -1))
2795 class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat <
2796 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
2797 (inst (i1 0), $ptr, $value, (as_i16imm $offset), (S_MOV_B32 -1))
2800 def : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
2801 def : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
2802 def : DSWritePat <DS_WRITE_B32, i32, local_store>;
2804 let AddedComplexity = 100 in {
2806 def : DSWritePat <DS_WRITE_B64, v2i32, local_store_aligned8bytes>;
2807 } // End AddedComplexity = 100
2810 (local_store v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
2812 (DS_WRITE2_B32 (i1 0), $ptr, (EXTRACT_SUBREG $value, sub0),
2813 (EXTRACT_SUBREG $value, sub1), $offset0, $offset1,
2817 class DSAtomicRetPat<DS inst, ValueType vt, PatFrag frag> : Pat <
2818 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
2819 (inst (i1 0), $ptr, $value, (as_i16imm $offset), (S_MOV_B32 -1))
2822 // Special case of DSAtomicRetPat for add / sub 1 -> inc / dec
2824 // We need to use something for the data0, so we set a register to
2825 // -1. For the non-rtn variants, the manual says it does
2826 // DS[A] = (DS[A] >= D0) ? 0 : DS[A] + 1, and setting D0 to uint_max
2827 // will always do the increment so I'm assuming it's the same.
2829 // We also load this -1 with s_mov_b32 / s_mov_b64 even though this
2830 // needs to be a VGPR. The SGPR copy pass will fix this, and it's
2831 // easier since there is no v_mov_b64.
2832 class DSAtomicIncRetPat<DS inst, ValueType vt,
2833 Instruction LoadImm, PatFrag frag> : Pat <
2834 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), (vt 1)),
2835 (inst (i1 0), $ptr, (LoadImm (vt -1)), (as_i16imm $offset), (S_MOV_B32 -1))
2839 class DSAtomicCmpXChg <DS inst, ValueType vt, PatFrag frag> : Pat <
2840 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
2841 (inst (i1 0), $ptr, $cmp, $swap, (as_i16imm $offset), (S_MOV_B32 -1))
2846 def : DSAtomicIncRetPat<DS_INC_RTN_U32, i32,
2847 S_MOV_B32, atomic_load_add_local>;
2848 def : DSAtomicIncRetPat<DS_DEC_RTN_U32, i32,
2849 S_MOV_B32, atomic_load_sub_local>;
2851 def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, atomic_swap_local>;
2852 def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, atomic_load_add_local>;
2853 def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, atomic_load_sub_local>;
2854 def : DSAtomicRetPat<DS_AND_RTN_B32, i32, atomic_load_and_local>;
2855 def : DSAtomicRetPat<DS_OR_RTN_B32, i32, atomic_load_or_local>;
2856 def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, atomic_load_xor_local>;
2857 def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, atomic_load_min_local>;
2858 def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, atomic_load_max_local>;
2859 def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, atomic_load_umin_local>;
2860 def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, atomic_load_umax_local>;
2862 def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, atomic_cmp_swap_32_local>;
2865 def : DSAtomicIncRetPat<DS_INC_RTN_U64, i64,
2866 S_MOV_B64, atomic_load_add_local>;
2867 def : DSAtomicIncRetPat<DS_DEC_RTN_U64, i64,
2868 S_MOV_B64, atomic_load_sub_local>;
2870 def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, atomic_swap_local>;
2871 def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, atomic_load_add_local>;
2872 def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, atomic_load_sub_local>;
2873 def : DSAtomicRetPat<DS_AND_RTN_B64, i64, atomic_load_and_local>;
2874 def : DSAtomicRetPat<DS_OR_RTN_B64, i64, atomic_load_or_local>;
2875 def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, atomic_load_xor_local>;
2876 def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, atomic_load_min_local>;
2877 def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, atomic_load_max_local>;
2878 def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, atomic_load_umin_local>;
2879 def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, atomic_load_umax_local>;
2881 def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, atomic_cmp_swap_64_local>;
2884 //===----------------------------------------------------------------------===//
2886 //===----------------------------------------------------------------------===//
2888 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
2889 PatFrag constant_ld> {
2891 (vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))),
2892 (Instr_ADDR64 $srsrc, $vaddr, $offset)
2896 let Predicates = [isSICI] in {
2897 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>;
2898 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>;
2899 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>;
2900 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>;
2901 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32, constant_load>;
2902 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32, constant_load>;
2903 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32, constant_load>;
2904 } // End Predicates = [isSICI]
2906 class MUBUFScratchLoadPat <MUBUF Instr, ValueType vt, PatFrag ld> : Pat <
2907 (vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr,
2908 i32:$soffset, u16imm:$offset))),
2909 (Instr $srsrc, $vaddr, $soffset, $offset, 0, 0, 0)
2912 let Predicates = [isSICI] in {
2913 def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i32, sextloadi8_private>;
2914 def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i32, extloadi8_private>;
2915 def : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, i32, sextloadi16_private>;
2916 def : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, i32, extloadi16_private>;
2917 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, i32, load_private>;
2918 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, v2i32, load_private>;
2919 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, v4i32, load_private>;
2920 } // End Predicates = [isSICI]
2922 // BUFFER_LOAD_DWORD*, addr64=0
2923 multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
2927 (vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset,
2928 imm:$offset, 0, 0, imm:$glc, imm:$slc,
2930 (offset $rsrc, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2931 (as_i1imm $slc), (as_i1imm $tfe))
2935 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2936 imm:$offset, 1, 0, imm:$glc, imm:$slc,
2938 (offen $rsrc, $vaddr, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
2943 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2944 imm:$offset, 0, 1, imm:$glc, imm:$slc,
2946 (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2947 (as_i1imm $slc), (as_i1imm $tfe))
2951 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset,
2952 imm, 1, 1, imm:$glc, imm:$slc,
2954 (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2959 let Predicates = [isSICI] in {
2960 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
2961 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
2962 defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
2963 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
2964 defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
2965 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
2966 } // End Predicates = [isSICI]
2968 class MUBUFScratchStorePat <MUBUF Instr, ValueType vt, PatFrag st> : Pat <
2969 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset,
2971 (Instr $value, $srsrc, $vaddr, $soffset, $offset, 0, 0, 0)
2974 let Predicates = [isSICI] in {
2975 def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i32, truncstorei8_private>;
2976 def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i32, truncstorei16_private>;
2977 def : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, i32, store_private>;
2978 def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>;
2979 def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>;
2980 } // End Predicates = [isSICI]
2983 class MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> : Pat <
2984 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i64:$vaddr, u16imm:$offset)),
2985 (Instr $value, $srsrc, $vaddr, $offset)
2988 let Predicates = [isSICI] in {
2989 def : MUBUFStore_Pattern <BUFFER_STORE_BYTE_ADDR64, i32, truncstorei8_private>;
2990 def : MUBUFStore_Pattern <BUFFER_STORE_SHORT_ADDR64, i32, truncstorei16_private>;
2991 def : MUBUFStore_Pattern <BUFFER_STORE_DWORD_ADDR64, i32, store_private>;
2992 def : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2_ADDR64, v2i32, store_private>;
2993 def : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4_ADDR64, v4i32, store_private>;
2994 } // End Predicates = [isSICI]
2998 //===----------------------------------------------------------------------===//
3000 //===----------------------------------------------------------------------===//
3002 // TBUFFER_STORE_FORMAT_*, addr64=0
3003 class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
3004 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
3005 i32:$soffset, imm:$inst_offset, imm:$dfmt,
3006 imm:$nfmt, imm:$offen, imm:$idxen,
3007 imm:$glc, imm:$slc, imm:$tfe),
3009 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
3010 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
3011 (as_i1imm $slc), (as_i1imm $tfe), $soffset)
3014 def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
3015 def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
3016 def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
3017 def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
3019 let SubtargetPredicate = isCI in {
3021 defm V_QSAD_PK_U16_U8 : VOP3Inst <vop3<0x173>, "v_qsad_pk_u16_u8",
3024 defm V_MQSAD_U16_U8 : VOP3Inst <vop3<0x172>, "v_mqsad_u16_u8",
3027 defm V_MQSAD_U32_U8 : VOP3Inst <vop3<0x175>, "v_mqsad_u32_u8",
3031 let isCommutable = 1 in {
3032 defm V_MAD_U64_U32 : VOP3Inst <vop3<0x176>, "v_mad_u64_u32",
3036 // XXX - Does this set VCC?
3037 defm V_MAD_I64_I32 : VOP3Inst <vop3<0x177>, "v_mad_i64_i32",
3040 } // End isCommutable = 1
3042 // Remaining instructions:
3044 // S_CBRANCH_CDBGUSER
3045 // S_CBRANCH_CDBGSYS
3046 // S_CBRANCH_CDBGSYS_OR_USER
3047 // S_CBRANCH_CDBGSYS_AND_USER
3050 // DS_GWS_SEMA_RELEASE_ALL
3052 // DS_CNDXCHG32_RTN_B64
3055 // DS_CONDXCHG32_RTN_B128
3058 // BUFFER_LOAD_DWORDX3
3059 // BUFFER_STORE_DWORDX3
3063 //===----------------------------------------------------------------------===//
3065 //===----------------------------------------------------------------------===//
3067 class FLATLoad_Pattern <FLAT Instr_ADDR64, ValueType vt,
3069 Pat <(vt (flat_ld i64:$ptr)),
3073 def : FLATLoad_Pattern <FLAT_LOAD_SBYTE, i32, sextloadi8_flat>;
3074 def : FLATLoad_Pattern <FLAT_LOAD_UBYTE, i32, az_extloadi8_flat>;
3075 def : FLATLoad_Pattern <FLAT_LOAD_SSHORT, i32, sextloadi16_flat>;
3076 def : FLATLoad_Pattern <FLAT_LOAD_USHORT, i32, az_extloadi16_flat>;
3077 def : FLATLoad_Pattern <FLAT_LOAD_DWORD, i32, flat_load>;
3078 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, i64, flat_load>;
3079 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, i64, az_extloadi32_flat>;
3080 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, v2i32, flat_load>;
3081 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX4, v4i32, flat_load>;
3083 class FLATStore_Pattern <FLAT Instr, ValueType vt, PatFrag st> :
3084 Pat <(st vt:$value, i64:$ptr),
3085 (Instr $value, $ptr)
3088 def : FLATStore_Pattern <FLAT_STORE_BYTE, i32, truncstorei8_flat>;
3089 def : FLATStore_Pattern <FLAT_STORE_SHORT, i32, truncstorei16_flat>;
3090 def : FLATStore_Pattern <FLAT_STORE_DWORD, i32, flat_store>;
3091 def : FLATStore_Pattern <FLAT_STORE_DWORDX2, i64, flat_store>;
3092 def : FLATStore_Pattern <FLAT_STORE_DWORDX2, v2i32, flat_store>;
3093 def : FLATStore_Pattern <FLAT_STORE_DWORDX4, v4i32, flat_store>;
3095 /********** ====================== **********/
3096 /********** Indirect adressing **********/
3097 /********** ====================== **********/
3099 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> {
3101 // 1. Extract with offset
3103 (vector_extract vt:$vec, (add i32:$idx, imm:$off)),
3104 (eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off))
3107 // 2. Extract without offset
3109 (vector_extract vt:$vec, i32:$idx),
3110 (eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0))
3113 // 3. Insert with offset
3115 (vector_insert vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)),
3116 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val)
3119 // 4. Insert without offset
3121 (vector_insert vt:$vec, eltvt:$val, i32:$idx),
3122 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val)
3126 defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>;
3127 defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>;
3128 defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>;
3129 defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>;
3131 defm : SI_INDIRECT_Pattern <v2i32, i32, SI_INDIRECT_DST_V2>;
3132 defm : SI_INDIRECT_Pattern <v4i32, i32, SI_INDIRECT_DST_V4>;
3133 defm : SI_INDIRECT_Pattern <v8i32, i32, SI_INDIRECT_DST_V8>;
3134 defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>;
3136 //===----------------------------------------------------------------------===//
3137 // Conversion Patterns
3138 //===----------------------------------------------------------------------===//
3140 def : Pat<(i32 (sext_inreg i32:$src, i1)),
3141 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16
3143 // Handle sext_inreg in i64
3145 (i64 (sext_inreg i64:$src, i1)),
3146 (S_BFE_I64 i64:$src, 0x10000) // 0 | 1 << 16
3150 (i64 (sext_inreg i64:$src, i8)),
3151 (S_BFE_I64 i64:$src, 0x80000) // 0 | 8 << 16
3155 (i64 (sext_inreg i64:$src, i16)),
3156 (S_BFE_I64 i64:$src, 0x100000) // 0 | 16 << 16
3160 (i64 (sext_inreg i64:$src, i32)),
3161 (S_BFE_I64 i64:$src, 0x200000) // 0 | 32 << 16
3164 class ZExt_i64_i32_Pat <SDNode ext> : Pat <
3165 (i64 (ext i32:$src)),
3166 (REG_SEQUENCE SReg_64, $src, sub0, (S_MOV_B32 0), sub1)
3169 class ZExt_i64_i1_Pat <SDNode ext> : Pat <
3170 (i64 (ext i1:$src)),
3171 (REG_SEQUENCE VReg_64,
3172 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0,
3173 (S_MOV_B32 0), sub1)
3177 def : ZExt_i64_i32_Pat<zext>;
3178 def : ZExt_i64_i32_Pat<anyext>;
3179 def : ZExt_i64_i1_Pat<zext>;
3180 def : ZExt_i64_i1_Pat<anyext>;
3183 (i64 (sext i32:$src)),
3184 (REG_SEQUENCE SReg_64, $src, sub0,
3185 (S_ASHR_I32 $src, 31), sub1)
3189 (i64 (sext i1:$src)),
3190 (REG_SEQUENCE VReg_64,
3191 (V_CNDMASK_B32_e64 0, -1, $src), sub0,
3192 (V_CNDMASK_B32_e64 0, -1, $src), sub1)
3195 // If we need to perform a logical operation on i1 values, we need to
3196 // use vector comparisons since there is only one SCC register. Vector
3197 // comparisions still write to a pair of SGPRs, so treat these as
3198 // 64-bit comparisons. When legalizing SGPR copies, instructions
3199 // resulting in the copies from SCC to these instructions will be
3200 // moved to the VALU.
3202 (i1 (and i1:$src0, i1:$src1)),
3203 (S_AND_B64 $src0, $src1)
3207 (i1 (or i1:$src0, i1:$src1)),
3208 (S_OR_B64 $src0, $src1)
3212 (i1 (xor i1:$src0, i1:$src1)),
3213 (S_XOR_B64 $src0, $src1)
3217 (f32 (sint_to_fp i1:$src)),
3218 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src)
3222 (f32 (uint_to_fp i1:$src)),
3223 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src)
3227 (f64 (sint_to_fp i1:$src)),
3228 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src))
3232 (f64 (uint_to_fp i1:$src)),
3233 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src))
3236 //===----------------------------------------------------------------------===//
3237 // Miscellaneous Patterns
3238 //===----------------------------------------------------------------------===//
3241 (i32 (trunc i64:$a)),
3242 (EXTRACT_SUBREG $a, sub0)
3246 (i1 (trunc i32:$a)),
3247 (V_CMP_EQ_I32_e64 (V_AND_B32_e64 (i32 1), $a), 1)
3251 (i32 (bswap i32:$a)),
3252 (V_BFI_B32 (S_MOV_B32 0x00ff00ff),
3253 (V_ALIGNBIT_B32 $a, $a, 24),
3254 (V_ALIGNBIT_B32 $a, $a, 8))
3258 (f32 (select i1:$src2, f32:$src1, f32:$src0)),
3259 (V_CNDMASK_B32_e64 $src0, $src1, $src2)
3262 //============================================================================//
3263 // Miscellaneous Optimization Patterns
3264 //============================================================================//
3266 def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64>;
3268 } // End isGCN predicate