1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file was originally auto-generated from a GPU register header file and
10 // all the instruction definitions were originally commented out. Instructions
11 // that are not yet supported remain commented out.
12 //===----------------------------------------------------------------------===//
19 def INTERP : InterpSlots;
21 def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
25 def SendMsgImm : Operand<i32> {
26 let PrintMethod = "printSendMsg";
29 def isSI : Predicate<"Subtarget.getGeneration() "
30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
32 def isCI : Predicate<"Subtarget.getGeneration() "
33 ">= AMDGPUSubtarget::SEA_ISLANDS">;
35 def isCFDepth0 : Predicate<"isCFDepth0()">;
37 def WAIT_FLAG : InstFlag<"printWaitFlag">;
39 let SubtargetPredicate = isSI in {
40 let OtherPredicates = [isCFDepth0] in {
42 //===----------------------------------------------------------------------===//
44 //===----------------------------------------------------------------------===//
48 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit
49 // SMRD instructions, because the SGPR_32 register class does not include M0
50 // and writing to M0 from an SMRD instruction will hang the GPU.
51 defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>;
52 defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>;
53 defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>;
54 defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>;
55 defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>;
57 defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
58 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32
61 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
62 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64
65 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
66 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128
69 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
70 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256
73 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
74 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512
79 //def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
80 //def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
82 //===----------------------------------------------------------------------===//
84 //===----------------------------------------------------------------------===//
86 let neverHasSideEffects = 1 in {
88 let isMoveImm = 1 in {
89 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
90 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
91 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>;
92 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>;
93 } // End isMoveImm = 1
95 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32",
96 [(set i32:$dst, (not i32:$src0))]
99 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64",
100 [(set i64:$dst, (not i64:$src0))]
102 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>;
103 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>;
104 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>;
105 def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>;
106 } // End neverHasSideEffects = 1
108 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>;
109 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>;
110 def S_BCNT1_I32_B32 : SOP1_32 <0x0000000f, "S_BCNT1_I32_B32",
111 [(set i32:$dst, (ctpop i32:$src0))]
113 def S_BCNT1_I32_B64 : SOP1_32_64 <0x00000010, "S_BCNT1_I32_B64", []>;
115 ////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>;
116 ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>;
117 ////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>;
118 ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>;
119 //def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>;
120 //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>;
121 def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>;
122 //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>;
123 def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8",
124 [(set i32:$dst, (sext_inreg i32:$src0, i8))]
126 def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16",
127 [(set i32:$dst, (sext_inreg i32:$src0, i16))]
130 ////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>;
131 ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>;
132 ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>;
133 ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>;
134 def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>;
135 def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>;
136 def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>;
137 def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>;
139 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in {
141 def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>;
142 def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>;
143 def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>;
144 def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>;
145 def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>;
146 def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>;
147 def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>;
148 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>;
150 } // End hasSideEffects = 1
152 def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>;
153 def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>;
154 def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>;
155 def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>;
156 def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>;
157 def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>;
158 //def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>;
159 def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>;
160 def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>;
161 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>;
163 //===----------------------------------------------------------------------===//
165 //===----------------------------------------------------------------------===//
167 let Defs = [SCC] in { // Carry out goes to SCC
168 let isCommutable = 1 in {
169 def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
170 def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32",
171 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))]
173 } // End isCommutable = 1
175 def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>;
176 def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32",
177 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))]
180 let Uses = [SCC] in { // Carry in comes from SCC
181 let isCommutable = 1 in {
182 def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32",
183 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
184 } // End isCommutable = 1
186 def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32",
187 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
188 } // End Uses = [SCC]
189 } // End Defs = [SCC]
191 def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32",
192 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]
194 def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32",
195 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]
197 def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32",
198 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]
200 def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32",
201 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]
204 def S_CSELECT_B32 : SOP2 <
205 0x0000000a, (outs SReg_32:$dst),
206 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
210 def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>;
212 def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32",
213 [(set i32:$dst, (and i32:$src0, i32:$src1))]
216 def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64",
217 [(set i64:$dst, (and i64:$src0, i64:$src1))]
220 def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32",
221 [(set i32:$dst, (or i32:$src0, i32:$src1))]
224 def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64",
225 [(set i64:$dst, (or i64:$src0, i64:$src1))]
228 def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32",
229 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
232 def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64",
233 [(set i64:$dst, (xor i64:$src0, i64:$src1))]
235 def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>;
236 def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>;
237 def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>;
238 def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>;
239 def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>;
240 def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>;
241 def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>;
242 def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>;
243 def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>;
244 def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>;
246 // Use added complexity so these patterns are preferred to the VALU patterns.
247 let AddedComplexity = 1 in {
249 def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32",
250 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
252 def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64",
253 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
255 def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32",
256 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
258 def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64",
259 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
261 def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32",
262 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
264 def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64",
265 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
268 } // End AddedComplexity = 1
270 def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>;
271 def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>;
272 def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>;
273 def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>;
274 def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>;
275 def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>;
276 def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
277 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
278 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
280 //===----------------------------------------------------------------------===//
282 //===----------------------------------------------------------------------===//
284 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">;
285 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">;
286 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">;
287 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32">;
288 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32">;
289 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32">;
290 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32">;
291 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32">;
292 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32">;
293 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32">;
294 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32">;
295 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32">;
296 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>;
297 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>;
298 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>;
299 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
300 //def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
302 //===----------------------------------------------------------------------===//
304 //===----------------------------------------------------------------------===//
306 def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>;
307 def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>;
310 This instruction is disabled for now until we can figure out how to teach
311 the instruction selector to correctly use the S_CMP* vs V_CMP*
314 When this instruction is enabled the code generator sometimes produces this
317 SCC = S_CMPK_EQ_I32 SGPR0, imm
319 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
321 def S_CMPK_EQ_I32 : SOPK <
322 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1),
324 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
328 let isCompare = 1 in {
329 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>;
330 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>;
331 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>;
332 def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>;
333 def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>;
334 def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>;
335 def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>;
336 def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>;
337 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>;
338 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>;
339 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>;
340 } // End isCompare = 1
342 let Defs = [SCC], isCommutable = 1 in {
343 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>;
344 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>;
347 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>;
348 def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>;
349 def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>;
350 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
351 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
352 //def EXP : EXP_ <0x00000000, "EXP", []>;
354 } // End let OtherPredicates = [isCFDepth0]
356 //===----------------------------------------------------------------------===//
358 //===----------------------------------------------------------------------===//
360 def S_NOP : SOPP <0x00000000, (ins i16imm:$SIMM16), "S_NOP $SIMM16", []>;
362 let isTerminator = 1 in {
364 def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM",
371 let isBranch = 1 in {
372 def S_BRANCH : SOPP <
373 0x00000002, (ins brtarget:$target), "S_BRANCH $target",
378 let DisableEncoding = "$scc" in {
379 def S_CBRANCH_SCC0 : SOPP <
380 0x00000004, (ins brtarget:$target, SCCReg:$scc),
381 "S_CBRANCH_SCC0 $target", []
383 def S_CBRANCH_SCC1 : SOPP <
384 0x00000005, (ins brtarget:$target, SCCReg:$scc),
385 "S_CBRANCH_SCC1 $target",
388 } // End DisableEncoding = "$scc"
390 def S_CBRANCH_VCCZ : SOPP <
391 0x00000006, (ins brtarget:$target, VCCReg:$vcc),
392 "S_CBRANCH_VCCZ $target",
395 def S_CBRANCH_VCCNZ : SOPP <
396 0x00000007, (ins brtarget:$target, VCCReg:$vcc),
397 "S_CBRANCH_VCCNZ $target",
401 let DisableEncoding = "$exec" in {
402 def S_CBRANCH_EXECZ : SOPP <
403 0x00000008, (ins brtarget:$target, EXECReg:$exec),
404 "S_CBRANCH_EXECZ $target",
407 def S_CBRANCH_EXECNZ : SOPP <
408 0x00000009, (ins brtarget:$target, EXECReg:$exec),
409 "S_CBRANCH_EXECNZ $target",
412 } // End DisableEncoding = "$exec"
415 } // End isBranch = 1
416 } // End isTerminator = 1
418 let hasSideEffects = 1 in {
419 def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER",
420 [(int_AMDGPU_barrier_local)]
429 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
432 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
433 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
434 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
436 let Uses = [EXEC] in {
437 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16",
438 [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
440 let DisableEncoding = "$m0";
442 } // End Uses = [EXEC]
444 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
445 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
446 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
447 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
448 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
449 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
450 } // End hasSideEffects
452 //===----------------------------------------------------------------------===//
454 //===----------------------------------------------------------------------===//
456 let isCompare = 1 in {
458 defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">;
459 defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_OLT>;
460 defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_OEQ>;
461 defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_OLE>;
462 defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_OGT>;
463 defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32">;
464 defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_OGE>;
465 defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", f32, COND_O>;
466 defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", f32, COND_UO>;
467 defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">;
468 defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">;
469 defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">;
470 defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">;
471 defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_UNE>;
472 defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">;
473 defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">;
475 let hasSideEffects = 1, Defs = [EXEC] in {
477 defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">;
478 defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">;
479 defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">;
480 defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">;
481 defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">;
482 defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">;
483 defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">;
484 defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">;
485 defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">;
486 defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">;
487 defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">;
488 defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">;
489 defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">;
490 defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">;
491 defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">;
492 defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">;
494 } // End hasSideEffects = 1, Defs = [EXEC]
496 defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">;
497 defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_OLT>;
498 defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_OEQ>;
499 defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_OLE>;
500 defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_OGT>;
501 defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">;
502 defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_OGE>;
503 defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64", f64, COND_O>;
504 defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64", f64, COND_UO>;
505 defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">;
506 defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">;
507 defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">;
508 defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">;
509 defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_UNE>;
510 defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">;
511 defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">;
513 let hasSideEffects = 1, Defs = [EXEC] in {
515 defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">;
516 defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">;
517 defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">;
518 defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">;
519 defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">;
520 defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">;
521 defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">;
522 defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">;
523 defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">;
524 defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">;
525 defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">;
526 defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">;
527 defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">;
528 defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">;
529 defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">;
530 defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">;
532 } // End hasSideEffects = 1, Defs = [EXEC]
534 defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">;
535 defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">;
536 defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">;
537 defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">;
538 defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">;
539 defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">;
540 defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">;
541 defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">;
542 defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">;
543 defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">;
544 defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">;
545 defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">;
546 defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">;
547 defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">;
548 defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">;
549 defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">;
551 let hasSideEffects = 1, Defs = [EXEC] in {
553 defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">;
554 defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">;
555 defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">;
556 defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">;
557 defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">;
558 defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">;
559 defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">;
560 defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">;
561 defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">;
562 defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">;
563 defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">;
564 defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">;
565 defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">;
566 defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">;
567 defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">;
568 defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">;
570 } // End hasSideEffects = 1, Defs = [EXEC]
572 defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">;
573 defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">;
574 defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">;
575 defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">;
576 defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">;
577 defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">;
578 defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">;
579 defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">;
580 defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">;
581 defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">;
582 defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">;
583 defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">;
584 defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">;
585 defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">;
586 defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">;
587 defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">;
589 let hasSideEffects = 1, Defs = [EXEC] in {
591 defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">;
592 defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">;
593 defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">;
594 defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">;
595 defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">;
596 defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">;
597 defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">;
598 defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">;
599 defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">;
600 defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">;
601 defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">;
602 defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">;
603 defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">;
604 defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">;
605 defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">;
606 defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">;
608 } // End hasSideEffects = 1, Defs = [EXEC]
610 defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">;
611 defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_SLT>;
612 defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>;
613 defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_SLE>;
614 defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_SGT>;
615 defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>;
616 defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_SGE>;
617 defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">;
619 let hasSideEffects = 1, Defs = [EXEC] in {
621 defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">;
622 defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">;
623 defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">;
624 defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">;
625 defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">;
626 defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">;
627 defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">;
628 defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">;
630 } // End hasSideEffects = 1, Defs = [EXEC]
632 defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">;
633 defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64", i64, COND_SLT>;
634 defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64", i64, COND_EQ>;
635 defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64", i64, COND_SLE>;
636 defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64", i64, COND_SGT>;
637 defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64", i64, COND_NE>;
638 defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64", i64, COND_SGE>;
639 defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">;
641 let hasSideEffects = 1, Defs = [EXEC] in {
643 defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">;
644 defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">;
645 defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">;
646 defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">;
647 defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">;
648 defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">;
649 defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">;
650 defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">;
652 } // End hasSideEffects = 1, Defs = [EXEC]
654 defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">;
655 defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32", i32, COND_ULT>;
656 defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32", i32, COND_EQ>;
657 defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32", i32, COND_ULE>;
658 defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32", i32, COND_UGT>;
659 defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32", i32, COND_NE>;
660 defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32", i32, COND_UGE>;
661 defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">;
663 let hasSideEffects = 1, Defs = [EXEC] in {
665 defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">;
666 defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">;
667 defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">;
668 defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">;
669 defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">;
670 defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">;
671 defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">;
672 defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">;
674 } // End hasSideEffects = 1, Defs = [EXEC]
676 defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">;
677 defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64", i64, COND_ULT>;
678 defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64", i64, COND_EQ>;
679 defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64", i64, COND_ULE>;
680 defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64", i64, COND_UGT>;
681 defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64", i64, COND_NE>;
682 defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64", i64, COND_UGE>;
683 defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">;
685 let hasSideEffects = 1, Defs = [EXEC] in {
687 defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">;
688 defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">;
689 defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">;
690 defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">;
691 defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">;
692 defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">;
693 defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">;
694 defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">;
696 } // End hasSideEffects = 1, Defs = [EXEC]
698 defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">;
700 let hasSideEffects = 1, Defs = [EXEC] in {
701 defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">;
702 } // End hasSideEffects = 1, Defs = [EXEC]
704 defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">;
706 let hasSideEffects = 1, Defs = [EXEC] in {
707 defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">;
708 } // End hasSideEffects = 1, Defs = [EXEC]
710 } // End isCompare = 1
712 //===----------------------------------------------------------------------===//
714 //===----------------------------------------------------------------------===//
717 def DS_ADD_U32 : DS_1A1D_NORET <0x0, "DS_ADD_U32", VReg_32>;
718 def DS_SUB_U32 : DS_1A1D_NORET <0x1, "DS_SUB_U32", VReg_32>;
719 def DS_RSUB_U32 : DS_1A1D_NORET <0x2, "DS_RSUB_U32", VReg_32>;
720 def DS_INC_U32 : DS_1A1D_NORET <0x3, "DS_INC_U32", VReg_32>;
721 def DS_DEC_U32 : DS_1A1D_NORET <0x4, "DS_DEC_U32", VReg_32>;
722 def DS_MIN_I32 : DS_1A1D_NORET <0x5, "DS_MIN_I32", VReg_32>;
723 def DS_MAX_I32 : DS_1A1D_NORET <0x6, "DS_MAX_I32", VReg_32>;
724 def DS_MIN_U32 : DS_1A1D_NORET <0x7, "DS_MIN_U32", VReg_32>;
725 def DS_MAX_U32 : DS_1A1D_NORET <0x8, "DS_MAX_U32", VReg_32>;
726 def DS_AND_B32 : DS_1A1D_NORET <0x9, "DS_AND_B32", VReg_32>;
727 def DS_OR_B32 : DS_1A1D_NORET <0xa, "DS_OR_B32", VReg_32>;
728 def DS_XOR_B32 : DS_1A1D_NORET <0xb, "DS_XOR_B32", VReg_32>;
729 def DS_MSKOR_B32 : DS_1A1D_NORET <0xc, "DS_MSKOR_B32", VReg_32>;
730 def DS_CMPST_B32 : DS_1A2D_NORET <0x10, "DS_CMPST_B32", VReg_32>;
731 def DS_CMPST_F32 : DS_1A2D_NORET <0x11, "DS_CMPST_F32", VReg_32>;
732 def DS_MIN_F32 : DS_1A1D_NORET <0x12, "DS_MIN_F32", VReg_32>;
733 def DS_MAX_F32 : DS_1A1D_NORET <0x13, "DS_MAX_F32", VReg_32>;
735 def DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "DS_ADD_RTN_U32", VReg_32>;
736 def DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "DS_SUB_RTN_U32", VReg_32>;
737 def DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "DS_RSUB_RTN_U32", VReg_32>;
738 def DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "DS_INC_RTN_U32", VReg_32>;
739 def DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "DS_DEC_RTN_U32", VReg_32>;
740 def DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "DS_MIN_RTN_I32", VReg_32>;
741 def DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "DS_MAX_RTN_I32", VReg_32>;
742 def DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "DS_MIN_RTN_U32", VReg_32>;
743 def DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "DS_MAX_RTN_U32", VReg_32>;
744 def DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "DS_AND_RTN_B32", VReg_32>;
745 def DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "DS_OR_RTN_B32", VReg_32>;
746 def DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "DS_XOR_RTN_B32", VReg_32>;
747 def DS_MSKOR_RTN_B32 : DS_1A1D_RET <0x2c, "DS_MSKOR_RTN_B32", VReg_32>;
748 def DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "DS_WRXCHG_RTN_B32", VReg_32>;
749 //def DS_WRXCHG2_RTN_B32 : DS_2A0D_RET <0x2e, "DS_WRXCHG2_RTN_B32", VReg_32>;
750 //def DS_WRXCHG2ST64_RTN_B32 : DS_2A0D_RET <0x2f, "DS_WRXCHG2_RTN_B32", VReg_32>;
751 def DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "DS_CMPST_RTN_B32", VReg_32>;
752 def DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "DS_CMPST_RTN_F32", VReg_32>;
753 def DS_MIN_RTN_F32 : DS_1A1D_RET <0x32, "DS_MIN_RTN_F32", VReg_32>;
754 def DS_MAX_RTN_F32 : DS_1A1D_RET <0x33, "DS_MAX_RTN_F32", VReg_32>;
756 let SubtargetPredicate = isCI in {
757 def DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "DS_WRAP_RTN_F32", VReg_32>;
761 def DS_ADD_U64 : DS_1A1D_NORET <0x40, "DS_ADD_U64", VReg_32>;
762 def DS_SUB_U64 : DS_1A1D_NORET <0x41, "DS_SUB_U64", VReg_32>;
763 def DS_RSUB_U64 : DS_1A1D_NORET <0x42, "DS_RSUB_U64", VReg_32>;
764 def DS_INC_U64 : DS_1A1D_NORET <0x43, "DS_INC_U64", VReg_32>;
765 def DS_DEC_U64 : DS_1A1D_NORET <0x44, "DS_DEC_U64", VReg_32>;
766 def DS_MIN_I64 : DS_1A1D_NORET <0x45, "DS_MIN_I64", VReg_64>;
767 def DS_MAX_I64 : DS_1A1D_NORET <0x46, "DS_MAX_I64", VReg_64>;
768 def DS_MIN_U64 : DS_1A1D_NORET <0x47, "DS_MIN_U64", VReg_64>;
769 def DS_MAX_U64 : DS_1A1D_NORET <0x48, "DS_MAX_U64", VReg_64>;
770 def DS_AND_B64 : DS_1A1D_NORET <0x49, "DS_AND_B64", VReg_64>;
771 def DS_OR_B64 : DS_1A1D_NORET <0x4a, "DS_OR_B64", VReg_64>;
772 def DS_XOR_B64 : DS_1A1D_NORET <0x4b, "DS_XOR_B64", VReg_64>;
773 def DS_MSKOR_B64 : DS_1A1D_NORET <0x4c, "DS_MSKOR_B64", VReg_64>;
774 def DS_CMPST_B64 : DS_1A2D_NORET <0x50, "DS_CMPST_B64", VReg_64>;
775 def DS_CMPST_F64 : DS_1A2D_NORET <0x51, "DS_CMPST_F64", VReg_64>;
776 def DS_MIN_F64 : DS_1A1D_NORET <0x52, "DS_MIN_F64", VReg_64>;
777 def DS_MAX_F64 : DS_1A1D_NORET <0x53, "DS_MAX_F64", VReg_64>;
779 def DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "DS_ADD_RTN_U64", VReg_64>;
780 def DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "DS_SUB_RTN_U64", VReg_64>;
781 def DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "DS_RSUB_RTN_U64", VReg_64>;
782 def DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "DS_INC_RTN_U64", VReg_64>;
783 def DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "DS_DEC_RTN_U64", VReg_64>;
784 def DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "DS_MIN_RTN_I64", VReg_64>;
785 def DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "DS_MAX_RTN_I64", VReg_64>;
786 def DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "DS_MIN_RTN_U64", VReg_64>;
787 def DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "DS_MAX_RTN_U64", VReg_64>;
788 def DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "DS_AND_RTN_B64", VReg_64>;
789 def DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "DS_OR_RTN_B64", VReg_64>;
790 def DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "DS_XOR_RTN_B64", VReg_64>;
791 def DS_MSKOR_RTN_B64 : DS_1A1D_RET <0x6c, "DS_MSKOR_RTN_B64", VReg_64>;
792 def DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "DS_WRXCHG_RTN_B64", VReg_64>;
793 //def DS_WRXCHG2_RTN_B64 : DS_2A0D_RET <0x6e, "DS_WRXCHG2_RTN_B64", VReg_64>;
794 //def DS_WRXCHG2ST64_RTN_B64 : DS_2A0D_RET <0x6f, "DS_WRXCHG2_RTN_B64", VReg_64>;
795 def DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "DS_CMPST_RTN_B64", VReg_64>;
796 def DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "DS_CMPST_RTN_F64", VReg_64>;
797 def DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "DS_MIN_F64", VReg_64>;
798 def DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "DS_MAX_F64", VReg_64>;
800 //let SubtargetPredicate = isCI in {
801 // DS_CONDXCHG32_RTN_B64
802 // DS_CONDXCHG32_RTN_B128
805 // TODO: _SRC2_* forms
807 def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>;
808 def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>;
809 def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>;
810 def DS_WRITE_B64 : DS_Store_Helper <0x00000004d, "DS_WRITE_B64", VReg_64>;
812 def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>;
813 def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>;
814 def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>;
815 def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>;
816 def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>;
817 def DS_READ_B64 : DS_Load_Helper <0x00000076, "DS_READ_B64", VReg_64>;
820 def DS_WRITE2_B32 : DS_Load2_Helper <0x0000000E, "DS_WRITE2_B32", VReg_64>;
821 def DS_WRITE2_B64 : DS_Load2_Helper <0x0000004E, "DS_WRITE2_B64", VReg_128>;
823 def DS_READ2_B32 : DS_Load2_Helper <0x00000037, "DS_READ2_B32", VReg_64>;
824 def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "DS_READ2_B64", VReg_128>;
826 // TODO: DS_READ2ST64_B32, DS_READ2ST64_B64,
827 // DS_WRITE2ST64_B32, DS_WRITE2ST64_B64
829 //===----------------------------------------------------------------------===//
830 // MUBUF Instructions
831 //===----------------------------------------------------------------------===//
833 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
834 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
835 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
836 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>;
837 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>;
838 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>;
839 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>;
840 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>;
841 defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>;
842 defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <0x00000009, "BUFFER_LOAD_SBYTE", VReg_32>;
843 defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <0x0000000a, "BUFFER_LOAD_USHORT", VReg_32>;
844 defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32>;
845 defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>;
846 defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>;
847 defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>;
849 def BUFFER_STORE_BYTE : MUBUF_Store_Helper <
850 0x00000018, "BUFFER_STORE_BYTE", VReg_32
853 def BUFFER_STORE_SHORT : MUBUF_Store_Helper <
854 0x0000001a, "BUFFER_STORE_SHORT", VReg_32
857 def BUFFER_STORE_DWORD : MUBUF_Store_Helper <
858 0x0000001c, "BUFFER_STORE_DWORD", VReg_32
861 def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
862 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64
865 def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
866 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128
868 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>;
869 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>;
870 //def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>;
871 //def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>;
872 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>;
873 //def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>;
874 //def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>;
875 //def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>;
876 //def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>;
877 //def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>;
878 //def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>;
879 //def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>;
880 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>;
881 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>;
882 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>;
883 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>;
884 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>;
885 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>;
886 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>;
887 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>;
888 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>;
889 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>;
890 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>;
891 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>;
892 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>;
893 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>;
894 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>;
895 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>;
896 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>;
897 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>;
898 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>;
899 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>;
900 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>;
901 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>;
902 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>;
903 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>;
905 //===----------------------------------------------------------------------===//
906 // MTBUF Instructions
907 //===----------------------------------------------------------------------===//
909 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>;
910 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>;
911 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>;
912 def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>;
913 def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>;
914 def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>;
915 def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>;
916 def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>;
918 //===----------------------------------------------------------------------===//
920 //===----------------------------------------------------------------------===//
922 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">;
923 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">;
924 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>;
925 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>;
926 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>;
927 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>;
928 //def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>;
929 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>;
930 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>;
931 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>;
932 defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">;
933 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>;
934 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>;
935 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>;
936 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>;
937 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>;
938 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>;
939 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>;
940 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>;
941 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>;
942 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>;
943 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>;
944 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>;
945 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>;
946 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>;
947 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>;
948 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>;
949 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>;
950 defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">;
951 //def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>;
952 defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">;
953 //def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>;
954 defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">;
955 defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">;
956 //def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>;
957 //def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>;
958 defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">;
959 //def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>;
960 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">;
961 //def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>;
962 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">;
963 defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">;
964 //def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>;
965 //def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>;
966 //def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>;
967 //def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>;
968 //def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>;
969 //def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>;
970 //def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>;
971 //def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>;
972 //def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>;
973 //def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>;
974 //def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>;
975 //def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>;
976 //def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>;
977 //def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>;
978 //def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>;
979 //def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>;
980 //def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>;
981 //def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>;
982 //def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>;
983 //def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>;
984 //def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>;
985 //def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>;
986 //def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>;
987 //def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>;
988 //def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>;
989 //def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>;
990 //def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>;
991 //def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>;
992 //def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>;
993 //def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>;
994 //def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>;
995 //def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>;
996 //def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>;
997 //def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>;
998 //def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>;
999 //def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>;
1000 //def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>;
1001 //def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>;
1002 //def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>;
1003 //def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>;
1004 //def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>;
1005 //def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>;
1006 //def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>;
1007 //def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>;
1008 //def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>;
1009 //def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>;
1010 //def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>;
1011 //def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>;
1012 //def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>;
1013 //def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>;
1014 //def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>;
1015 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>;
1016 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>;
1018 //===----------------------------------------------------------------------===//
1019 // VOP1 Instructions
1020 //===----------------------------------------------------------------------===//
1022 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
1024 let neverHasSideEffects = 1, isMoveImm = 1 in {
1025 defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>;
1026 } // End neverHasSideEffects = 1, isMoveImm = 1
1028 let Uses = [EXEC] in {
1030 def V_READFIRSTLANE_B32 : VOP1 <
1032 (outs SReg_32:$vdst),
1033 (ins VReg_32:$src0),
1034 "V_READFIRSTLANE_B32 $vdst, $src0",
1040 defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64",
1041 [(set i32:$dst, (fp_to_sint f64:$src0))]
1043 defm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32",
1044 [(set f64:$dst, (sint_to_fp i32:$src0))]
1046 defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32",
1047 [(set f32:$dst, (sint_to_fp i32:$src0))]
1049 defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32",
1050 [(set f32:$dst, (uint_to_fp i32:$src0))]
1052 defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32",
1053 [(set i32:$dst, (fp_to_uint f32:$src0))]
1055 defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32",
1056 [(set i32:$dst, (fp_to_sint f32:$src0))]
1058 defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>;
1059 ////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>;
1060 //defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>;
1061 //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>;
1062 //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>;
1063 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>;
1064 defm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64",
1065 [(set f32:$dst, (fround f64:$src0))]
1067 defm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32",
1068 [(set f64:$dst, (fextend f32:$src0))]
1070 defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0",
1071 [(set f32:$dst, (AMDGPUcvt_f32_ubyte0 i32:$src0))]
1073 defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1",
1074 [(set f32:$dst, (AMDGPUcvt_f32_ubyte1 i32:$src0))]
1076 defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2",
1077 [(set f32:$dst, (AMDGPUcvt_f32_ubyte2 i32:$src0))]
1079 defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3",
1080 [(set f32:$dst, (AMDGPUcvt_f32_ubyte3 i32:$src0))]
1082 defm V_CVT_U32_F64 : VOP1_32_64 <0x00000015, "V_CVT_U32_F64",
1083 [(set i32:$dst, (fp_to_uint f64:$src0))]
1085 defm V_CVT_F64_U32 : VOP1_64_32 <0x00000016, "V_CVT_F64_U32",
1086 [(set f64:$dst, (uint_to_fp i32:$src0))]
1089 defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32",
1090 [(set f32:$dst, (AMDGPUfract f32:$src0))]
1092 defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32",
1093 [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))]
1095 defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32",
1096 [(set f32:$dst, (fceil f32:$src0))]
1098 defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32",
1099 [(set f32:$dst, (frint f32:$src0))]
1101 defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32",
1102 [(set f32:$dst, (ffloor f32:$src0))]
1104 defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32",
1105 [(set f32:$dst, (fexp2 f32:$src0))]
1107 defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>;
1108 defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32",
1109 [(set f32:$dst, (flog2 f32:$src0))]
1111 defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>;
1112 defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>;
1113 defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32",
1114 [(set f32:$dst, (fdiv FP_ONE, f32:$src0))]
1116 defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>;
1117 defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>;
1118 defm V_RSQ_LEGACY_F32 : VOP1_32 <
1119 0x0000002d, "V_RSQ_LEGACY_F32",
1120 [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))]
1122 defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32",
1123 [(set f32:$dst, (fdiv FP_ONE, (fsqrt f32:$src0)))]
1125 defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64",
1126 [(set f64:$dst, (fdiv FP_ONE, f64:$src0))]
1128 defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>;
1129 defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64",
1130 [(set f64:$dst, (fdiv FP_ONE, (fsqrt f64:$src0)))]
1132 defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>;
1133 defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32",
1134 [(set f32:$dst, (fsqrt f32:$src0))]
1136 defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64",
1137 [(set f64:$dst, (fsqrt f64:$src0))]
1139 defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>;
1140 defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>;
1141 defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>;
1142 defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>;
1143 defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>;
1144 defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>;
1145 defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>;
1146 //defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>;
1147 defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>;
1148 defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>;
1149 //defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>;
1150 defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>;
1151 //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>;
1152 defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>;
1153 defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>;
1154 defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>;
1157 //===----------------------------------------------------------------------===//
1158 // VINTRP Instructions
1159 //===----------------------------------------------------------------------===//
1161 def V_INTERP_P1_F32 : VINTRP <
1163 (outs VReg_32:$dst),
1164 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1165 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]",
1167 let DisableEncoding = "$m0";
1170 def V_INTERP_P2_F32 : VINTRP <
1172 (outs VReg_32:$dst),
1173 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1174 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
1177 let Constraints = "$src0 = $dst";
1178 let DisableEncoding = "$src0,$m0";
1182 def V_INTERP_MOV_F32 : VINTRP <
1184 (outs VReg_32:$dst),
1185 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1186 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]",
1188 let DisableEncoding = "$m0";
1191 //===----------------------------------------------------------------------===//
1192 // VOP2 Instructions
1193 //===----------------------------------------------------------------------===//
1195 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
1196 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
1197 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]",
1200 let DisableEncoding = "$vcc";
1203 def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
1204 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2,
1205 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
1206 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg",
1207 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))]
1209 let src0_modifiers = 0;
1210 let src1_modifiers = 0;
1211 let src2_modifiers = 0;
1214 def V_READLANE_B32 : VOP2 <
1216 (outs SReg_32:$vdst),
1217 (ins VReg_32:$src0, SSrc_32:$vsrc1),
1218 "V_READLANE_B32 $vdst, $src0, $vsrc1",
1222 def V_WRITELANE_B32 : VOP2 <
1224 (outs VReg_32:$vdst),
1225 (ins SReg_32:$src0, SSrc_32:$vsrc1),
1226 "V_WRITELANE_B32 $vdst, $src0, $vsrc1",
1230 let isCommutable = 1 in {
1231 defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32",
1232 [(set f32:$dst, (fadd f32:$src0, f32:$src1))]
1235 defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32",
1236 [(set f32:$dst, (fsub f32:$src0, f32:$src1))]
1238 defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">;
1239 } // End isCommutable = 1
1241 defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>;
1243 let isCommutable = 1 in {
1245 defm V_MUL_LEGACY_F32 : VOP2_32 <
1246 0x00000007, "V_MUL_LEGACY_F32",
1247 [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))]
1250 defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32",
1251 [(set f32:$dst, (fmul f32:$src0, f32:$src1))]
1255 defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24",
1256 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))]
1258 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>;
1259 defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24",
1260 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))]
1262 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>;
1265 defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32",
1266 [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))]
1269 defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32",
1270 [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))]
1273 defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>;
1274 defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>;
1275 defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32",
1276 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]>;
1277 defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32",
1278 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]>;
1279 defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32",
1280 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]>;
1281 defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32",
1282 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]>;
1284 defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32",
1285 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
1288 defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">;
1290 defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32",
1291 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
1293 defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">;
1295 let hasPostISelHook = 1 in {
1297 defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32",
1298 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
1302 defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">;
1304 defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32",
1305 [(set i32:$dst, (and i32:$src0, i32:$src1))]>;
1306 defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32",
1307 [(set i32:$dst, (or i32:$src0, i32:$src1))]
1309 defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32",
1310 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
1313 } // End isCommutable = 1
1315 defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32",
1316 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))]>;
1317 defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>;
1318 defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>;
1319 defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>;
1320 defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>;
1321 defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
1322 defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
1324 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
1325 // No patterns so that the scalar instructions are always selected.
1326 // The scalar versions will be replaced with vector when needed later.
1327 defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32",
1328 [(set i32:$dst, (add i32:$src0, i32:$src1))], VSrc_32>;
1329 defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32",
1330 [(set i32:$dst, (sub i32:$src0, i32:$src1))], VSrc_32>;
1331 defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], VSrc_32,
1334 let Uses = [VCC] in { // Carry-in comes from VCC
1335 defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32",
1336 [(set i32:$dst, (adde i32:$src0, i32:$src1))], VReg_32>;
1337 defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32",
1338 [(set i32:$dst, (sube i32:$src0, i32:$src1))], VReg_32>;
1339 defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], VReg_32,
1341 } // End Uses = [VCC]
1342 } // End isCommutable = 1, Defs = [VCC]
1344 defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>;
1345 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
1346 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
1347 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>;
1348 defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32",
1349 [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))]
1351 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>;
1352 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>;
1354 //===----------------------------------------------------------------------===//
1355 // VOP3 Instructions
1356 //===----------------------------------------------------------------------===//
1358 let neverHasSideEffects = 1 in {
1360 defm V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>;
1361 defm V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32",
1362 [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))]
1364 defm V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24",
1365 [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))]
1367 defm V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24",
1368 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))]
1371 } // End neverHasSideEffects
1373 defm V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>;
1374 defm V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>;
1375 defm V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>;
1376 defm V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>;
1378 let neverHasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
1379 defm V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32",
1380 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))]>;
1381 defm V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32",
1382 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))]>;
1385 defm V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32",
1386 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))]>;
1387 defm V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32",
1388 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))]
1390 def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64",
1391 [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
1393 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
1394 defm V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>;
1396 defm V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>;
1397 defm V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>;
1398 ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>;
1399 ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>;
1400 ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>;
1401 ////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>;
1402 ////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>;
1403 ////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>;
1404 ////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>;
1405 ////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>;
1406 ////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>;
1407 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>;
1408 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>;
1409 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>;
1410 defm V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>;
1411 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>;
1412 defm V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>;
1413 def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>;
1415 def V_LSHL_B64 : VOP3_64_32 <0x00000161, "V_LSHL_B64",
1416 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
1418 def V_LSHR_B64 : VOP3_64_32 <0x00000162, "V_LSHR_B64",
1419 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
1421 def V_ASHR_I64 : VOP3_64_32 <0x00000163, "V_ASHR_I64",
1422 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
1425 let isCommutable = 1 in {
1427 def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>;
1428 def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>;
1429 def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>;
1430 def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>;
1432 } // isCommutable = 1
1434 def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>;
1436 let isCommutable = 1 in {
1438 defm V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>;
1439 defm V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>;
1440 defm V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>;
1441 defm V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>;
1443 } // isCommutable = 1
1445 defm V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>;
1446 def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>;
1447 defm V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>;
1448 def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>;
1449 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>;
1450 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>;
1451 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>;
1452 def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>;
1454 //===----------------------------------------------------------------------===//
1455 // Pseudo Instructions
1456 //===----------------------------------------------------------------------===//
1458 let isCodeGenOnly = 1, isPseudo = 1 in {
1460 def V_MOV_I1 : InstSI <
1463 "", [(set i1:$dst, (imm:$src))]
1466 def V_AND_I1 : InstSI <
1467 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1468 [(set i1:$dst, (and i1:$src0, i1:$src1))]
1471 def V_OR_I1 : InstSI <
1472 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1473 [(set i1:$dst, (or i1:$src0, i1:$src1))]
1476 // SI pseudo instructions. These are used by the CFG structurizer pass
1477 // and should be lowered to ISA instructions prior to codegen.
1479 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
1480 Uses = [EXEC], Defs = [EXEC] in {
1482 let isBranch = 1, isTerminator = 1 in {
1485 (outs SReg_64:$dst),
1486 (ins SReg_64:$vcc, brtarget:$target),
1488 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
1491 def SI_ELSE : InstSI <
1492 (outs SReg_64:$dst),
1493 (ins SReg_64:$src, brtarget:$target),
1495 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]
1497 let Constraints = "$src = $dst";
1500 def SI_LOOP : InstSI <
1502 (ins SReg_64:$saved, brtarget:$target),
1503 "SI_LOOP $saved, $target",
1504 [(int_SI_loop i64:$saved, bb:$target)]
1507 } // end isBranch = 1, isTerminator = 1
1509 def SI_BREAK : InstSI <
1510 (outs SReg_64:$dst),
1512 "SI_ELSE $dst, $src",
1513 [(set i64:$dst, (int_SI_break i64:$src))]
1516 def SI_IF_BREAK : InstSI <
1517 (outs SReg_64:$dst),
1518 (ins SReg_64:$vcc, SReg_64:$src),
1519 "SI_IF_BREAK $dst, $vcc, $src",
1520 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))]
1523 def SI_ELSE_BREAK : InstSI <
1524 (outs SReg_64:$dst),
1525 (ins SReg_64:$src0, SReg_64:$src1),
1526 "SI_ELSE_BREAK $dst, $src0, $src1",
1527 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))]
1530 def SI_END_CF : InstSI <
1532 (ins SReg_64:$saved),
1534 [(int_SI_end_cf i64:$saved)]
1537 def SI_KILL : InstSI <
1541 [(int_AMDGPU_kill f32:$src)]
1544 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
1545 // Uses = [EXEC], Defs = [EXEC]
1547 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
1549 //defm SI_ : RegisterLoadStore <VReg_32, FRAMEri, ADDRIndirect>;
1551 let UseNamedOperandTable = 1 in {
1553 def SI_RegisterLoad : InstSI <
1554 (outs VReg_32:$dst, SReg_64:$temp),
1555 (ins FRAMEri32:$addr, i32imm:$chan),
1558 let isRegisterLoad = 1;
1562 class SIRegStore<dag outs> : InstSI <
1564 (ins VReg_32:$val, FRAMEri32:$addr, i32imm:$chan),
1567 let isRegisterStore = 1;
1571 let usesCustomInserter = 1 in {
1572 def SI_RegisterStorePseudo : SIRegStore<(outs)>;
1573 } // End usesCustomInserter = 1
1574 def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>;
1577 } // End UseNamedOperandTable = 1
1579 def SI_INDIRECT_SRC : InstSI <
1580 (outs VReg_32:$dst, SReg_64:$temp),
1581 (ins unknown:$src, VSrc_32:$idx, i32imm:$off),
1582 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off",
1586 class SI_INDIRECT_DST<RegisterClass rc> : InstSI <
1587 (outs rc:$dst, SReg_64:$temp),
1588 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val),
1589 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val",
1592 let Constraints = "$src = $dst";
1595 def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>;
1596 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
1597 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
1598 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
1599 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
1601 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
1603 let usesCustomInserter = 1 in {
1605 // This pseudo instruction takes a pointer as input and outputs a resource
1606 // constant that can be used with the ADDR64 MUBUF instructions.
1607 def SI_ADDR64_RSRC : InstSI <
1608 (outs SReg_128:$srsrc),
1613 def V_SUB_F64 : InstSI <
1614 (outs VReg_64:$dst),
1615 (ins VReg_64:$src0, VReg_64:$src1),
1616 "V_SUB_F64 $dst, $src0, $src1",
1620 } // end usesCustomInserter
1622 multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
1624 def _SAVE : InstSI <
1625 (outs VReg_32:$dst),
1626 (ins sgpr_class:$src, i32imm:$frame_idx),
1630 def _RESTORE : InstSI <
1631 (outs sgpr_class:$dst),
1632 (ins VReg_32:$src, i32imm:$frame_idx),
1638 defm SI_SPILL_S32 : SI_SPILL_SGPR <SReg_32>;
1639 defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
1640 defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
1641 defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
1642 defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
1644 } // end IsCodeGenOnly, isPseudo
1646 } // end SubtargetPredicate = SI
1648 let Predicates = [isSI] in {
1651 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2),
1652 (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0))
1657 (SI_KILL 0xbf800000)
1660 /* int_SI_vs_load_input */
1662 (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
1663 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
1668 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
1669 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
1670 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
1671 $src0, $src1, $src2, $src3)
1675 (f64 (fsub f64:$src0, f64:$src1)),
1676 (V_SUB_F64 $src0, $src1)
1679 //===----------------------------------------------------------------------===//
1681 //===----------------------------------------------------------------------===//
1683 multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
1685 // 1. Offset as 8bit DWORD immediate
1687 (constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))),
1688 (vt (Instr_IMM $sbase, (as_dword_i32imm $offset)))
1691 // 2. Offset loaded in an 32bit SGPR
1693 (constant_load (add i64:$sbase, (i64 IMM32bit:$offset))),
1694 (vt (Instr_SGPR $sbase, (S_MOV_B32 (i32 (as_i32imm $offset)))))
1697 // 3. No offset at all
1699 (constant_load i64:$sbase),
1700 (vt (Instr_IMM $sbase, 0))
1704 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
1705 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
1706 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>;
1707 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
1708 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
1709 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
1710 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
1711 defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
1713 // 1. Offset as 8bit DWORD immediate
1715 (SIload_constant v4i32:$sbase, IMM8bitDWORD:$offset),
1716 (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset))
1719 // 2. Offset loaded in an 32bit SGPR
1721 (SIload_constant v4i32:$sbase, imm:$offset),
1722 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
1725 //===----------------------------------------------------------------------===//
1727 //===----------------------------------------------------------------------===//
1730 (i1 (xor i1:$src0, i1:$src1)),
1731 (S_XOR_B64 $src0, $src1)
1734 //===----------------------------------------------------------------------===//
1736 //===----------------------------------------------------------------------===//
1739 (int_AMDGPU_barrier_global),
1743 //===----------------------------------------------------------------------===//
1745 //===----------------------------------------------------------------------===//
1748 (or i64:$src0, i64:$src1),
1749 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1750 (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub0),
1751 (EXTRACT_SUBREG i64:$src1, sub0)), sub0),
1752 (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub1),
1753 (EXTRACT_SUBREG i64:$src1, sub1)), sub1)
1756 class SextInReg <ValueType vt, int ShiftAmt> : Pat <
1757 (sext_inreg i32:$src0, vt),
1758 (V_ASHRREV_I32_e32 ShiftAmt, (V_LSHLREV_B32_e32 ShiftAmt, $src0))
1761 def : SextInReg <i8, 24>;
1762 def : SextInReg <i16, 16>;
1764 /********** ======================= **********/
1765 /********** Image sampling patterns **********/
1766 /********** ======================= **********/
1768 /* SIsample for simple 1D texture lookup */
1770 (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
1771 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1774 class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1775 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
1776 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1779 class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1780 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT),
1781 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1784 class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1785 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY),
1786 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1789 class SampleShadowPattern<SDNode name, MIMG opcode,
1790 ValueType vt> : Pat <
1791 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW),
1792 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1795 class SampleShadowArrayPattern<SDNode name, MIMG opcode,
1796 ValueType vt> : Pat <
1797 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
1798 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1801 /* SIsample* for texture lookups consuming more address parameters */
1802 multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
1803 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
1804 MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
1805 def : SamplePattern <SIsample, sample, addr_type>;
1806 def : SampleRectPattern <SIsample, sample, addr_type>;
1807 def : SampleArrayPattern <SIsample, sample, addr_type>;
1808 def : SampleShadowPattern <SIsample, sample_c, addr_type>;
1809 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
1811 def : SamplePattern <SIsamplel, sample_l, addr_type>;
1812 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
1813 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
1814 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
1816 def : SamplePattern <SIsampleb, sample_b, addr_type>;
1817 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
1818 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
1819 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
1821 def : SamplePattern <SIsampled, sample_d, addr_type>;
1822 def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
1823 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
1824 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
1827 defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
1828 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
1829 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
1830 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
1832 defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
1833 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
1834 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
1835 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
1837 defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
1838 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
1839 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
1840 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
1842 defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
1843 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
1844 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
1845 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
1848 /* int_SI_imageload for texture fetches consuming varying address parameters */
1849 class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1850 (name addr_type:$addr, v32i8:$rsrc, imm),
1851 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
1854 class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1855 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
1856 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
1859 class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1860 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
1861 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
1864 class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1865 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
1866 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
1869 multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> {
1870 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>;
1871 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>;
1874 multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> {
1875 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>;
1876 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>;
1879 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>;
1880 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>;
1882 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>;
1883 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>;
1885 /* Image resource information */
1887 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm),
1888 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1892 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY),
1893 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1897 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA),
1898 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1901 /********** ============================================ **********/
1902 /********** Extraction, Insertion, Building and Casting **********/
1903 /********** ============================================ **********/
1905 foreach Index = 0-2 in {
1906 def Extract_Element_v2i32_#Index : Extract_Element <
1907 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1909 def Insert_Element_v2i32_#Index : Insert_Element <
1910 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1913 def Extract_Element_v2f32_#Index : Extract_Element <
1914 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1916 def Insert_Element_v2f32_#Index : Insert_Element <
1917 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1921 foreach Index = 0-3 in {
1922 def Extract_Element_v4i32_#Index : Extract_Element <
1923 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1925 def Insert_Element_v4i32_#Index : Insert_Element <
1926 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1929 def Extract_Element_v4f32_#Index : Extract_Element <
1930 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1932 def Insert_Element_v4f32_#Index : Insert_Element <
1933 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1937 foreach Index = 0-7 in {
1938 def Extract_Element_v8i32_#Index : Extract_Element <
1939 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1941 def Insert_Element_v8i32_#Index : Insert_Element <
1942 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1945 def Extract_Element_v8f32_#Index : Extract_Element <
1946 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1948 def Insert_Element_v8f32_#Index : Insert_Element <
1949 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1953 foreach Index = 0-15 in {
1954 def Extract_Element_v16i32_#Index : Extract_Element <
1955 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1957 def Insert_Element_v16i32_#Index : Insert_Element <
1958 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1961 def Extract_Element_v16f32_#Index : Extract_Element <
1962 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1964 def Insert_Element_v16f32_#Index : Insert_Element <
1965 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1969 def : BitConvert <i32, f32, SReg_32>;
1970 def : BitConvert <i32, f32, VReg_32>;
1972 def : BitConvert <f32, i32, SReg_32>;
1973 def : BitConvert <f32, i32, VReg_32>;
1975 def : BitConvert <i64, f64, VReg_64>;
1977 def : BitConvert <f64, i64, VReg_64>;
1979 def : BitConvert <v2f32, v2i32, VReg_64>;
1980 def : BitConvert <v2i32, v2f32, VReg_64>;
1981 def : BitConvert <v2i32, i64, VReg_64>;
1982 def : BitConvert <i64, v2i32, VReg_64>;
1983 def : BitConvert <v2f32, i64, VReg_64>;
1984 def : BitConvert <i64, v2f32, VReg_64>;
1985 def : BitConvert <v2i32, f64, VReg_64>;
1986 def : BitConvert <f64, v2i32, VReg_64>;
1987 def : BitConvert <v4f32, v4i32, VReg_128>;
1988 def : BitConvert <v4i32, v4f32, VReg_128>;
1990 def : BitConvert <v8f32, v8i32, SReg_256>;
1991 def : BitConvert <v8i32, v8f32, SReg_256>;
1992 def : BitConvert <v8i32, v32i8, SReg_256>;
1993 def : BitConvert <v32i8, v8i32, SReg_256>;
1994 def : BitConvert <v8i32, v32i8, VReg_256>;
1995 def : BitConvert <v8i32, v8f32, VReg_256>;
1996 def : BitConvert <v8f32, v8i32, VReg_256>;
1997 def : BitConvert <v32i8, v8i32, VReg_256>;
1999 def : BitConvert <v16i32, v16f32, VReg_512>;
2000 def : BitConvert <v16f32, v16i32, VReg_512>;
2002 /********** =================== **********/
2003 /********** Src & Dst modifiers **********/
2004 /********** =================== **********/
2006 def FCLAMP_SI : AMDGPUShaderInst <
2007 (outs VReg_32:$dst),
2008 (ins VSrc_32:$src0),
2009 "FCLAMP_SI $dst, $src0",
2012 let usesCustomInserter = 1;
2016 (AMDGPUclamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
2017 (FCLAMP_SI f32:$src)
2020 /********** ================================ **********/
2021 /********** Floating point absolute/negative **********/
2022 /********** ================================ **********/
2024 // Manipulate the sign bit directly, as e.g. using the source negation modifier
2025 // in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0,
2026 // breaking the piglit *s-floatBitsToInt-neg* tests
2028 // TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly
2029 // removing these patterns
2032 (fneg (fabs f32:$src)),
2033 (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
2036 def FABS_SI : AMDGPUShaderInst <
2037 (outs VReg_32:$dst),
2038 (ins VSrc_32:$src0),
2039 "FABS_SI $dst, $src0",
2042 let usesCustomInserter = 1;
2050 def FNEG_SI : AMDGPUShaderInst <
2051 (outs VReg_32:$dst),
2052 (ins VSrc_32:$src0),
2053 "FNEG_SI $dst, $src0",
2056 let usesCustomInserter = 1;
2064 /********** ================== **********/
2065 /********** Immediate Patterns **********/
2066 /********** ================== **********/
2069 (SGPRImm<(i32 imm)>:$imm),
2070 (S_MOV_B32 imm:$imm)
2074 (SGPRImm<(f32 fpimm)>:$imm),
2075 (S_MOV_B32 fpimm:$imm)
2080 (V_MOV_B32_e32 imm:$imm)
2085 (V_MOV_B32_e32 fpimm:$imm)
2089 (i64 InlineImm<i64>:$imm),
2090 (S_MOV_B64 InlineImm<i64>:$imm)
2093 /********** ===================== **********/
2094 /********** Interpolation Paterns **********/
2095 /********** ===================== **********/
2098 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params),
2099 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params)
2103 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij),
2104 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0),
2105 imm:$attr_chan, imm:$attr, i32:$params),
2106 (EXTRACT_SUBREG $ij, sub1),
2107 imm:$attr_chan, imm:$attr, $params)
2110 /********** ================== **********/
2111 /********** Intrinsic Patterns **********/
2112 /********** ================== **********/
2114 /* llvm.AMDGPU.pow */
2115 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
2118 (int_AMDGPU_div f32:$src0, f32:$src1),
2119 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1))
2123 (fdiv f32:$src0, f32:$src1),
2124 (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1))
2128 (fdiv f64:$src0, f64:$src1),
2129 (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0))
2134 (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
2139 (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
2143 (int_AMDGPU_cube v4f32:$src),
2144 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2145 (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0),
2146 (EXTRACT_SUBREG $src, sub1),
2147 (EXTRACT_SUBREG $src, sub2)),
2149 (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0),
2150 (EXTRACT_SUBREG $src, sub1),
2151 (EXTRACT_SUBREG $src, sub2)),
2153 (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0),
2154 (EXTRACT_SUBREG $src, sub1),
2155 (EXTRACT_SUBREG $src, sub2)),
2157 (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0),
2158 (EXTRACT_SUBREG $src, sub1),
2159 (EXTRACT_SUBREG $src, sub2)),
2164 (i32 (sext i1:$src0)),
2165 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
2168 class Ext32Pat <SDNode ext> : Pat <
2169 (i32 (ext i1:$src0)),
2170 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
2173 def : Ext32Pat <zext>;
2174 def : Ext32Pat <anyext>;
2176 // Offset in an 32Bit VGPR
2178 (SIload_constant v4i32:$sbase, i32:$voff),
2179 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0)
2182 // The multiplication scales from [0,1] to the unsigned integer range
2184 (AMDGPUurecip i32:$src0),
2186 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
2187 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
2192 (V_MBCNT_HI_U32_B32_e32 0xffffffff,
2193 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0))
2196 //===----------------------------------------------------------------------===//
2198 //===----------------------------------------------------------------------===//
2200 def : IMad24Pat<V_MAD_I32_I24>;
2201 def : UMad24Pat<V_MAD_U32_U24>;
2204 (fadd f64:$src0, f64:$src1),
2205 (V_ADD_F64 $src0, $src1, (i64 0))
2209 (fmul f64:$src0, f64:$src1),
2210 (V_MUL_F64 $src0, $src1, (i64 0))
2214 (mul i32:$src0, i32:$src1),
2215 (V_MUL_LO_I32 $src0, $src1, (i32 0))
2219 (mulhu i32:$src0, i32:$src1),
2220 (V_MUL_HI_U32 $src0, $src1, (i32 0))
2224 (mulhs i32:$src0, i32:$src1),
2225 (V_MUL_HI_I32 $src0, $src1, (i32 0))
2228 defm : BFIPatterns <V_BFI_B32, S_MOV_B32>;
2229 def : ROTRPattern <V_ALIGNBIT_B32>;
2231 /********** ======================= **********/
2232 /********** Load/Store Patterns **********/
2233 /********** ======================= **********/
2235 multiclass DSReadPat <DS inst, ValueType vt, PatFrag frag> {
2237 (vt (frag (add i32:$ptr, (i32 IMM16bit:$offset)))),
2238 (inst (i1 0), $ptr, (as_i16imm $offset))
2243 (vt (inst 0, $src0, 0))
2247 defm : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
2248 defm : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
2249 defm : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
2250 defm : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
2251 defm : DSReadPat <DS_READ_B32, i32, local_load>;
2252 defm : DSReadPat <DS_READ_B64, i64, local_load>;
2254 multiclass DSWritePat <DS inst, ValueType vt, PatFrag frag> {
2256 (frag vt:$value, (add i32:$ptr, (i32 IMM16bit:$offset))),
2257 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2261 (frag vt:$val, i32:$ptr),
2262 (inst 0, $ptr, $val, 0)
2266 defm : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
2267 defm : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
2268 defm : DSWritePat <DS_WRITE_B32, i32, local_store>;
2269 defm : DSWritePat <DS_WRITE_B64, i64, local_store>;
2271 multiclass DSAtomicRetPat<DS inst, ValueType vt, PatFrag frag> {
2273 (frag (add i32:$ptr, (i32 IMM16bit:$offset)), vt:$value),
2274 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2278 (frag i32:$ptr, vt:$val),
2279 (inst 0, $ptr, $val, 0)
2283 // Special case of DSAtomicRetPat for add / sub 1 -> inc / dec
2285 // We need to use something for the data0, so we set a register to
2286 // -1. For the non-rtn variants, the manual says it does
2287 // DS[A] = (DS[A] >= D0) ? 0 : DS[A] + 1, and setting D0 to uint_max
2288 // will always do the increment so I'm assuming it's the same.
2290 // We also load this -1 with s_mov_b32 / s_mov_b64 even though this
2291 // needs to be a VGPR. The SGPR copy pass will fix this, and it's
2292 // easier since there is no v_mov_b64.
2293 multiclass DSAtomicIncRetPat<DS inst, ValueType vt,
2294 Instruction LoadImm, PatFrag frag> {
2296 (frag (add i32:$ptr, (i32 IMM16bit:$offset)), (vt 1)),
2297 (inst (i1 0), $ptr, (LoadImm (vt -1)), (as_i16imm $offset))
2301 (frag i32:$ptr, (vt 1)),
2302 (inst 0, $ptr, (LoadImm (vt -1)), 0)
2306 multiclass DSAtomicCmpXChg <DS inst, ValueType vt, PatFrag frag> {
2308 (frag (add i32:$ptr, (i32 IMM16bit:$offset)), vt:$cmp, vt:$swap),
2309 (inst (i1 0), $ptr, $cmp, $swap, (as_i16imm $offset))
2313 (frag i32:$ptr, vt:$cmp, vt:$swap),
2314 (inst 0, $ptr, $cmp, $swap, 0)
2320 defm : DSAtomicIncRetPat<DS_INC_RTN_U32, i32,
2321 S_MOV_B32, atomic_load_add_local>;
2322 defm : DSAtomicIncRetPat<DS_DEC_RTN_U32, i32,
2323 S_MOV_B32, atomic_load_sub_local>;
2325 defm : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, atomic_swap_local>;
2326 defm : DSAtomicRetPat<DS_ADD_RTN_U32, i32, atomic_load_add_local>;
2327 defm : DSAtomicRetPat<DS_SUB_RTN_U32, i32, atomic_load_sub_local>;
2328 defm : DSAtomicRetPat<DS_AND_RTN_B32, i32, atomic_load_and_local>;
2329 defm : DSAtomicRetPat<DS_OR_RTN_B32, i32, atomic_load_or_local>;
2330 defm : DSAtomicRetPat<DS_XOR_RTN_B32, i32, atomic_load_xor_local>;
2331 defm : DSAtomicRetPat<DS_MIN_RTN_I32, i32, atomic_load_min_local>;
2332 defm : DSAtomicRetPat<DS_MAX_RTN_I32, i32, atomic_load_max_local>;
2333 defm : DSAtomicRetPat<DS_MIN_RTN_U32, i32, atomic_load_umin_local>;
2334 defm : DSAtomicRetPat<DS_MAX_RTN_U32, i32, atomic_load_umax_local>;
2336 defm : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, atomic_cmp_swap_32_local>;
2339 defm : DSAtomicIncRetPat<DS_INC_RTN_U64, i64,
2340 S_MOV_B64, atomic_load_add_local>;
2341 defm : DSAtomicIncRetPat<DS_DEC_RTN_U64, i64,
2342 S_MOV_B64, atomic_load_sub_local>;
2344 defm : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, atomic_swap_local>;
2345 defm : DSAtomicRetPat<DS_ADD_RTN_U64, i64, atomic_load_add_local>;
2346 defm : DSAtomicRetPat<DS_SUB_RTN_U64, i64, atomic_load_sub_local>;
2347 defm : DSAtomicRetPat<DS_AND_RTN_B64, i64, atomic_load_and_local>;
2348 defm : DSAtomicRetPat<DS_OR_RTN_B64, i64, atomic_load_or_local>;
2349 defm : DSAtomicRetPat<DS_XOR_RTN_B64, i64, atomic_load_xor_local>;
2350 defm : DSAtomicRetPat<DS_MIN_RTN_I64, i64, atomic_load_min_local>;
2351 defm : DSAtomicRetPat<DS_MAX_RTN_I64, i64, atomic_load_max_local>;
2352 defm : DSAtomicRetPat<DS_MIN_RTN_U64, i64, atomic_load_umin_local>;
2353 defm : DSAtomicRetPat<DS_MAX_RTN_U64, i64, atomic_load_umax_local>;
2355 defm : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, atomic_cmp_swap_64_local>;
2358 //===----------------------------------------------------------------------===//
2360 //===----------------------------------------------------------------------===//
2362 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
2363 PatFrag global_ld, PatFrag constant_ld> {
2365 (vt (global_ld (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset))),
2366 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset))
2370 (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))),
2371 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset))
2375 (vt (global_ld i64:$ptr)),
2376 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
2380 (vt (global_ld (add i64:$ptr, i64:$offset))),
2381 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
2385 (vt (constant_ld (add i64:$ptr, i64:$offset))),
2386 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
2390 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32,
2391 sextloadi8_global, sextloadi8_constant>;
2392 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32,
2393 az_extloadi8_global, az_extloadi8_constant>;
2394 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32,
2395 sextloadi16_global, sextloadi16_constant>;
2396 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32,
2397 az_extloadi16_global, az_extloadi16_constant>;
2398 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32,
2399 global_load, constant_load>;
2400 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64,
2401 global_load, constant_load>;
2402 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64,
2403 az_extloadi32_global, az_extloadi32_constant>;
2404 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32,
2405 global_load, constant_load>;
2406 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32,
2407 global_load, constant_load>;
2409 multiclass MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> {
2412 (st vt:$value, (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset)),
2413 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset))
2417 (st vt:$value, (add i64:$ptr, IMM12bit:$offset)),
2418 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset))
2422 (st vt:$value, i64:$ptr),
2423 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
2427 (st vt:$value, (add i64:$ptr, i64:$offset)),
2428 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0)
2432 defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE, i32, truncstorei8_global>;
2433 defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT, i32, truncstorei16_global>;
2434 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32, global_store>;
2435 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>;
2436 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>;
2437 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>;
2439 // BUFFER_LOAD_DWORD*, addr64=0
2440 multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
2444 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2445 imm:$offset, 0, 0, imm:$glc, imm:$slc,
2447 (offset $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2448 (as_i1imm $slc), (as_i1imm $tfe))
2452 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2453 imm, 1, 0, imm:$glc, imm:$slc,
2455 (offen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2460 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2461 imm:$offset, 0, 1, imm:$glc, imm:$slc,
2463 (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2464 (as_i1imm $slc), (as_i1imm $tfe))
2468 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset,
2469 imm, 1, 1, imm:$glc, imm:$slc,
2471 (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2476 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
2477 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
2478 defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
2479 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
2480 defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
2481 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
2483 //===----------------------------------------------------------------------===//
2485 //===----------------------------------------------------------------------===//
2487 // TBUFFER_STORE_FORMAT_*, addr64=0
2488 class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
2489 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
2490 i32:$soffset, imm:$inst_offset, imm:$dfmt,
2491 imm:$nfmt, imm:$offen, imm:$idxen,
2492 imm:$glc, imm:$slc, imm:$tfe),
2494 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
2495 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
2496 (as_i1imm $slc), (as_i1imm $tfe), $soffset)
2499 def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
2500 def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
2501 def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
2502 def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
2504 let SubtargetPredicate = isCI in {
2506 // Sea island new arithmetic instructinos
2507 let neverHasSideEffects = 1 in {
2508 defm V_TRUNC_F64 : VOP1_64 <0x00000017, "V_TRUNC_F64",
2509 [(set f64:$dst, (ftrunc f64:$src0))]
2511 defm V_CEIL_F64 : VOP1_64 <0x00000018, "V_CEIL_F64",
2512 [(set f64:$dst, (fceil f64:$src0))]
2514 defm V_FLOOR_F64 : VOP1_64 <0x0000001A, "V_FLOOR_F64",
2515 [(set f64:$dst, (ffloor f64:$src0))]
2517 defm V_RNDNE_F64 : VOP1_64 <0x00000019, "V_RNDNE_F64",
2518 [(set f64:$dst, (frint f64:$src0))]
2521 defm V_QSAD_PK_U16_U8 : VOP3_32 <0x00000173, "V_QSAD_PK_U16_U8", []>;
2522 defm V_MQSAD_U16_U8 : VOP3_32 <0x000000172, "V_MQSAD_U16_U8", []>;
2523 defm V_MQSAD_U32_U8 : VOP3_32 <0x00000175, "V_MQSAD_U32_U8", []>;
2524 def V_MAD_U64_U32 : VOP3_64 <0x00000176, "V_MAD_U64_U32", []>;
2526 // XXX - Does this set VCC?
2527 def V_MAD_I64_I32 : VOP3_64 <0x00000177, "V_MAD_I64_I32", []>;
2528 } // End neverHasSideEffects = 1
2530 // Remaining instructions:
2532 // S_CBRANCH_CDBGUSER
2533 // S_CBRANCH_CDBGSYS
2534 // S_CBRANCH_CDBGSYS_OR_USER
2535 // S_CBRANCH_CDBGSYS_AND_USER
2540 // DS_GWS_SEMA_RELEASE_ALL
2542 // DS_CNDXCHG32_RTN_B64
2545 // DS_CONDXCHG32_RTN_B128
2548 // BUFFER_LOAD_DWORDX3
2549 // BUFFER_STORE_DWORDX3
2554 /********** ====================== **********/
2555 /********** Indirect adressing **********/
2556 /********** ====================== **********/
2558 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> {
2560 // 1. Extract with offset
2562 (vector_extract vt:$vec, (add i32:$idx, imm:$off)),
2563 (eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off))
2566 // 2. Extract without offset
2568 (vector_extract vt:$vec, i32:$idx),
2569 (eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0))
2572 // 3. Insert with offset
2574 (vector_insert vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)),
2575 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val)
2578 // 4. Insert without offset
2580 (vector_insert vt:$vec, eltvt:$val, i32:$idx),
2581 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val)
2585 defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>;
2586 defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>;
2587 defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>;
2588 defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>;
2590 defm : SI_INDIRECT_Pattern <v2i32, i32, SI_INDIRECT_DST_V2>;
2591 defm : SI_INDIRECT_Pattern <v4i32, i32, SI_INDIRECT_DST_V4>;
2592 defm : SI_INDIRECT_Pattern <v8i32, i32, SI_INDIRECT_DST_V8>;
2593 defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>;
2595 //===----------------------------------------------------------------------===//
2596 // Conversion Patterns
2597 //===----------------------------------------------------------------------===//
2599 def : Pat<(i32 (sext_inreg i32:$src, i1)),
2600 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16
2602 // TODO: Match 64-bit BFE. SI has a 64-bit BFE, but it's scalar only so it
2603 // might not be worth the effort, and will need to expand to shifts when
2604 // fixing SGPR copies.
2606 // Handle sext_inreg in i64
2608 (i64 (sext_inreg i64:$src, i1)),
2609 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2610 (S_BFE_I32 (EXTRACT_SUBREG i64:$src, sub0), 65536), sub0), // 0 | 1 << 16
2611 (S_MOV_B32 -1), sub1)
2615 (i64 (sext_inreg i64:$src, i8)),
2616 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2617 (S_SEXT_I32_I8 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
2618 (S_MOV_B32 -1), sub1)
2622 (i64 (sext_inreg i64:$src, i16)),
2623 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2624 (S_SEXT_I32_I16 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
2625 (S_MOV_B32 -1), sub1)
2628 class ZExt_i64_i32_Pat <SDNode ext> : Pat <
2629 (i64 (ext i32:$src)),
2630 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub0),
2631 (S_MOV_B32 0), sub1)
2634 class ZExt_i64_i1_Pat <SDNode ext> : Pat <
2635 (i64 (ext i1:$src)),
2637 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2638 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0),
2639 (S_MOV_B32 0), sub1)
2643 def : ZExt_i64_i32_Pat<zext>;
2644 def : ZExt_i64_i32_Pat<anyext>;
2645 def : ZExt_i64_i1_Pat<zext>;
2646 def : ZExt_i64_i1_Pat<anyext>;
2649 (i64 (sext i32:$src)),
2651 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub0),
2652 (S_ASHR_I32 $src, 31), sub1)
2656 (i64 (sext i1:$src)),
2659 (i64 (IMPLICIT_DEF)),
2660 (V_CNDMASK_B32_e64 0, -1, $src), sub0),
2661 (V_CNDMASK_B32_e64 0, -1, $src), sub1)
2665 (f32 (sint_to_fp i1:$src)),
2666 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src)
2670 (f32 (uint_to_fp i1:$src)),
2671 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src)
2675 (f64 (sint_to_fp i1:$src)),
2676 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src))
2680 (f64 (uint_to_fp i1:$src)),
2681 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src))
2684 //===----------------------------------------------------------------------===//
2685 // Miscellaneous Patterns
2686 //===----------------------------------------------------------------------===//
2689 (i32 (trunc i64:$a)),
2690 (EXTRACT_SUBREG $a, sub0)
2694 (i1 (trunc i32:$a)),
2695 (V_CMP_EQ_I32_e64 (V_AND_B32_e32 (i32 1), $a), 1)
2698 // V_ADD_I32_e32/S_ADD_I32 produces carry in VCC/SCC. For the vector
2699 // case, the sgpr-copies pass will fix this to use the vector version.
2701 (i32 (addc i32:$src0, i32:$src1)),
2702 (S_ADD_I32 $src0, $src1)
2706 (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)),
2707 (V_BCNT_U32_B32_e32 $popcnt, $val)
2711 (i64 (ctpop i64:$src)),
2712 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2713 (S_BCNT1_I32_B64 $src), sub0),
2714 (S_MOV_B32 0), sub1)
2717 //============================================================================//
2718 // Miscellaneous Optimization Patterns
2719 //============================================================================//
2721 def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>;
2723 } // End isSI predicate