1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
14 class vopc <bits<8> si> : vop {
15 field bits<8> SI = si;
17 field bits<9> SI3 = {0, si{7-0}};
20 class vop1 <bits<8> si> : vop {
21 field bits<8> SI = si;
23 field bits<9> SI3 = {1, 1, si{6-0}};
26 class vop2 <bits<6> si> : vop {
27 field bits<6> SI = si;
29 field bits<9> SI3 = {1, 0, 0, si{5-0}};
32 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
33 // in AMDGPUMCInstLower.h
39 //===----------------------------------------------------------------------===//
41 //===----------------------------------------------------------------------===//
43 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
44 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
45 [SDNPMayLoad, SDNPMemOperand]
48 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
50 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
51 SDTCisVT<1, iAny>, // vdata(VGPR)
52 SDTCisVT<2, i32>, // num_channels(imm)
53 SDTCisVT<3, i32>, // vaddr(VGPR)
54 SDTCisVT<4, i32>, // soffset(SGPR)
55 SDTCisVT<5, i32>, // inst_offset(imm)
56 SDTCisVT<6, i32>, // dfmt(imm)
57 SDTCisVT<7, i32>, // nfmt(imm)
58 SDTCisVT<8, i32>, // offen(imm)
59 SDTCisVT<9, i32>, // idxen(imm)
60 SDTCisVT<10, i32>, // glc(imm)
61 SDTCisVT<11, i32>, // slc(imm)
62 SDTCisVT<12, i32> // tfe(imm)
64 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
67 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
68 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
72 class SDSample<string opcode> : SDNode <opcode,
73 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
74 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
77 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
78 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
79 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
80 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
82 def SIconstdata_ptr : SDNode<
83 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
86 // Transformation function, extract the lower 32bit of a 64bit immediate
87 def LO32 : SDNodeXForm<imm, [{
88 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
91 def LO32f : SDNodeXForm<fpimm, [{
92 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
93 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
96 // Transformation function, extract the upper 32bit of a 64bit immediate
97 def HI32 : SDNodeXForm<imm, [{
98 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
101 def HI32f : SDNodeXForm<fpimm, [{
102 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
103 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
106 def IMM8bitDWORD : PatLeaf <(imm),
107 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
110 def as_dword_i32imm : SDNodeXForm<imm, [{
111 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
114 def as_i1imm : SDNodeXForm<imm, [{
115 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
118 def as_i8imm : SDNodeXForm<imm, [{
119 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
122 def as_i16imm : SDNodeXForm<imm, [{
123 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
126 def as_i32imm: SDNodeXForm<imm, [{
127 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
130 def IMM8bit : PatLeaf <(imm),
131 [{return isUInt<8>(N->getZExtValue());}]
134 def IMM12bit : PatLeaf <(imm),
135 [{return isUInt<12>(N->getZExtValue());}]
138 def IMM16bit : PatLeaf <(imm),
139 [{return isUInt<16>(N->getZExtValue());}]
142 def IMM32bit : PatLeaf <(imm),
143 [{return isUInt<32>(N->getZExtValue());}]
146 def mubuf_vaddr_offset : PatFrag<
147 (ops node:$ptr, node:$offset, node:$imm_offset),
148 (add (add node:$ptr, node:$offset), node:$imm_offset)
151 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
152 return isInlineImmediate(N);
155 class SGPRImm <dag frag> : PatLeaf<frag, [{
156 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
157 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
160 const SIRegisterInfo *SIRI =
161 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
162 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
164 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
171 //===----------------------------------------------------------------------===//
173 //===----------------------------------------------------------------------===//
175 def FRAMEri32 : Operand<iPTR> {
176 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
179 def sopp_brtarget : Operand<OtherVT> {
180 let EncoderMethod = "getSOPPBrEncoding";
181 let OperandType = "OPERAND_PCREL";
184 include "SIInstrFormats.td"
186 let OperandType = "OPERAND_IMMEDIATE" in {
188 def offen : Operand<i1> {
189 let PrintMethod = "printOffen";
191 def idxen : Operand<i1> {
192 let PrintMethod = "printIdxen";
194 def addr64 : Operand<i1> {
195 let PrintMethod = "printAddr64";
197 def mbuf_offset : Operand<i16> {
198 let PrintMethod = "printMBUFOffset";
200 def glc : Operand <i1> {
201 let PrintMethod = "printGLC";
203 def slc : Operand <i1> {
204 let PrintMethod = "printSLC";
206 def tfe : Operand <i1> {
207 let PrintMethod = "printTFE";
210 def omod : Operand <i32> {
211 let PrintMethod = "printOModSI";
214 def ClampMod : Operand <i1> {
215 let PrintMethod = "printClampSI";
218 } // End OperandType = "OPERAND_IMMEDIATE"
220 //===----------------------------------------------------------------------===//
222 //===----------------------------------------------------------------------===//
224 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
225 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
227 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
228 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
229 def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
230 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
231 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
232 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
234 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
235 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
237 //===----------------------------------------------------------------------===//
238 // SI assembler operands
239 //===----------------------------------------------------------------------===//
259 //===----------------------------------------------------------------------===//
261 // SI Instruction multiclass helpers.
263 // Instructions with _32 take 32-bit operands.
264 // Instructions with _64 take 64-bit operands.
266 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
267 // encoding is the standard encoding, but instruction that make use of
268 // any of the instruction modifiers must use the 64-bit encoding.
270 // Instructions with _e32 use the 32-bit encoding.
271 // Instructions with _e64 use the 64-bit encoding.
273 //===----------------------------------------------------------------------===//
275 class SIMCInstr <string pseudo, int subtarget> {
276 string PseudoInstr = pseudo;
277 int Subtarget = subtarget;
280 //===----------------------------------------------------------------------===//
282 //===----------------------------------------------------------------------===//
284 class EXPCommon : InstSI<
286 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
287 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
288 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
297 let isPseudo = 1 in {
298 def "" : EXPCommon, SIMCInstr <"EXP", SISubtarget.NONE> ;
301 def _si : EXPCommon, SIMCInstr <"EXP", SISubtarget.SI>, EXPe;
304 //===----------------------------------------------------------------------===//
306 //===----------------------------------------------------------------------===//
308 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
309 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
310 opName#" $dst, $src0", pattern
313 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
314 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
315 opName#" $dst, $src0", pattern
318 // 64-bit input, 32-bit output.
319 class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
320 op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
321 opName#" $dst, $src0", pattern
324 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
325 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
326 opName#" $dst, $src0, $src1", pattern
329 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
330 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
331 opName#" $dst, $src0, $src1", pattern
334 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
335 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
336 opName#" $dst, $src0, $src1", pattern
340 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
341 string opName, PatLeaf cond> : SOPC <
342 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
343 opName#" $dst, $src0, $src1", []>;
345 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
346 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
348 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
349 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
351 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
352 op, (outs SReg_32:$dst), (ins i16imm:$src0),
353 opName#" $dst, $src0", pattern
356 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
357 op, (outs SReg_64:$dst), (ins i16imm:$src0),
358 opName#" $dst, $src0", pattern
361 //===----------------------------------------------------------------------===//
363 //===----------------------------------------------------------------------===//
365 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
366 SMRD <outs, ins, "", pattern>,
367 SIMCInstr<opName, SISubtarget.NONE> {
371 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
373 SMRD <outs, ins, asm, []>,
375 SIMCInstr<opName, SISubtarget.SI>;
377 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
378 string asm, list<dag> pattern> {
380 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
382 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
386 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
387 RegisterClass dstClass> {
389 op, opName#"_IMM", 1, (outs dstClass:$dst),
390 (ins baseClass:$sbase, u32imm:$offset),
391 opName#" $dst, $sbase, $offset", []
394 defm _SGPR : SMRD_m <
395 op, opName#"_SGPR", 0, (outs dstClass:$dst),
396 (ins baseClass:$sbase, SReg_32:$soff),
397 opName#" $dst, $sbase, $soff", []
401 //===----------------------------------------------------------------------===//
402 // Vector ALU classes
403 //===----------------------------------------------------------------------===//
405 // This must always be right before the operand being input modified.
406 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
407 let PrintMethod = "printOperandAndMods";
409 def InputModsNoDefault : Operand <i32> {
410 let PrintMethod = "printOperandAndMods";
413 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
415 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
416 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
420 // Returns the register class to use for the destination of VOP[123C]
421 // instructions for the given VT.
422 class getVALUDstForVT<ValueType VT> {
423 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
426 // Returns the register class to use for source 0 of VOP[12C]
427 // instructions for the given VT.
428 class getVOPSrc0ForVT<ValueType VT> {
429 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
432 // Returns the register class to use for source 1 of VOP[12C] for the
434 class getVOPSrc1ForVT<ValueType VT> {
435 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
438 // Returns the register classes for the source arguments of a VOP[12C]
439 // instruction for the given SrcVTs.
440 class getInRC32 <list<ValueType> SrcVT> {
441 list<RegisterClass> ret = [
442 getVOPSrc0ForVT<SrcVT[0]>.ret,
443 getVOPSrc1ForVT<SrcVT[1]>.ret
447 // Returns the register class to use for sources of VOP3 instructions for the
449 class getVOP3SrcForVT<ValueType VT> {
450 RegisterClass ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
453 // Returns the register classes for the source arguments of a VOP3
454 // instruction for the given SrcVTs.
455 class getInRC64 <list<ValueType> SrcVT> {
456 list<RegisterClass> ret = [
457 getVOP3SrcForVT<SrcVT[0]>.ret,
458 getVOP3SrcForVT<SrcVT[1]>.ret,
459 getVOP3SrcForVT<SrcVT[2]>.ret
463 // Returns 1 if the source arguments have modifiers, 0 if they do not.
464 class hasModifiers<ValueType SrcVT> {
465 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
466 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
469 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
470 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
471 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
472 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
476 // Returns the input arguments for VOP3 instructions for the given SrcVT.
477 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
478 RegisterClass Src2RC, int NumSrcArgs,
482 !if (!eq(NumSrcArgs, 1),
483 !if (!eq(HasModifiers, 1),
484 // VOP1 with modifiers
485 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
486 ClampMod:$clamp, omod:$omod)
488 // VOP1 without modifiers
491 !if (!eq(NumSrcArgs, 2),
492 !if (!eq(HasModifiers, 1),
493 // VOP 2 with modifiers
494 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
495 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
496 ClampMod:$clamp, omod:$omod)
498 // VOP2 without modifiers
499 (ins Src0RC:$src0, Src1RC:$src1)
501 /* NumSrcArgs == 3 */,
502 !if (!eq(HasModifiers, 1),
503 // VOP3 with modifiers
504 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
505 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
506 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
507 ClampMod:$clamp, omod:$omod)
509 // VOP3 without modifiers
510 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
514 // Returns the assembly string for the inputs and outputs of a VOP[12C]
515 // instruction. This does not add the _e32 suffix, so it can be reused
517 class getAsm32 <int NumSrcArgs> {
518 string src1 = ", $src1";
519 string src2 = ", $src2";
520 string ret = " $dst, $src0"#
521 !if(!eq(NumSrcArgs, 1), "", src1)#
522 !if(!eq(NumSrcArgs, 3), src2, "");
525 // Returns the assembly string for the inputs and outputs of a VOP3
527 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
528 string src0 = "$src0_modifiers,";
529 string src1 = !if(!eq(NumSrcArgs, 1), "",
530 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
531 " $src1_modifiers,"));
532 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
534 !if(!eq(HasModifiers, 0),
535 getAsm32<NumSrcArgs>.ret,
536 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
540 class VOPProfile <list<ValueType> _ArgVT> {
542 field list<ValueType> ArgVT = _ArgVT;
544 field ValueType DstVT = ArgVT[0];
545 field ValueType Src0VT = ArgVT[1];
546 field ValueType Src1VT = ArgVT[2];
547 field ValueType Src2VT = ArgVT[3];
548 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
549 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
550 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
551 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
552 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
553 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
555 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
556 field bit HasModifiers = hasModifiers<Src0VT>.ret;
558 field dag Outs = (outs DstRC:$dst);
560 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
561 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
564 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
565 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
568 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
569 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
570 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
571 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
572 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
573 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
574 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
575 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
576 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
578 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
579 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
580 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
581 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
582 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
583 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
584 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
585 let Src0RC32 = VCSrc_32;
587 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
588 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
590 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
591 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
592 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
593 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
596 class VOP <string opName> {
597 string OpName = opName;
600 class VOP2_REV <string revOp, bit isOrig> {
601 string RevOp = revOp;
605 class AtomicNoRet <string noRetOp, bit isRet> {
606 string NoRetOp = noRetOp;
610 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
611 VOP1Common <outs, ins, "", pattern>,
612 SIMCInstr<opName, SISubtarget.NONE> {
616 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
618 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
620 def _si : VOP1<op.SI, outs, ins, asm, []>,
621 SIMCInstr <opName, SISubtarget.SI>;
624 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
626 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
627 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
628 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
629 bits<2> omod = !if(HasModifiers, ?, 0);
630 bits<1> clamp = !if(HasModifiers, ?, 0);
631 bits<9> src1 = !if(HasSrc1, ?, 0);
632 bits<9> src2 = !if(HasSrc2, ?, 0);
635 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
636 VOP3Common <outs, ins, "", pattern>,
638 SIMCInstr<opName, SISubtarget.NONE> {
642 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
643 VOP3 <op, outs, ins, asm, []>,
644 SIMCInstr<opName, SISubtarget.SI>;
646 multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
647 string opName, int NumSrcArgs, bit HasMods = 1> {
649 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
651 def _si : VOP3_Real_si <op, outs, ins, asm, opName>,
652 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
653 !if(!eq(NumSrcArgs, 2), 0, 1),
658 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
659 list<dag> pattern, string opName, bit HasMods = 1> {
661 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
663 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
664 VOP3DisableFields<0, 0, HasMods>;
667 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
668 list<dag> pattern, string opName, string revOp,
669 bit HasMods = 1, bit UseFullOp = 0> {
671 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
672 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
674 def _si : VOP3_Real_si <op.SI3,
675 outs, ins, asm, opName>,
676 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>,
677 VOP3DisableFields<1, 0, HasMods>;
680 multiclass VOP3b_2_m <bits<9> op, dag outs, dag ins, string asm,
681 list<dag> pattern, string opName, string revOp,
682 bit HasMods = 1, bit UseFullOp = 0> {
683 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
684 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
686 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
687 // can write it into any SGPR. We currently don't use the carry out,
688 // so for now hardcode it to VCC as well.
689 let sdst = SIOperand.VCC, Defs = [VCC] in {
690 def _si : VOP3b <op, outs, ins, asm, pattern>,
691 VOP3DisableFields<1, 0, HasMods>,
692 SIMCInstr<opName, SISubtarget.SI>,
693 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
694 } // End sdst = SIOperand.VCC, Defs = [VCC]
697 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
698 list<dag> pattern, string opName,
699 bit HasMods, bit defExec> {
701 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
703 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
704 VOP3DisableFields<1, 0, HasMods> {
705 let Defs = !if(defExec, [EXEC], []);
709 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
710 dag ins32, string asm32, list<dag> pat32,
711 dag ins64, string asm64, list<dag> pat64,
714 def _e32 : VOP1 <op.SI, outs, ins32, opName#asm32, pat32>, VOP<opName>;
716 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
719 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
720 SDPatternOperator node = null_frag> : VOP1_Helper <
722 P.Ins32, P.Asm32, [],
725 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
726 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
727 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
731 class VOP2_e32 <bits<6> op, string opName, dag outs, dag ins, string asm,
732 list<dag> pattern, string revOp> :
733 VOP2 <op, outs, ins, opName#asm, pattern>,
735 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
737 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
738 dag ins32, string asm32, list<dag> pat32,
739 dag ins64, string asm64, list<dag> pat64,
740 string revOp, bit HasMods> {
741 def _e32 : VOP2_e32 <op.SI, opName, outs, ins32, asm32, pat32, revOp>;
743 defm _e64 : VOP3_2_m <op,
744 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
748 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
749 SDPatternOperator node = null_frag,
750 string revOp = opName> : VOP2_Helper <
752 P.Ins32, P.Asm32, [],
756 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
757 i1:$clamp, i32:$omod)),
758 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
759 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
760 revOp, P.HasModifiers
763 multiclass VOP2b_Helper <bits<6> op, string opName, dag outs,
764 dag ins32, string asm32, list<dag> pat32,
765 dag ins64, string asm64, list<dag> pat64,
766 string revOp, bit HasMods> {
768 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
770 defm _e64 : VOP3b_2_m <
771 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
772 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
776 multiclass VOP2bInst <bits<6> op, string opName, VOPProfile P,
777 SDPatternOperator node = null_frag,
778 string revOp = opName> : VOP2b_Helper <
780 P.Ins32, P.Asm32, [],
784 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
785 i1:$clamp, i32:$omod)),
786 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
787 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
788 revOp, P.HasModifiers
791 multiclass VOPC_Helper <vopc op, string opName,
792 dag ins32, string asm32, list<dag> pat32,
793 dag out64, dag ins64, string asm64, list<dag> pat64,
794 bit HasMods, bit DefExec> {
795 def _e32 : VOPC <op.SI, ins32, opName#asm32, pat32>, VOP <opName> {
796 let Defs = !if(DefExec, [EXEC], []);
799 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64, opName,
803 multiclass VOPCInst <vopc op, string opName,
804 VOPProfile P, PatLeaf cond = COND_NULL,
805 bit DefExec = 0> : VOPC_Helper <
807 P.Ins32, P.Asm32, [],
808 (outs SReg_64:$dst), P.Ins64, P.Asm64,
811 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
812 i1:$clamp, i32:$omod)),
813 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
815 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
816 P.HasModifiers, DefExec
819 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
820 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
822 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
823 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
825 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
826 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
828 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
829 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
832 multiclass VOPCX <vopc op, string opName, VOPProfile P,
833 PatLeaf cond = COND_NULL>
834 : VOPCInst <op, opName, P, cond, 1>;
836 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
837 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
839 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
840 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
842 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
843 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
845 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
846 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
848 multiclass VOP3_Helper <bits<9> op, string opName, dag outs, dag ins, string asm,
849 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
850 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
853 multiclass VOP3Inst <bits<9> op, string opName, VOPProfile P,
854 SDPatternOperator node = null_frag> : VOP3_Helper <
855 op, opName, P.Outs, P.Ins64, P.Asm64,
856 !if(!eq(P.NumSrcArgs, 3),
859 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
860 i1:$clamp, i32:$omod)),
861 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
862 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
863 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
865 !if(!eq(P.NumSrcArgs, 2),
868 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
869 i1:$clamp, i32:$omod)),
870 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
871 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
872 /* P.NumSrcArgs == 1 */,
875 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
876 i1:$clamp, i32:$omod))))],
877 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
878 P.NumSrcArgs, P.HasModifiers
881 multiclass VOP3b_Helper <bits<9> op, RegisterClass vrc, RegisterClass arc,
882 string opName, list<dag> pattern> :
884 op, (outs vrc:$dst0, SReg_64:$dst1),
885 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
886 InputModsNoDefault:$src1_modifiers, arc:$src1,
887 InputModsNoDefault:$src2_modifiers, arc:$src2,
888 ClampMod:$clamp, i32imm:$omod),
889 opName#" $dst0, $dst1, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
893 multiclass VOP3b_64 <bits<9> op, string opName, list<dag> pattern> :
894 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
896 multiclass VOP3b_32 <bits<9> op, string opName, list<dag> pattern> :
897 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
900 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
901 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
902 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
903 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
904 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
905 i32:$src1_modifiers, P.Src1VT:$src1,
906 i32:$src2_modifiers, P.Src2VT:$src2,
910 //===----------------------------------------------------------------------===//
911 // Vector I/O classes
912 //===----------------------------------------------------------------------===//
914 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
915 DS <op, outs, ins, asm, pat> {
918 // Single load interpret the 2 i8imm operands as a single i16 offset.
919 let offset0 = offset{7-0};
920 let offset1 = offset{15-8};
923 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
925 (outs regClass:$vdst),
926 (ins i1imm:$gds, VReg_32:$addr, u16imm:$offset),
927 asm#" $vdst, $addr, $offset, [M0]",
935 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
937 (outs regClass:$vdst),
938 (ins i1imm:$gds, VReg_32:$addr, u8imm:$offset0, u8imm:$offset1),
939 asm#" $vdst, $addr, $offset0, $offset1, [M0]",
947 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
950 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u16imm:$offset),
951 asm#" $addr, $data0, $offset [M0]",
959 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
962 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
963 u8imm:$offset0, u8imm:$offset1),
964 asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]",
971 // 1 address, 1 data.
972 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
975 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
976 asm#" $vdst, $addr, $data0, $offset, [M0]", []>,
977 AtomicNoRet<noRetOp, 1> {
983 let hasPostISelHook = 1; // Adjusted to no return version.
986 // 1 address, 2 data.
987 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
990 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
991 asm#" $vdst, $addr, $data0, $data1, $offset, [M0]",
993 AtomicNoRet<noRetOp, 1> {
997 let hasPostISelHook = 1; // Adjusted to no return version.
1000 // 1 address, 2 data.
1001 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
1004 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
1005 asm#" $addr, $data0, $data1, $offset, [M0]",
1007 AtomicNoRet<noRetOp, 0> {
1012 // 1 address, 1 data.
1013 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
1016 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
1017 asm#" $addr, $data0, $offset, [M0]",
1019 AtomicNoRet<noRetOp, 0> {
1026 //===----------------------------------------------------------------------===//
1028 //===----------------------------------------------------------------------===//
1030 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1031 MTBUF <outs, ins, "", pattern>,
1032 SIMCInstr<opName, SISubtarget.NONE> {
1036 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1038 MTBUF <outs, ins, asm, []>,
1040 SIMCInstr<opName, SISubtarget.SI>;
1042 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1043 list<dag> pattern> {
1045 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1047 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1051 let mayStore = 1, mayLoad = 0 in {
1053 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1054 RegisterClass regClass> : MTBUF_m <
1056 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1057 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
1058 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1059 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1060 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1063 } // mayStore = 1, mayLoad = 0
1065 let mayLoad = 1, mayStore = 0 in {
1067 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1068 RegisterClass regClass> : MTBUF_m <
1069 op, opName, (outs regClass:$dst),
1070 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1071 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
1072 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1073 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1074 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1077 } // mayLoad = 1, mayStore = 0
1079 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1081 bit IsAddr64 = is_addr64;
1082 string OpName = NAME # suffix;
1085 class MUBUFAtomicAddr64 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1086 : MUBUF <op, outs, ins, asm, pattern> {
1096 class MUBUFAtomicOffset <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1097 : MUBUF <op, outs, ins, asm, pattern> {
1107 multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
1108 ValueType vt, SDPatternOperator atomic> {
1110 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1112 // No return variants
1115 def _ADDR64 : MUBUFAtomicAddr64 <
1117 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1118 mbuf_offset:$offset, slc:$slc),
1119 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", []
1120 >, MUBUFAddr64Table<1>, AtomicNoRet<NAME#"_ADDR64", 0>;
1122 def _OFFSET : MUBUFAtomicOffset <
1124 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1125 SSrc_32:$soffset, slc:$slc),
1126 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", []
1127 >, MUBUFAddr64Table<0>, AtomicNoRet<NAME#"_OFFSET", 0>;
1130 // Variant that return values
1131 let glc = 1, Constraints = "$vdata = $vdata_in",
1132 DisableEncoding = "$vdata_in" in {
1134 def _RTN_ADDR64 : MUBUFAtomicAddr64 <
1135 op, (outs rc:$vdata),
1136 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1137 mbuf_offset:$offset, slc:$slc),
1138 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1140 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1141 i1:$slc), vt:$vdata_in))]
1142 >, MUBUFAddr64Table<1, "_RTN">, AtomicNoRet<NAME#"_ADDR64", 1>;
1144 def _RTN_OFFSET : MUBUFAtomicOffset <
1145 op, (outs rc:$vdata),
1146 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1147 SSrc_32:$soffset, slc:$slc),
1148 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1150 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1151 i1:$slc), vt:$vdata_in))]
1152 >, MUBUFAddr64Table<0, "_RTN">, AtomicNoRet<NAME#"_OFFSET", 1>;
1156 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1159 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
1160 ValueType load_vt = i32,
1161 SDPatternOperator ld = null_frag> {
1163 let lds = 0, mayLoad = 1 in {
1167 let offen = 0, idxen = 0, vaddr = 0 in {
1168 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
1169 (ins SReg_128:$srsrc,
1170 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1171 slc:$slc, tfe:$tfe),
1172 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1173 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1174 i32:$soffset, i16:$offset,
1175 i1:$glc, i1:$slc, i1:$tfe)))]>,
1176 MUBUFAddr64Table<0>;
1179 let offen = 1, idxen = 0 in {
1180 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
1181 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1182 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1184 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1187 let offen = 0, idxen = 1 in {
1188 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
1189 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1190 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1191 slc:$slc, tfe:$tfe),
1192 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1195 let offen = 1, idxen = 1 in {
1196 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
1197 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1198 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1199 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1203 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1204 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
1205 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1206 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1207 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1208 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
1213 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1214 ValueType store_vt, SDPatternOperator st> {
1216 let addr64 = 0, lds = 0 in {
1220 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1221 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1223 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1224 "$glc"#"$slc"#"$tfe",
1228 let offen = 0, idxen = 0, vaddr = 0 in {
1229 def _OFFSET : MUBUF <
1231 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1232 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1233 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1234 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1235 i16:$offset, i1:$glc, i1:$slc,
1237 >, MUBUFAddr64Table<0>;
1238 } // offen = 0, idxen = 0, vaddr = 0
1240 let offen = 1, idxen = 0 in {
1241 def _OFFEN : MUBUF <
1243 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1244 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1245 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1246 "$glc"#"$slc"#"$tfe",
1249 } // end offen = 1, idxen = 0
1251 } // End addr64 = 0, lds = 0
1253 def _ADDR64 : MUBUF <
1255 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1256 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1257 [(st store_vt:$vdata,
1258 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1272 let soffset = 128; // ZERO
1276 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1277 FLAT <op, (outs regClass:$data),
1278 (ins VReg_64:$addr),
1279 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1286 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1287 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1288 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1300 class MIMG_Mask <string op, int channels> {
1302 int Channels = channels;
1305 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1306 RegisterClass dst_rc,
1307 RegisterClass src_rc> : MIMG <
1309 (outs dst_rc:$vdata),
1310 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1311 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1313 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1314 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1319 let hasPostISelHook = 1;
1322 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1323 RegisterClass dst_rc,
1325 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1326 MIMG_Mask<asm#"_V1", channels>;
1327 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1328 MIMG_Mask<asm#"_V2", channels>;
1329 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1330 MIMG_Mask<asm#"_V4", channels>;
1333 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1334 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1335 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1336 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1337 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1340 class MIMG_Sampler_Helper <bits<7> op, string asm,
1341 RegisterClass dst_rc,
1342 RegisterClass src_rc> : MIMG <
1344 (outs dst_rc:$vdata),
1345 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1346 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1347 SReg_256:$srsrc, SReg_128:$ssamp),
1348 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1349 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1353 let hasPostISelHook = 1;
1356 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1357 RegisterClass dst_rc,
1359 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1360 MIMG_Mask<asm#"_V1", channels>;
1361 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1362 MIMG_Mask<asm#"_V2", channels>;
1363 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1364 MIMG_Mask<asm#"_V4", channels>;
1365 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1366 MIMG_Mask<asm#"_V8", channels>;
1367 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1368 MIMG_Mask<asm#"_V16", channels>;
1371 multiclass MIMG_Sampler <bits<7> op, string asm> {
1372 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1373 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1374 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1375 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1378 class MIMG_Gather_Helper <bits<7> op, string asm,
1379 RegisterClass dst_rc,
1380 RegisterClass src_rc> : MIMG <
1382 (outs dst_rc:$vdata),
1383 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1384 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1385 SReg_256:$srsrc, SReg_128:$ssamp),
1386 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1387 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1392 // DMASK was repurposed for GATHER4. 4 components are always
1393 // returned and DMASK works like a swizzle - it selects
1394 // the component to fetch. The only useful DMASK values are
1395 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1396 // (red,red,red,red) etc.) The ISA document doesn't mention
1398 // Therefore, disable all code which updates DMASK by setting these two:
1400 let hasPostISelHook = 0;
1403 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1404 RegisterClass dst_rc,
1406 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1407 MIMG_Mask<asm#"_V1", channels>;
1408 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1409 MIMG_Mask<asm#"_V2", channels>;
1410 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1411 MIMG_Mask<asm#"_V4", channels>;
1412 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1413 MIMG_Mask<asm#"_V8", channels>;
1414 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1415 MIMG_Mask<asm#"_V16", channels>;
1418 multiclass MIMG_Gather <bits<7> op, string asm> {
1419 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1420 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1421 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1422 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1425 //===----------------------------------------------------------------------===//
1426 // Vector instruction mappings
1427 //===----------------------------------------------------------------------===//
1429 // Maps an opcode in e32 form to its e64 equivalent
1430 def getVOPe64 : InstrMapping {
1431 let FilterClass = "VOP";
1432 let RowFields = ["OpName"];
1433 let ColFields = ["Size"];
1435 let ValueCols = [["8"]];
1438 // Maps an opcode in e64 form to its e32 equivalent
1439 def getVOPe32 : InstrMapping {
1440 let FilterClass = "VOP";
1441 let RowFields = ["OpName"];
1442 let ColFields = ["Size"];
1444 let ValueCols = [["4"]];
1447 // Maps an original opcode to its commuted version
1448 def getCommuteRev : InstrMapping {
1449 let FilterClass = "VOP2_REV";
1450 let RowFields = ["RevOp"];
1451 let ColFields = ["IsOrig"];
1453 let ValueCols = [["0"]];
1456 def getMaskedMIMGOp : InstrMapping {
1457 let FilterClass = "MIMG_Mask";
1458 let RowFields = ["Op"];
1459 let ColFields = ["Channels"];
1461 let ValueCols = [["1"], ["2"], ["3"] ];
1464 // Maps an commuted opcode to its original version
1465 def getCommuteOrig : InstrMapping {
1466 let FilterClass = "VOP2_REV";
1467 let RowFields = ["RevOp"];
1468 let ColFields = ["IsOrig"];
1470 let ValueCols = [["1"]];
1473 def isDS : InstrMapping {
1474 let FilterClass = "DS";
1475 let RowFields = ["Inst"];
1476 let ColFields = ["Size"];
1478 let ValueCols = [["8"]];
1481 def getMCOpcode : InstrMapping {
1482 let FilterClass = "SIMCInstr";
1483 let RowFields = ["PseudoInstr"];
1484 let ColFields = ["Subtarget"];
1485 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1486 let ValueCols = [[!cast<string>(SISubtarget.SI)]];
1489 def getAddr64Inst : InstrMapping {
1490 let FilterClass = "MUBUFAddr64Table";
1491 let RowFields = ["OpName"];
1492 let ColFields = ["IsAddr64"];
1494 let ValueCols = [["1"]];
1497 // Maps an atomic opcode to its version with a return value.
1498 def getAtomicRetOp : InstrMapping {
1499 let FilterClass = "AtomicNoRet";
1500 let RowFields = ["NoRetOp"];
1501 let ColFields = ["IsRet"];
1503 let ValueCols = [["1"]];
1506 // Maps an atomic opcode to its returnless version.
1507 def getAtomicNoRetOp : InstrMapping {
1508 let FilterClass = "AtomicNoRet";
1509 let RowFields = ["NoRetOp"];
1510 let ColFields = ["IsRet"];
1512 let ValueCols = [["0"]];
1515 include "SIInstructions.td"