1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
14 class vopc <bits<8> si> : vop {
15 field bits<8> SI = si;
17 field bits<9> SI3 = {0, si{7-0}};
20 class vop1 <bits<8> si> : vop {
21 field bits<8> SI = si;
23 field bits<9> SI3 = {1, 1, si{6-0}};
26 class vop2 <bits<6> si> : vop {
27 field bits<6> SI = si;
29 field bits<9> SI3 = {1, 0, 0, si{5-0}};
32 class vop3 <bits<9> si> : vop {
33 field bits<9> SI3 = si;
36 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
37 // in AMDGPUMCInstLower.h
43 //===----------------------------------------------------------------------===//
45 //===----------------------------------------------------------------------===//
47 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
48 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
49 [SDNPMayLoad, SDNPMemOperand]
52 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
54 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
55 SDTCisVT<1, iAny>, // vdata(VGPR)
56 SDTCisVT<2, i32>, // num_channels(imm)
57 SDTCisVT<3, i32>, // vaddr(VGPR)
58 SDTCisVT<4, i32>, // soffset(SGPR)
59 SDTCisVT<5, i32>, // inst_offset(imm)
60 SDTCisVT<6, i32>, // dfmt(imm)
61 SDTCisVT<7, i32>, // nfmt(imm)
62 SDTCisVT<8, i32>, // offen(imm)
63 SDTCisVT<9, i32>, // idxen(imm)
64 SDTCisVT<10, i32>, // glc(imm)
65 SDTCisVT<11, i32>, // slc(imm)
66 SDTCisVT<12, i32> // tfe(imm)
68 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
71 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
72 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
76 class SDSample<string opcode> : SDNode <opcode,
77 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
78 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
81 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
82 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
83 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
84 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
86 def SIconstdata_ptr : SDNode<
87 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
90 // Transformation function, extract the lower 32bit of a 64bit immediate
91 def LO32 : SDNodeXForm<imm, [{
92 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
95 def LO32f : SDNodeXForm<fpimm, [{
96 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
97 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
100 // Transformation function, extract the upper 32bit of a 64bit immediate
101 def HI32 : SDNodeXForm<imm, [{
102 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
105 def HI32f : SDNodeXForm<fpimm, [{
106 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
107 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
110 def IMM8bitDWORD : PatLeaf <(imm),
111 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
114 def as_dword_i32imm : SDNodeXForm<imm, [{
115 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
118 def as_i1imm : SDNodeXForm<imm, [{
119 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
122 def as_i8imm : SDNodeXForm<imm, [{
123 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
126 def as_i16imm : SDNodeXForm<imm, [{
127 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
130 def as_i32imm: SDNodeXForm<imm, [{
131 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
134 def IMM8bit : PatLeaf <(imm),
135 [{return isUInt<8>(N->getZExtValue());}]
138 def IMM12bit : PatLeaf <(imm),
139 [{return isUInt<12>(N->getZExtValue());}]
142 def IMM16bit : PatLeaf <(imm),
143 [{return isUInt<16>(N->getZExtValue());}]
146 def IMM32bit : PatLeaf <(imm),
147 [{return isUInt<32>(N->getZExtValue());}]
150 def mubuf_vaddr_offset : PatFrag<
151 (ops node:$ptr, node:$offset, node:$imm_offset),
152 (add (add node:$ptr, node:$offset), node:$imm_offset)
155 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
156 return isInlineImmediate(N);
159 class SGPRImm <dag frag> : PatLeaf<frag, [{
160 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
161 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
164 const SIRegisterInfo *SIRI =
165 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
166 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
168 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
175 //===----------------------------------------------------------------------===//
177 //===----------------------------------------------------------------------===//
179 def FRAMEri32 : Operand<iPTR> {
180 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
183 def sopp_brtarget : Operand<OtherVT> {
184 let EncoderMethod = "getSOPPBrEncoding";
185 let OperandType = "OPERAND_PCREL";
188 include "SIInstrFormats.td"
190 let OperandType = "OPERAND_IMMEDIATE" in {
192 def offen : Operand<i1> {
193 let PrintMethod = "printOffen";
195 def idxen : Operand<i1> {
196 let PrintMethod = "printIdxen";
198 def addr64 : Operand<i1> {
199 let PrintMethod = "printAddr64";
201 def mbuf_offset : Operand<i16> {
202 let PrintMethod = "printMBUFOffset";
204 def glc : Operand <i1> {
205 let PrintMethod = "printGLC";
207 def slc : Operand <i1> {
208 let PrintMethod = "printSLC";
210 def tfe : Operand <i1> {
211 let PrintMethod = "printTFE";
214 def omod : Operand <i32> {
215 let PrintMethod = "printOModSI";
218 def ClampMod : Operand <i1> {
219 let PrintMethod = "printClampSI";
222 } // End OperandType = "OPERAND_IMMEDIATE"
224 //===----------------------------------------------------------------------===//
226 //===----------------------------------------------------------------------===//
228 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
229 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
231 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
232 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
233 def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
234 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
235 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
236 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
238 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
239 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
241 //===----------------------------------------------------------------------===//
242 // SI assembler operands
243 //===----------------------------------------------------------------------===//
263 //===----------------------------------------------------------------------===//
265 // SI Instruction multiclass helpers.
267 // Instructions with _32 take 32-bit operands.
268 // Instructions with _64 take 64-bit operands.
270 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
271 // encoding is the standard encoding, but instruction that make use of
272 // any of the instruction modifiers must use the 64-bit encoding.
274 // Instructions with _e32 use the 32-bit encoding.
275 // Instructions with _e64 use the 64-bit encoding.
277 //===----------------------------------------------------------------------===//
279 class SIMCInstr <string pseudo, int subtarget> {
280 string PseudoInstr = pseudo;
281 int Subtarget = subtarget;
284 //===----------------------------------------------------------------------===//
286 //===----------------------------------------------------------------------===//
288 class EXPCommon : InstSI<
290 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
291 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
292 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
301 let isPseudo = 1 in {
302 def "" : EXPCommon, SIMCInstr <"EXP", SISubtarget.NONE> ;
305 def _si : EXPCommon, SIMCInstr <"EXP", SISubtarget.SI>, EXPe;
308 //===----------------------------------------------------------------------===//
310 //===----------------------------------------------------------------------===//
312 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
313 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
314 opName#" $dst, $src0", pattern
317 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
318 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
319 opName#" $dst, $src0", pattern
322 // 64-bit input, 32-bit output.
323 class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
324 op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
325 opName#" $dst, $src0", pattern
328 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
329 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
330 opName#" $dst, $src0, $src1", pattern
333 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
334 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
335 opName#" $dst, $src0, $src1", pattern
338 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
339 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
340 opName#" $dst, $src0, $src1", pattern
344 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
345 string opName, PatLeaf cond> : SOPC <
346 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
347 opName#" $dst, $src0, $src1", []>;
349 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
350 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
352 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
353 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
355 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
356 op, (outs SReg_32:$dst), (ins i16imm:$src0),
357 opName#" $dst, $src0", pattern
360 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
361 op, (outs SReg_64:$dst), (ins i16imm:$src0),
362 opName#" $dst, $src0", pattern
365 //===----------------------------------------------------------------------===//
367 //===----------------------------------------------------------------------===//
369 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
370 SMRD <outs, ins, "", pattern>,
371 SIMCInstr<opName, SISubtarget.NONE> {
375 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
377 SMRD <outs, ins, asm, []>,
379 SIMCInstr<opName, SISubtarget.SI>;
381 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
382 string asm, list<dag> pattern> {
384 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
386 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
390 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
391 RegisterClass dstClass> {
393 op, opName#"_IMM", 1, (outs dstClass:$dst),
394 (ins baseClass:$sbase, u32imm:$offset),
395 opName#" $dst, $sbase, $offset", []
398 defm _SGPR : SMRD_m <
399 op, opName#"_SGPR", 0, (outs dstClass:$dst),
400 (ins baseClass:$sbase, SReg_32:$soff),
401 opName#" $dst, $sbase, $soff", []
405 //===----------------------------------------------------------------------===//
406 // Vector ALU classes
407 //===----------------------------------------------------------------------===//
409 // This must always be right before the operand being input modified.
410 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
411 let PrintMethod = "printOperandAndMods";
413 def InputModsNoDefault : Operand <i32> {
414 let PrintMethod = "printOperandAndMods";
417 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
419 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
420 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
424 // Returns the register class to use for the destination of VOP[123C]
425 // instructions for the given VT.
426 class getVALUDstForVT<ValueType VT> {
427 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
430 // Returns the register class to use for source 0 of VOP[12C]
431 // instructions for the given VT.
432 class getVOPSrc0ForVT<ValueType VT> {
433 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
436 // Returns the register class to use for source 1 of VOP[12C] for the
438 class getVOPSrc1ForVT<ValueType VT> {
439 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
442 // Returns the register classes for the source arguments of a VOP[12C]
443 // instruction for the given SrcVTs.
444 class getInRC32 <list<ValueType> SrcVT> {
445 list<RegisterClass> ret = [
446 getVOPSrc0ForVT<SrcVT[0]>.ret,
447 getVOPSrc1ForVT<SrcVT[1]>.ret
451 // Returns the register class to use for sources of VOP3 instructions for the
453 class getVOP3SrcForVT<ValueType VT> {
454 RegisterClass ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
457 // Returns the register classes for the source arguments of a VOP3
458 // instruction for the given SrcVTs.
459 class getInRC64 <list<ValueType> SrcVT> {
460 list<RegisterClass> ret = [
461 getVOP3SrcForVT<SrcVT[0]>.ret,
462 getVOP3SrcForVT<SrcVT[1]>.ret,
463 getVOP3SrcForVT<SrcVT[2]>.ret
467 // Returns 1 if the source arguments have modifiers, 0 if they do not.
468 class hasModifiers<ValueType SrcVT> {
469 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
470 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
473 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
474 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
475 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
476 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
480 // Returns the input arguments for VOP3 instructions for the given SrcVT.
481 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
482 RegisterClass Src2RC, int NumSrcArgs,
486 !if (!eq(NumSrcArgs, 1),
487 !if (!eq(HasModifiers, 1),
488 // VOP1 with modifiers
489 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
490 ClampMod:$clamp, omod:$omod)
492 // VOP1 without modifiers
495 !if (!eq(NumSrcArgs, 2),
496 !if (!eq(HasModifiers, 1),
497 // VOP 2 with modifiers
498 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
499 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
500 ClampMod:$clamp, omod:$omod)
502 // VOP2 without modifiers
503 (ins Src0RC:$src0, Src1RC:$src1)
505 /* NumSrcArgs == 3 */,
506 !if (!eq(HasModifiers, 1),
507 // VOP3 with modifiers
508 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
509 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
510 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
511 ClampMod:$clamp, omod:$omod)
513 // VOP3 without modifiers
514 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
518 // Returns the assembly string for the inputs and outputs of a VOP[12C]
519 // instruction. This does not add the _e32 suffix, so it can be reused
521 class getAsm32 <int NumSrcArgs> {
522 string src1 = ", $src1";
523 string src2 = ", $src2";
524 string ret = " $dst, $src0"#
525 !if(!eq(NumSrcArgs, 1), "", src1)#
526 !if(!eq(NumSrcArgs, 3), src2, "");
529 // Returns the assembly string for the inputs and outputs of a VOP3
531 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
532 string src0 = "$src0_modifiers,";
533 string src1 = !if(!eq(NumSrcArgs, 1), "",
534 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
535 " $src1_modifiers,"));
536 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
538 !if(!eq(HasModifiers, 0),
539 getAsm32<NumSrcArgs>.ret,
540 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
544 class VOPProfile <list<ValueType> _ArgVT> {
546 field list<ValueType> ArgVT = _ArgVT;
548 field ValueType DstVT = ArgVT[0];
549 field ValueType Src0VT = ArgVT[1];
550 field ValueType Src1VT = ArgVT[2];
551 field ValueType Src2VT = ArgVT[3];
552 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
553 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
554 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
555 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
556 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
557 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
559 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
560 field bit HasModifiers = hasModifiers<Src0VT>.ret;
562 field dag Outs = (outs DstRC:$dst);
564 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
565 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
568 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
569 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
572 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
573 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
574 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
575 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
576 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
577 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
578 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
579 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
580 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
582 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
583 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
584 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
585 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
586 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
587 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
588 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
589 let Src0RC32 = VCSrc_32;
591 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
592 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
594 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
595 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
596 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
597 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
600 class VOP <string opName> {
601 string OpName = opName;
604 class VOP2_REV <string revOp, bit isOrig> {
605 string RevOp = revOp;
609 class AtomicNoRet <string noRetOp, bit isRet> {
610 string NoRetOp = noRetOp;
614 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
615 VOP1Common <outs, ins, "", pattern>,
616 SIMCInstr<opName, SISubtarget.NONE> {
620 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
622 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
624 def _si : VOP1<op.SI, outs, ins, asm, []>,
625 SIMCInstr <opName, SISubtarget.SI>;
628 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
630 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
631 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
632 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
633 bits<2> omod = !if(HasModifiers, ?, 0);
634 bits<1> clamp = !if(HasModifiers, ?, 0);
635 bits<9> src1 = !if(HasSrc1, ?, 0);
636 bits<9> src2 = !if(HasSrc2, ?, 0);
639 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
640 VOP3Common <outs, ins, "", pattern>,
642 SIMCInstr<opName, SISubtarget.NONE> {
646 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
647 VOP3 <op, outs, ins, asm, []>,
648 SIMCInstr<opName, SISubtarget.SI>;
650 multiclass VOP3_m <vop3 op, dag outs, dag ins, string asm, list<dag> pattern,
651 string opName, int NumSrcArgs, bit HasMods = 1> {
653 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
655 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
656 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
657 !if(!eq(NumSrcArgs, 2), 0, 1),
662 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
663 list<dag> pattern, string opName, bit HasMods = 1> {
665 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
667 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
668 VOP3DisableFields<0, 0, HasMods>;
671 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
672 list<dag> pattern, string opName, string revOp,
673 bit HasMods = 1, bit UseFullOp = 0> {
675 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
676 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
678 def _si : VOP3_Real_si <op.SI3,
679 outs, ins, asm, opName>,
680 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>,
681 VOP3DisableFields<1, 0, HasMods>;
684 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
685 list<dag> pattern, string opName, string revOp,
686 bit HasMods = 1, bit UseFullOp = 0> {
687 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
688 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
690 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
691 // can write it into any SGPR. We currently don't use the carry out,
692 // so for now hardcode it to VCC as well.
693 let sdst = SIOperand.VCC, Defs = [VCC] in {
694 def _si : VOP3b <op.SI3, outs, ins, asm, pattern>,
695 VOP3DisableFields<1, 0, HasMods>,
696 SIMCInstr<opName, SISubtarget.SI>,
697 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
698 } // End sdst = SIOperand.VCC, Defs = [VCC]
701 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
702 list<dag> pattern, string opName,
703 bit HasMods, bit defExec> {
705 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
707 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
708 VOP3DisableFields<1, 0, HasMods> {
709 let Defs = !if(defExec, [EXEC], []);
713 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
714 dag ins32, string asm32, list<dag> pat32,
715 dag ins64, string asm64, list<dag> pat64,
718 def _e32 : VOP1 <op.SI, outs, ins32, opName#asm32, pat32>, VOP<opName>;
720 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
723 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
724 SDPatternOperator node = null_frag> : VOP1_Helper <
726 P.Ins32, P.Asm32, [],
729 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
730 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
731 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
735 class VOP2_e32 <bits<6> op, string opName, dag outs, dag ins, string asm,
736 list<dag> pattern, string revOp> :
737 VOP2 <op, outs, ins, opName#asm, pattern>,
739 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
741 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
742 dag ins32, string asm32, list<dag> pat32,
743 dag ins64, string asm64, list<dag> pat64,
744 string revOp, bit HasMods> {
745 def _e32 : VOP2_e32 <op.SI, opName, outs, ins32, asm32, pat32, revOp>;
747 defm _e64 : VOP3_2_m <op,
748 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
752 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
753 SDPatternOperator node = null_frag,
754 string revOp = opName> : VOP2_Helper <
756 P.Ins32, P.Asm32, [],
760 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
761 i1:$clamp, i32:$omod)),
762 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
763 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
764 revOp, P.HasModifiers
767 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
768 dag ins32, string asm32, list<dag> pat32,
769 dag ins64, string asm64, list<dag> pat64,
770 string revOp, bit HasMods> {
772 def _e32 : VOP2_e32 <op.SI, opName, outs, ins32, asm32, pat32, revOp>;
774 defm _e64 : VOP3b_2_m <op,
775 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
779 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
780 SDPatternOperator node = null_frag,
781 string revOp = opName> : VOP2b_Helper <
783 P.Ins32, P.Asm32, [],
787 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
788 i1:$clamp, i32:$omod)),
789 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
790 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
791 revOp, P.HasModifiers
794 multiclass VOPC_Helper <vopc op, string opName,
795 dag ins32, string asm32, list<dag> pat32,
796 dag out64, dag ins64, string asm64, list<dag> pat64,
797 bit HasMods, bit DefExec> {
798 def _e32 : VOPC <op.SI, ins32, opName#asm32, pat32>, VOP <opName> {
799 let Defs = !if(DefExec, [EXEC], []);
802 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64, opName,
806 multiclass VOPCInst <vopc op, string opName,
807 VOPProfile P, PatLeaf cond = COND_NULL,
808 bit DefExec = 0> : VOPC_Helper <
810 P.Ins32, P.Asm32, [],
811 (outs SReg_64:$dst), P.Ins64, P.Asm64,
814 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
815 i1:$clamp, i32:$omod)),
816 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
818 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
819 P.HasModifiers, DefExec
822 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
823 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
825 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
826 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
828 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
829 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
831 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
832 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
835 multiclass VOPCX <vopc op, string opName, VOPProfile P,
836 PatLeaf cond = COND_NULL>
837 : VOPCInst <op, opName, P, cond, 1>;
839 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
840 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
842 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
843 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
845 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
846 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
848 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
849 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
851 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
852 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
853 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
856 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
857 SDPatternOperator node = null_frag> : VOP3_Helper <
858 op, opName, P.Outs, P.Ins64, P.Asm64,
859 !if(!eq(P.NumSrcArgs, 3),
862 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
863 i1:$clamp, i32:$omod)),
864 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
865 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
866 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
868 !if(!eq(P.NumSrcArgs, 2),
871 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
872 i1:$clamp, i32:$omod)),
873 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
874 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
875 /* P.NumSrcArgs == 1 */,
878 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
879 i1:$clamp, i32:$omod))))],
880 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
881 P.NumSrcArgs, P.HasModifiers
884 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterClass arc,
885 string opName, list<dag> pattern> :
887 op, (outs vrc:$dst0, SReg_64:$dst1),
888 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
889 InputModsNoDefault:$src1_modifiers, arc:$src1,
890 InputModsNoDefault:$src2_modifiers, arc:$src2,
891 ClampMod:$clamp, i32imm:$omod),
892 opName#" $dst0, $dst1, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
896 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
897 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
899 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
900 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
903 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
904 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
905 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
906 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
907 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
908 i32:$src1_modifiers, P.Src1VT:$src1,
909 i32:$src2_modifiers, P.Src2VT:$src2,
913 //===----------------------------------------------------------------------===//
914 // Vector I/O classes
915 //===----------------------------------------------------------------------===//
917 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
918 DS <op, outs, ins, asm, pat> {
921 // Single load interpret the 2 i8imm operands as a single i16 offset.
922 let offset0 = offset{7-0};
923 let offset1 = offset{15-8};
926 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
928 (outs regClass:$vdst),
929 (ins i1imm:$gds, VReg_32:$addr, u16imm:$offset),
930 asm#" $vdst, $addr, $offset, [M0]",
938 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
940 (outs regClass:$vdst),
941 (ins i1imm:$gds, VReg_32:$addr, u8imm:$offset0, u8imm:$offset1),
942 asm#" $vdst, $addr, $offset0, $offset1, [M0]",
950 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
953 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u16imm:$offset),
954 asm#" $addr, $data0, $offset [M0]",
962 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
965 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
966 u8imm:$offset0, u8imm:$offset1),
967 asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]",
974 // 1 address, 1 data.
975 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
978 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
979 asm#" $vdst, $addr, $data0, $offset, [M0]", []>,
980 AtomicNoRet<noRetOp, 1> {
986 let hasPostISelHook = 1; // Adjusted to no return version.
989 // 1 address, 2 data.
990 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
993 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
994 asm#" $vdst, $addr, $data0, $data1, $offset, [M0]",
996 AtomicNoRet<noRetOp, 1> {
1000 let hasPostISelHook = 1; // Adjusted to no return version.
1003 // 1 address, 2 data.
1004 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
1007 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
1008 asm#" $addr, $data0, $data1, $offset, [M0]",
1010 AtomicNoRet<noRetOp, 0> {
1015 // 1 address, 1 data.
1016 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
1019 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
1020 asm#" $addr, $data0, $offset, [M0]",
1022 AtomicNoRet<noRetOp, 0> {
1029 //===----------------------------------------------------------------------===//
1031 //===----------------------------------------------------------------------===//
1033 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1034 MTBUF <outs, ins, "", pattern>,
1035 SIMCInstr<opName, SISubtarget.NONE> {
1039 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1041 MTBUF <outs, ins, asm, []>,
1043 SIMCInstr<opName, SISubtarget.SI>;
1045 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1046 list<dag> pattern> {
1048 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1050 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1054 let mayStore = 1, mayLoad = 0 in {
1056 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1057 RegisterClass regClass> : MTBUF_m <
1059 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1060 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
1061 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1062 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1063 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1066 } // mayStore = 1, mayLoad = 0
1068 let mayLoad = 1, mayStore = 0 in {
1070 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1071 RegisterClass regClass> : MTBUF_m <
1072 op, opName, (outs regClass:$dst),
1073 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1074 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
1075 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1076 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1077 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1080 } // mayLoad = 1, mayStore = 0
1082 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1084 bit IsAddr64 = is_addr64;
1085 string OpName = NAME # suffix;
1088 class MUBUFAtomicAddr64 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1089 : MUBUF <op, outs, ins, asm, pattern> {
1099 class MUBUFAtomicOffset <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1100 : MUBUF <op, outs, ins, asm, pattern> {
1110 multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
1111 ValueType vt, SDPatternOperator atomic> {
1113 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1115 // No return variants
1118 def _ADDR64 : MUBUFAtomicAddr64 <
1120 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1121 mbuf_offset:$offset, slc:$slc),
1122 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", []
1123 >, MUBUFAddr64Table<1>, AtomicNoRet<NAME#"_ADDR64", 0>;
1125 def _OFFSET : MUBUFAtomicOffset <
1127 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1128 SSrc_32:$soffset, slc:$slc),
1129 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", []
1130 >, MUBUFAddr64Table<0>, AtomicNoRet<NAME#"_OFFSET", 0>;
1133 // Variant that return values
1134 let glc = 1, Constraints = "$vdata = $vdata_in",
1135 DisableEncoding = "$vdata_in" in {
1137 def _RTN_ADDR64 : MUBUFAtomicAddr64 <
1138 op, (outs rc:$vdata),
1139 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1140 mbuf_offset:$offset, slc:$slc),
1141 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1143 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1144 i1:$slc), vt:$vdata_in))]
1145 >, MUBUFAddr64Table<1, "_RTN">, AtomicNoRet<NAME#"_ADDR64", 1>;
1147 def _RTN_OFFSET : MUBUFAtomicOffset <
1148 op, (outs rc:$vdata),
1149 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1150 SSrc_32:$soffset, slc:$slc),
1151 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1153 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1154 i1:$slc), vt:$vdata_in))]
1155 >, MUBUFAddr64Table<0, "_RTN">, AtomicNoRet<NAME#"_OFFSET", 1>;
1159 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1162 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
1163 ValueType load_vt = i32,
1164 SDPatternOperator ld = null_frag> {
1166 let lds = 0, mayLoad = 1 in {
1170 let offen = 0, idxen = 0, vaddr = 0 in {
1171 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
1172 (ins SReg_128:$srsrc,
1173 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1174 slc:$slc, tfe:$tfe),
1175 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1176 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1177 i32:$soffset, i16:$offset,
1178 i1:$glc, i1:$slc, i1:$tfe)))]>,
1179 MUBUFAddr64Table<0>;
1182 let offen = 1, idxen = 0 in {
1183 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
1184 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1185 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1187 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1190 let offen = 0, idxen = 1 in {
1191 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
1192 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1193 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1194 slc:$slc, tfe:$tfe),
1195 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1198 let offen = 1, idxen = 1 in {
1199 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
1200 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1201 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1202 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1206 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1207 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
1208 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1209 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1210 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1211 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
1216 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1217 ValueType store_vt, SDPatternOperator st> {
1219 let addr64 = 0, lds = 0 in {
1223 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1224 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1226 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1227 "$glc"#"$slc"#"$tfe",
1231 let offen = 0, idxen = 0, vaddr = 0 in {
1232 def _OFFSET : MUBUF <
1234 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1235 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1236 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1237 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1238 i16:$offset, i1:$glc, i1:$slc,
1240 >, MUBUFAddr64Table<0>;
1241 } // offen = 0, idxen = 0, vaddr = 0
1243 let offen = 1, idxen = 0 in {
1244 def _OFFEN : MUBUF <
1246 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1247 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1248 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1249 "$glc"#"$slc"#"$tfe",
1252 } // end offen = 1, idxen = 0
1254 } // End addr64 = 0, lds = 0
1256 def _ADDR64 : MUBUF <
1258 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1259 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1260 [(st store_vt:$vdata,
1261 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1275 let soffset = 128; // ZERO
1279 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1280 FLAT <op, (outs regClass:$data),
1281 (ins VReg_64:$addr),
1282 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1289 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1290 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1291 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1303 class MIMG_Mask <string op, int channels> {
1305 int Channels = channels;
1308 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1309 RegisterClass dst_rc,
1310 RegisterClass src_rc> : MIMG <
1312 (outs dst_rc:$vdata),
1313 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1314 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1316 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1317 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1322 let hasPostISelHook = 1;
1325 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1326 RegisterClass dst_rc,
1328 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1329 MIMG_Mask<asm#"_V1", channels>;
1330 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1331 MIMG_Mask<asm#"_V2", channels>;
1332 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1333 MIMG_Mask<asm#"_V4", channels>;
1336 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1337 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1338 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1339 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1340 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1343 class MIMG_Sampler_Helper <bits<7> op, string asm,
1344 RegisterClass dst_rc,
1345 RegisterClass src_rc> : MIMG <
1347 (outs dst_rc:$vdata),
1348 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1349 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1350 SReg_256:$srsrc, SReg_128:$ssamp),
1351 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1352 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1356 let hasPostISelHook = 1;
1359 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1360 RegisterClass dst_rc,
1362 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1363 MIMG_Mask<asm#"_V1", channels>;
1364 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1365 MIMG_Mask<asm#"_V2", channels>;
1366 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1367 MIMG_Mask<asm#"_V4", channels>;
1368 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1369 MIMG_Mask<asm#"_V8", channels>;
1370 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1371 MIMG_Mask<asm#"_V16", channels>;
1374 multiclass MIMG_Sampler <bits<7> op, string asm> {
1375 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1376 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1377 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1378 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1381 class MIMG_Gather_Helper <bits<7> op, string asm,
1382 RegisterClass dst_rc,
1383 RegisterClass src_rc> : MIMG <
1385 (outs dst_rc:$vdata),
1386 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1387 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1388 SReg_256:$srsrc, SReg_128:$ssamp),
1389 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1390 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1395 // DMASK was repurposed for GATHER4. 4 components are always
1396 // returned and DMASK works like a swizzle - it selects
1397 // the component to fetch. The only useful DMASK values are
1398 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1399 // (red,red,red,red) etc.) The ISA document doesn't mention
1401 // Therefore, disable all code which updates DMASK by setting these two:
1403 let hasPostISelHook = 0;
1406 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1407 RegisterClass dst_rc,
1409 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1410 MIMG_Mask<asm#"_V1", channels>;
1411 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1412 MIMG_Mask<asm#"_V2", channels>;
1413 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1414 MIMG_Mask<asm#"_V4", channels>;
1415 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1416 MIMG_Mask<asm#"_V8", channels>;
1417 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1418 MIMG_Mask<asm#"_V16", channels>;
1421 multiclass MIMG_Gather <bits<7> op, string asm> {
1422 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1423 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1424 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1425 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1428 //===----------------------------------------------------------------------===//
1429 // Vector instruction mappings
1430 //===----------------------------------------------------------------------===//
1432 // Maps an opcode in e32 form to its e64 equivalent
1433 def getVOPe64 : InstrMapping {
1434 let FilterClass = "VOP";
1435 let RowFields = ["OpName"];
1436 let ColFields = ["Size"];
1438 let ValueCols = [["8"]];
1441 // Maps an opcode in e64 form to its e32 equivalent
1442 def getVOPe32 : InstrMapping {
1443 let FilterClass = "VOP";
1444 let RowFields = ["OpName"];
1445 let ColFields = ["Size"];
1447 let ValueCols = [["4"]];
1450 // Maps an original opcode to its commuted version
1451 def getCommuteRev : InstrMapping {
1452 let FilterClass = "VOP2_REV";
1453 let RowFields = ["RevOp"];
1454 let ColFields = ["IsOrig"];
1456 let ValueCols = [["0"]];
1459 def getMaskedMIMGOp : InstrMapping {
1460 let FilterClass = "MIMG_Mask";
1461 let RowFields = ["Op"];
1462 let ColFields = ["Channels"];
1464 let ValueCols = [["1"], ["2"], ["3"] ];
1467 // Maps an commuted opcode to its original version
1468 def getCommuteOrig : InstrMapping {
1469 let FilterClass = "VOP2_REV";
1470 let RowFields = ["RevOp"];
1471 let ColFields = ["IsOrig"];
1473 let ValueCols = [["1"]];
1476 def isDS : InstrMapping {
1477 let FilterClass = "DS";
1478 let RowFields = ["Inst"];
1479 let ColFields = ["Size"];
1481 let ValueCols = [["8"]];
1484 def getMCOpcode : InstrMapping {
1485 let FilterClass = "SIMCInstr";
1486 let RowFields = ["PseudoInstr"];
1487 let ColFields = ["Subtarget"];
1488 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1489 let ValueCols = [[!cast<string>(SISubtarget.SI)]];
1492 def getAddr64Inst : InstrMapping {
1493 let FilterClass = "MUBUFAddr64Table";
1494 let RowFields = ["OpName"];
1495 let ColFields = ["IsAddr64"];
1497 let ValueCols = [["1"]];
1500 // Maps an atomic opcode to its version with a return value.
1501 def getAtomicRetOp : InstrMapping {
1502 let FilterClass = "AtomicNoRet";
1503 let RowFields = ["NoRetOp"];
1504 let ColFields = ["IsRet"];
1506 let ValueCols = [["1"]];
1509 // Maps an atomic opcode to its returnless version.
1510 def getAtomicNoRetOp : InstrMapping {
1511 let FilterClass = "AtomicNoRet";
1512 let RowFields = ["NoRetOp"];
1513 let ColFields = ["IsRet"];
1515 let ValueCols = [["0"]];
1518 include "SIInstructions.td"