1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
40 // that doesn't have VOP2 encoding on VI
41 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
45 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
50 class sop1 <bits<8> si, bits<8> vi = si> {
51 field bits<8> SI = si;
52 field bits<8> VI = vi;
55 class sop2 <bits<7> si, bits<7> vi = si> {
56 field bits<7> SI = si;
57 field bits<7> VI = vi;
60 class sopk <bits<5> si, bits<5> vi = si> {
61 field bits<5> SI = si;
62 field bits<5> VI = vi;
65 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66 // in AMDGPUInstrInfo.cpp
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79 [SDNPMayLoad, SDNPMemOperand]
82 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
84 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
85 SDTCisVT<1, iAny>, // vdata(VGPR)
86 SDTCisVT<2, i32>, // num_channels(imm)
87 SDTCisVT<3, i32>, // vaddr(VGPR)
88 SDTCisVT<4, i32>, // soffset(SGPR)
89 SDTCisVT<5, i32>, // inst_offset(imm)
90 SDTCisVT<6, i32>, // dfmt(imm)
91 SDTCisVT<7, i32>, // nfmt(imm)
92 SDTCisVT<8, i32>, // offen(imm)
93 SDTCisVT<9, i32>, // idxen(imm)
94 SDTCisVT<10, i32>, // glc(imm)
95 SDTCisVT<11, i32>, // slc(imm)
96 SDTCisVT<12, i32> // tfe(imm)
98 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
101 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
106 class SDSample<string opcode> : SDNode <opcode,
107 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
111 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
116 def SIconstdata_ptr : SDNode<
117 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
120 // Transformation function, extract the lower 32bit of a 64bit immediate
121 def LO32 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
125 def LO32f : SDNodeXForm<fpimm, [{
126 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
130 // Transformation function, extract the upper 32bit of a 64bit immediate
131 def HI32 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
135 def HI32f : SDNodeXForm<fpimm, [{
136 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
140 def IMM8bitDWORD : PatLeaf <(imm),
141 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
144 def as_dword_i32imm : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
148 def as_i1imm : SDNodeXForm<imm, [{
149 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
152 def as_i8imm : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
156 def as_i16imm : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
160 def as_i32imm: SDNodeXForm<imm, [{
161 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
164 def as_i64imm: SDNodeXForm<imm, [{
165 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
174 // Copied from the AArch64 backend:
175 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176 return CurDAG->getTargetConstant(
177 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
180 def IMM8bit : PatLeaf <(imm),
181 [{return isUInt<8>(N->getZExtValue());}]
184 def IMM12bit : PatLeaf <(imm),
185 [{return isUInt<12>(N->getZExtValue());}]
188 def IMM16bit : PatLeaf <(imm),
189 [{return isUInt<16>(N->getZExtValue());}]
192 def IMM20bit : PatLeaf <(imm),
193 [{return isUInt<20>(N->getZExtValue());}]
196 def IMM32bit : PatLeaf <(imm),
197 [{return isUInt<32>(N->getZExtValue());}]
200 def mubuf_vaddr_offset : PatFrag<
201 (ops node:$ptr, node:$offset, node:$imm_offset),
202 (add (add node:$ptr, node:$offset), node:$imm_offset)
205 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206 return isInlineImmediate(N);
209 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210 return isInlineImmediate(N);
213 class SGPRImm <dag frag> : PatLeaf<frag, [{
214 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
217 const SIRegisterInfo *SIRI =
218 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
219 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
221 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
228 //===----------------------------------------------------------------------===//
230 //===----------------------------------------------------------------------===//
232 def FRAMEri32 : Operand<iPTR> {
233 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
236 def sopp_brtarget : Operand<OtherVT> {
237 let EncoderMethod = "getSOPPBrEncoding";
238 let OperandType = "OPERAND_PCREL";
241 include "SIInstrFormats.td"
242 include "VIInstrFormats.td"
244 let OperandType = "OPERAND_IMMEDIATE" in {
246 def offen : Operand<i1> {
247 let PrintMethod = "printOffen";
249 def idxen : Operand<i1> {
250 let PrintMethod = "printIdxen";
252 def addr64 : Operand<i1> {
253 let PrintMethod = "printAddr64";
255 def mbuf_offset : Operand<i16> {
256 let PrintMethod = "printMBUFOffset";
258 def ds_offset : Operand<i16> {
259 let PrintMethod = "printDSOffset";
261 def ds_offset0 : Operand<i8> {
262 let PrintMethod = "printDSOffset0";
264 def ds_offset1 : Operand<i8> {
265 let PrintMethod = "printDSOffset1";
267 def glc : Operand <i1> {
268 let PrintMethod = "printGLC";
270 def slc : Operand <i1> {
271 let PrintMethod = "printSLC";
273 def tfe : Operand <i1> {
274 let PrintMethod = "printTFE";
277 def omod : Operand <i32> {
278 let PrintMethod = "printOModSI";
281 def ClampMod : Operand <i1> {
282 let PrintMethod = "printClampSI";
285 } // End OperandType = "OPERAND_IMMEDIATE"
287 //===----------------------------------------------------------------------===//
289 //===----------------------------------------------------------------------===//
291 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
292 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
294 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
295 def MUBUFAddr64 : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
296 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
297 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
298 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
299 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
301 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
302 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
303 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
304 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
306 //===----------------------------------------------------------------------===//
307 // SI assembler operands
308 //===----------------------------------------------------------------------===//
328 //===----------------------------------------------------------------------===//
330 // SI Instruction multiclass helpers.
332 // Instructions with _32 take 32-bit operands.
333 // Instructions with _64 take 64-bit operands.
335 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
336 // encoding is the standard encoding, but instruction that make use of
337 // any of the instruction modifiers must use the 64-bit encoding.
339 // Instructions with _e32 use the 32-bit encoding.
340 // Instructions with _e64 use the 64-bit encoding.
342 //===----------------------------------------------------------------------===//
344 class SIMCInstr <string pseudo, int subtarget> {
345 string PseudoInstr = pseudo;
346 int Subtarget = subtarget;
349 //===----------------------------------------------------------------------===//
351 //===----------------------------------------------------------------------===//
353 class EXPCommon : InstSI<
355 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
356 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
357 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
366 let isPseudo = 1 in {
367 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
370 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
372 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
375 //===----------------------------------------------------------------------===//
377 //===----------------------------------------------------------------------===//
379 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
380 SOP1 <outs, ins, "", pattern>,
381 SIMCInstr<opName, SISubtarget.NONE> {
385 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
386 SOP1 <outs, ins, asm, []>,
388 SIMCInstr<opName, SISubtarget.SI>;
390 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
391 SOP1 <outs, ins, asm, []>,
393 SIMCInstr<opName, SISubtarget.VI>;
395 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
398 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
400 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
402 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
406 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
407 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
408 opName#" $dst, $src0", pattern
411 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
412 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
413 opName#" $dst, $src0", pattern
416 // no input, 64-bit output.
417 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
418 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
420 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
425 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
431 // 64-bit input, 32-bit output.
432 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
433 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
434 opName#" $dst, $src0", pattern
437 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
438 SOP2<outs, ins, "", pattern>,
439 SIMCInstr<opName, SISubtarget.NONE> {
444 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
445 SOP2<outs, ins, asm, []>,
447 SIMCInstr<opName, SISubtarget.SI>;
449 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
450 SOP2<outs, ins, asm, []>,
452 SIMCInstr<opName, SISubtarget.VI>;
454 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
455 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
456 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
458 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
459 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
460 opName#" $dst, $src0, $src1 [$scc]">;
462 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
463 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
464 opName#" $dst, $src0, $src1 [$scc]">;
467 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
470 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
472 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
474 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
478 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
479 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
480 opName#" $dst, $src0, $src1", pattern
483 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
484 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
485 opName#" $dst, $src0, $src1", pattern
488 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
489 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
490 opName#" $dst, $src0, $src1", pattern
493 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
494 string opName, PatLeaf cond> : SOPC <
495 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
496 opName#" $dst, $src0, $src1", []>;
498 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
499 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
501 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
502 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
504 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
505 SOPK <outs, ins, "", pattern>,
506 SIMCInstr<opName, SISubtarget.NONE> {
510 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
511 SOPK <outs, ins, asm, []>,
513 SIMCInstr<opName, SISubtarget.SI>;
515 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
516 SOPK <outs, ins, asm, []>,
518 SIMCInstr<opName, SISubtarget.VI>;
520 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
521 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
524 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
525 opName#" $dst, $src0">;
527 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
528 opName#" $dst, $src0">;
531 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
532 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
533 (ins SReg_32:$src0, u16imm:$src1), pattern>;
535 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
536 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
538 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
539 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
542 //===----------------------------------------------------------------------===//
544 //===----------------------------------------------------------------------===//
546 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
547 SMRD <outs, ins, "", pattern>,
548 SIMCInstr<opName, SISubtarget.NONE> {
552 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
554 SMRD <outs, ins, asm, []>,
556 SIMCInstr<opName, SISubtarget.SI>;
558 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
560 SMRD <outs, ins, asm, []>,
562 SIMCInstr<opName, SISubtarget.VI>;
564 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
565 string asm, list<dag> pattern> {
567 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
569 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
571 // glc is only applicable to scalar stores, which are not yet
574 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
578 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
579 RegisterClass dstClass> {
581 op, opName#"_IMM", 1, (outs dstClass:$dst),
582 (ins baseClass:$sbase, u32imm:$offset),
583 opName#" $dst, $sbase, $offset", []
586 defm _SGPR : SMRD_m <
587 op, opName#"_SGPR", 0, (outs dstClass:$dst),
588 (ins baseClass:$sbase, SReg_32:$soff),
589 opName#" $dst, $sbase, $soff", []
593 //===----------------------------------------------------------------------===//
594 // Vector ALU classes
595 //===----------------------------------------------------------------------===//
597 // This must always be right before the operand being input modified.
598 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
599 let PrintMethod = "printOperandAndMods";
601 def InputModsNoDefault : Operand <i32> {
602 let PrintMethod = "printOperandAndMods";
605 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
607 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
608 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
612 // Returns the register class to use for the destination of VOP[123C]
613 // instructions for the given VT.
614 class getVALUDstForVT<ValueType VT> {
615 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32,
616 !if(!eq(VT.Size, 64), VReg_64,
617 SReg_64)); // else VT == i1
620 // Returns the register class to use for source 0 of VOP[12C]
621 // instructions for the given VT.
622 class getVOPSrc0ForVT<ValueType VT> {
623 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
626 // Returns the register class to use for source 1 of VOP[12C] for the
628 class getVOPSrc1ForVT<ValueType VT> {
629 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
632 // Returns the register class to use for sources of VOP3 instructions for the
634 class getVOP3SrcForVT<ValueType VT> {
635 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
638 // Returns 1 if the source arguments have modifiers, 0 if they do not.
639 class hasModifiers<ValueType SrcVT> {
640 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
641 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
644 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
645 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
646 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
647 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
651 // Returns the input arguments for VOP3 instructions for the given SrcVT.
652 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
653 RegisterOperand Src2RC, int NumSrcArgs,
657 !if (!eq(NumSrcArgs, 1),
658 !if (!eq(HasModifiers, 1),
659 // VOP1 with modifiers
660 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
661 ClampMod:$clamp, omod:$omod)
663 // VOP1 without modifiers
666 !if (!eq(NumSrcArgs, 2),
667 !if (!eq(HasModifiers, 1),
668 // VOP 2 with modifiers
669 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
670 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
671 ClampMod:$clamp, omod:$omod)
673 // VOP2 without modifiers
674 (ins Src0RC:$src0, Src1RC:$src1)
676 /* NumSrcArgs == 3 */,
677 !if (!eq(HasModifiers, 1),
678 // VOP3 with modifiers
679 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
680 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
681 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
682 ClampMod:$clamp, omod:$omod)
684 // VOP3 without modifiers
685 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
689 // Returns the assembly string for the inputs and outputs of a VOP[12C]
690 // instruction. This does not add the _e32 suffix, so it can be reused
692 class getAsm32 <int NumSrcArgs> {
693 string src1 = ", $src1";
694 string src2 = ", $src2";
695 string ret = " $dst, $src0"#
696 !if(!eq(NumSrcArgs, 1), "", src1)#
697 !if(!eq(NumSrcArgs, 3), src2, "");
700 // Returns the assembly string for the inputs and outputs of a VOP3
702 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
703 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
704 string src1 = !if(!eq(NumSrcArgs, 1), "",
705 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
706 " $src1_modifiers,"));
707 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
709 !if(!eq(HasModifiers, 0),
710 getAsm32<NumSrcArgs>.ret,
711 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
715 class VOPProfile <list<ValueType> _ArgVT> {
717 field list<ValueType> ArgVT = _ArgVT;
719 field ValueType DstVT = ArgVT[0];
720 field ValueType Src0VT = ArgVT[1];
721 field ValueType Src1VT = ArgVT[2];
722 field ValueType Src2VT = ArgVT[3];
723 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
724 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
725 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
726 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
727 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
728 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
730 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
731 field bit HasModifiers = hasModifiers<Src0VT>.ret;
733 field dag Outs = (outs DstRC:$dst);
735 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
736 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
739 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
740 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
743 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
744 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
745 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
746 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
747 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
748 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
749 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
750 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
751 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
753 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
754 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
755 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
756 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
757 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
758 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
759 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
760 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
761 let Src0RC32 = VCSrc_32;
764 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
765 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
766 let Asm64 = " $dst, $src0_modifiers, $src1";
769 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
770 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
771 let Asm64 = " $dst, $src0_modifiers, $src1";
774 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
775 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
776 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
778 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
779 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
780 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
781 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
784 class VOP <string opName> {
785 string OpName = opName;
788 class VOP2_REV <string revOp, bit isOrig> {
789 string RevOp = revOp;
793 class AtomicNoRet <string noRetOp, bit isRet> {
794 string NoRetOp = noRetOp;
798 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
799 VOP1Common <outs, ins, "", pattern>,
801 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
805 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
807 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
809 def _si : VOP1<op.SI, outs, ins, asm, []>,
810 SIMCInstr <opName#"_e32", SISubtarget.SI>;
811 def _vi : VOP1<op.VI, outs, ins, asm, []>,
812 SIMCInstr <opName#"_e32", SISubtarget.VI>;
815 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
817 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
819 def _si : VOP1<op.SI, outs, ins, asm, []>,
820 SIMCInstr <opName#"_e32", SISubtarget.SI>;
821 // No VI instruction. This class is for SI only.
824 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
825 VOP2Common <outs, ins, "", pattern>,
827 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
831 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
832 string opName, string revOp> {
833 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
834 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
836 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
837 SIMCInstr <opName#"_e32", SISubtarget.SI>;
840 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
841 string opName, string revOp> {
842 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
843 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
845 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
846 SIMCInstr <opName#"_e32", SISubtarget.SI>;
847 def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
848 SIMCInstr <opName#"_e32", SISubtarget.VI>;
851 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
853 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
854 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
855 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
856 bits<2> omod = !if(HasModifiers, ?, 0);
857 bits<1> clamp = !if(HasModifiers, ?, 0);
858 bits<9> src1 = !if(HasSrc1, ?, 0);
859 bits<9> src2 = !if(HasSrc2, ?, 0);
862 class VOP3DisableModFields <bit HasSrc0Mods,
865 bit HasOutputMods = 0> {
866 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
867 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
868 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
869 bits<2> omod = !if(HasOutputMods, ?, 0);
870 bits<1> clamp = !if(HasOutputMods, ?, 0);
873 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
874 VOP3Common <outs, ins, "", pattern>,
876 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
880 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
881 VOP3Common <outs, ins, asm, []>,
883 SIMCInstr<opName#"_e64", SISubtarget.SI>;
885 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
886 VOP3Common <outs, ins, asm, []>,
888 SIMCInstr <opName#"_e64", SISubtarget.VI>;
890 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
891 VOP3Common <outs, ins, asm, []>,
893 SIMCInstr<opName#"_e64", SISubtarget.SI>;
895 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
896 VOP3Common <outs, ins, asm, []>,
898 SIMCInstr <opName#"_e64", SISubtarget.VI>;
900 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
901 string opName, int NumSrcArgs, bit HasMods = 1> {
903 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
905 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
906 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
907 !if(!eq(NumSrcArgs, 2), 0, 1),
909 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
910 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
911 !if(!eq(NumSrcArgs, 2), 0, 1),
915 // VOP3_m without source modifiers
916 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
917 string opName, int NumSrcArgs, bit HasMods = 1> {
919 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
921 let src0_modifiers = 0,
926 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
927 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
931 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
932 list<dag> pattern, string opName, bit HasMods = 1> {
934 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
936 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
937 VOP3DisableFields<0, 0, HasMods>;
939 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
940 VOP3DisableFields<0, 0, HasMods>;
943 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
944 list<dag> pattern, string opName, bit HasMods = 1> {
946 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
948 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
949 VOP3DisableFields<0, 0, HasMods>;
950 // No VI instruction. This class is for SI only.
953 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
954 list<dag> pattern, string opName, string revOp,
955 bit HasMods = 1, bit UseFullOp = 0> {
957 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
958 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
960 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
961 VOP3DisableFields<1, 0, HasMods>;
963 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
964 VOP3DisableFields<1, 0, HasMods>;
967 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
968 list<dag> pattern, string opName, string revOp,
969 bit HasMods = 1, bit UseFullOp = 0> {
971 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
972 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
974 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
975 VOP3DisableFields<1, 0, HasMods>;
977 // No VI instruction. This class is for SI only.
980 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
981 // option of implicit vcc use?
982 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
983 list<dag> pattern, string opName, string revOp,
984 bit HasMods = 1, bit UseFullOp = 0> {
985 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
986 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
988 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
989 // can write it into any SGPR. We currently don't use the carry out,
990 // so for now hardcode it to VCC as well.
991 let sdst = SIOperand.VCC, Defs = [VCC] in {
992 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
993 VOP3DisableFields<1, 0, HasMods>;
995 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
996 VOP3DisableFields<1, 0, HasMods>;
997 } // End sdst = SIOperand.VCC, Defs = [VCC]
1000 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1001 list<dag> pattern, string opName, string revOp,
1002 bit HasMods = 1, bit UseFullOp = 0> {
1003 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1006 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1007 VOP3DisableFields<1, 1, HasMods>;
1009 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1010 VOP3DisableFields<1, 1, HasMods>;
1013 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1014 list<dag> pattern, string opName,
1015 bit HasMods, bit defExec> {
1017 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1019 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1020 VOP3DisableFields<1, 0, HasMods> {
1021 let Defs = !if(defExec, [EXEC], []);
1024 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1025 VOP3DisableFields<1, 0, HasMods> {
1026 let Defs = !if(defExec, [EXEC], []);
1030 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1031 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1032 string asm, list<dag> pattern = []> {
1033 let isPseudo = 1 in {
1034 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1035 SIMCInstr<opName, SISubtarget.NONE>;
1038 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1039 SIMCInstr <opName, SISubtarget.SI>;
1041 def _vi : VOP3Common <outs, ins, asm, []>,
1043 VOP3DisableFields <1, 0, 0>,
1044 SIMCInstr <opName, SISubtarget.VI>;
1047 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1048 dag ins32, string asm32, list<dag> pat32,
1049 dag ins64, string asm64, list<dag> pat64,
1052 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1054 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
1057 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1058 SDPatternOperator node = null_frag> : VOP1_Helper <
1060 P.Ins32, P.Asm32, [],
1063 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1064 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1065 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1069 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1070 SDPatternOperator node = null_frag> {
1072 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1074 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1076 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1077 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1078 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1079 opName, P.HasModifiers>;
1082 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1083 dag ins32, string asm32, list<dag> pat32,
1084 dag ins64, string asm64, list<dag> pat64,
1085 string revOp, bit HasMods> {
1086 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1088 defm _e64 : VOP3_2_m <op,
1089 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1093 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1094 SDPatternOperator node = null_frag,
1095 string revOp = opName> : VOP2_Helper <
1097 P.Ins32, P.Asm32, [],
1101 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1102 i1:$clamp, i32:$omod)),
1103 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1104 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1105 revOp, P.HasModifiers
1108 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1109 SDPatternOperator node = null_frag,
1110 string revOp = opName> {
1111 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1113 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#"_e64"#P.Asm64,
1116 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1117 i1:$clamp, i32:$omod)),
1118 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1119 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1120 opName, revOp, P.HasModifiers>;
1123 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1124 dag ins32, string asm32, list<dag> pat32,
1125 dag ins64, string asm64, list<dag> pat64,
1126 string revOp, bit HasMods> {
1128 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1130 defm _e64 : VOP3b_2_m <op,
1131 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1135 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1136 SDPatternOperator node = null_frag,
1137 string revOp = opName> : VOP2b_Helper <
1139 P.Ins32, P.Asm32, [],
1143 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1144 i1:$clamp, i32:$omod)),
1145 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1146 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1147 revOp, P.HasModifiers
1150 // A VOP2 instruction that is VOP3-only on VI.
1151 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1152 dag ins32, string asm32, list<dag> pat32,
1153 dag ins64, string asm64, list<dag> pat64,
1154 string revOp, bit HasMods> {
1155 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1157 defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
1161 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1162 SDPatternOperator node = null_frag,
1163 string revOp = opName>
1166 P.Ins32, P.Asm32, [],
1170 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1171 i1:$clamp, i32:$omod)),
1172 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1173 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1174 revOp, P.HasModifiers
1177 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1178 VOPCCommon <ins, "", pattern>,
1180 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1184 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1185 string opName, bit DefExec> {
1186 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1188 def _si : VOPC<op.SI, ins, asm, []>,
1189 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1190 let Defs = !if(DefExec, [EXEC], []);
1193 def _vi : VOPC<op.VI, ins, asm, []>,
1194 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1195 let Defs = !if(DefExec, [EXEC], []);
1199 multiclass VOPC_Helper <vopc op, string opName,
1200 dag ins32, string asm32, list<dag> pat32,
1201 dag out64, dag ins64, string asm64, list<dag> pat64,
1202 bit HasMods, bit DefExec> {
1203 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1205 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1206 opName, HasMods, DefExec>;
1209 // Special case for class instructions which only have modifiers on
1210 // the 1st source operand.
1211 multiclass VOPC_Class_Helper <vopc op, string opName,
1212 dag ins32, string asm32, list<dag> pat32,
1213 dag out64, dag ins64, string asm64, list<dag> pat64,
1214 bit HasMods, bit DefExec> {
1215 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1217 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1218 opName, HasMods, DefExec>,
1219 VOP3DisableModFields<1, 0, 0>;
1222 multiclass VOPCInst <vopc op, string opName,
1223 VOPProfile P, PatLeaf cond = COND_NULL,
1224 bit DefExec = 0> : VOPC_Helper <
1226 P.Ins32, P.Asm32, [],
1227 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1230 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1231 i1:$clamp, i32:$omod)),
1232 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1234 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1235 P.HasModifiers, DefExec
1238 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1239 bit DefExec = 0> : VOPC_Class_Helper <
1241 P.Ins32, P.Asm32, [],
1242 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1245 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1246 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1247 P.HasModifiers, DefExec
1251 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1252 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1254 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1255 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1257 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1258 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1260 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1261 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1264 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1265 PatLeaf cond = COND_NULL>
1266 : VOPCInst <op, opName, P, cond, 1>;
1268 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1269 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1271 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1272 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1274 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1275 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1277 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1278 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1280 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1281 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1282 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
1285 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1286 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1288 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1289 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1291 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1292 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1294 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1295 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1297 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1298 SDPatternOperator node = null_frag> : VOP3_Helper <
1299 op, opName, P.Outs, P.Ins64, P.Asm64,
1300 !if(!eq(P.NumSrcArgs, 3),
1303 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1304 i1:$clamp, i32:$omod)),
1305 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1306 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1307 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1309 !if(!eq(P.NumSrcArgs, 2),
1312 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1313 i1:$clamp, i32:$omod)),
1314 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1315 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1316 /* P.NumSrcArgs == 1 */,
1319 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1320 i1:$clamp, i32:$omod))))],
1321 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1322 P.NumSrcArgs, P.HasModifiers
1325 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1326 // only VOP instruction that implicitly reads VCC.
1327 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1329 SDPatternOperator node = null_frag> : VOP3_Helper <
1332 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1333 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1334 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1337 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1339 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1340 i1:$clamp, i32:$omod)),
1341 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1342 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1347 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1348 string opName, list<dag> pattern> :
1350 op, (outs vrc:$vdst, SReg_64:$sdst),
1351 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1352 InputModsNoDefault:$src1_modifiers, arc:$src1,
1353 InputModsNoDefault:$src2_modifiers, arc:$src2,
1354 ClampMod:$clamp, omod:$omod),
1355 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1356 opName, opName, 1, 1
1359 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1360 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1362 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1363 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1366 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1367 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1368 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1369 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1370 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1371 i32:$src1_modifiers, P.Src1VT:$src1,
1372 i32:$src2_modifiers, P.Src2VT:$src2,
1376 //===----------------------------------------------------------------------===//
1377 // Interpolation opcodes
1378 //===----------------------------------------------------------------------===//
1380 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1381 VINTRPCommon <outs, ins, "", pattern>,
1382 SIMCInstr<opName, SISubtarget.NONE> {
1386 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1388 VINTRPCommon <outs, ins, asm, []>,
1390 SIMCInstr<opName, SISubtarget.SI>;
1392 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1394 VINTRPCommon <outs, ins, asm, []>,
1396 SIMCInstr<opName, SISubtarget.VI>;
1398 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1399 string disableEncoding = "", string constraints = "",
1400 list<dag> pattern = []> {
1401 let DisableEncoding = disableEncoding,
1402 Constraints = constraints in {
1403 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1405 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1407 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1411 //===----------------------------------------------------------------------===//
1412 // Vector I/O classes
1413 //===----------------------------------------------------------------------===//
1415 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1416 DS <outs, ins, "", pattern>,
1417 SIMCInstr <opName, SISubtarget.NONE> {
1421 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1422 DS <outs, ins, asm, []>,
1424 SIMCInstr <opName, SISubtarget.SI>;
1426 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1427 DS <outs, ins, asm, []>,
1429 SIMCInstr <opName, SISubtarget.VI>;
1431 class DS_1A_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1432 DS <outs, ins, asm, []>,
1434 SIMCInstr <opName, SISubtarget.SI> {
1436 // Single load interpret the 2 i8imm operands as a single i16 offset.
1438 let offset0 = offset{7-0};
1439 let offset1 = offset{15-8};
1442 class DS_1A_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1443 DS <outs, ins, asm, []>,
1445 SIMCInstr <opName, SISubtarget.VI> {
1447 // Single load interpret the 2 i8imm operands as a single i16 offset.
1449 let offset0 = offset{7-0};
1450 let offset1 = offset{15-8};
1453 multiclass DS_1A_Load_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1455 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1456 def "" : DS_Pseudo <opName, outs, ins, pat>;
1458 let data0 = 0, data1 = 0 in {
1459 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1460 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1465 multiclass DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass>
1469 (outs regClass:$vdst),
1470 (ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1471 asm#" $vdst, $addr"#"$offset"#" [M0]",
1474 multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1476 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1477 def "" : DS_Pseudo <opName, outs, ins, pat>;
1479 let data0 = 0, data1 = 0 in {
1480 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1481 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1486 multiclass DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass>
1490 (outs regClass:$vdst),
1491 (ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1493 asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
1496 multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
1497 string asm, list<dag> pat> {
1498 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1499 def "" : DS_Pseudo <opName, outs, ins, pat>;
1501 let data1 = 0, vdst = 0 in {
1502 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1503 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1508 multiclass DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass>
1513 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
1514 asm#" $addr, $data0"#"$offset"#" [M0]",
1517 multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
1518 string asm, list<dag> pat> {
1519 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1520 def "" : DS_Pseudo <opName, outs, ins, pat>;
1523 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1524 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1529 multiclass DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass>
1534 (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, regClass:$data1,
1535 ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
1536 asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
1539 // 1 address, 1 data.
1540 multiclass DS_1A1D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1541 string asm, list<dag> pat, string noRetOp> {
1542 let mayLoad = 1, mayStore = 1,
1543 hasPostISelHook = 1 // Adjusted to no return version.
1545 def "" : DS_Pseudo <opName, outs, ins, pat>,
1546 AtomicNoRet<noRetOp, 1>;
1549 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1550 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1555 multiclass DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc,
1556 string noRetOp = ""> : DS_1A1D_RET_m <
1559 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1560 asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", [], noRetOp>;
1562 // 1 address, 2 data.
1563 multiclass DS_1A2D_RET_m <bits<8> op, string opName, dag outs, dag ins,
1564 string asm, list<dag> pat, string noRetOp> {
1565 let mayLoad = 1, mayStore = 1,
1566 hasPostISelHook = 1 // Adjusted to no return version.
1568 def "" : DS_Pseudo <opName, outs, ins, pat>,
1569 AtomicNoRet<noRetOp, 1>;
1571 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1572 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1576 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1577 string noRetOp = ""> : DS_1A2D_RET_m <
1580 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1581 asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1584 // 1 address, 2 data.
1585 multiclass DS_1A2D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1586 string asm, list<dag> pat, string noRetOp> {
1587 let mayLoad = 1, mayStore = 1 in {
1588 def "" : DS_Pseudo <opName, outs, ins, pat>,
1589 AtomicNoRet<noRetOp, 0>;
1592 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1593 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1598 multiclass DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc,
1599 string noRetOp = asm> : DS_1A2D_NORET_m <
1602 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1603 asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1606 // 1 address, 1 data.
1607 multiclass DS_1A1D_NORET_m <bits<8> op, string opName, dag outs, dag ins,
1608 string asm, list<dag> pat, string noRetOp> {
1609 let mayLoad = 1, mayStore = 1 in {
1610 def "" : DS_Pseudo <opName, outs, ins, pat>,
1611 AtomicNoRet<noRetOp, 0>;
1613 let data1 = 0, vdst = 0 in {
1614 def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1615 def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1620 multiclass DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc,
1621 string noRetOp = asm> : DS_1A1D_NORET_m <
1624 (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1625 asm#" $addr, $data0"#"$offset"#" [M0]",
1628 //===----------------------------------------------------------------------===//
1630 //===----------------------------------------------------------------------===//
1632 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1633 MTBUF <outs, ins, "", pattern>,
1634 SIMCInstr<opName, SISubtarget.NONE> {
1638 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1640 MTBUF <outs, ins, asm, []>,
1642 SIMCInstr<opName, SISubtarget.SI>;
1644 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1645 MTBUF <outs, ins, asm, []>,
1647 SIMCInstr <opName, SISubtarget.VI>;
1649 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1650 list<dag> pattern> {
1652 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1654 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1656 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1660 let mayStore = 1, mayLoad = 0 in {
1662 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1663 RegisterClass regClass> : MTBUF_m <
1665 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1666 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1667 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1668 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1669 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1672 } // mayStore = 1, mayLoad = 0
1674 let mayLoad = 1, mayStore = 0 in {
1676 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1677 RegisterClass regClass> : MTBUF_m <
1678 op, opName, (outs regClass:$dst),
1679 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1680 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1681 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1682 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1683 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1686 } // mayLoad = 1, mayStore = 0
1688 //===----------------------------------------------------------------------===//
1690 //===----------------------------------------------------------------------===//
1692 class mubuf <bits<7> si, bits<7> vi = si> {
1693 field bits<7> SI = si;
1694 field bits<7> VI = vi;
1697 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1698 bit IsAddr64 = is_addr64;
1699 string OpName = NAME # suffix;
1702 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1703 MUBUF <outs, ins, "", pattern>,
1704 SIMCInstr<opName, SISubtarget.NONE> {
1707 // dummy fields, so that we can use let statements around multiclasses
1717 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1719 MUBUF <outs, ins, asm, []>,
1721 SIMCInstr<opName, SISubtarget.SI> {
1725 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
1727 MUBUF <outs, ins, asm, []>,
1729 SIMCInstr<opName, SISubtarget.VI> {
1733 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
1734 list<dag> pattern> {
1736 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1737 MUBUFAddr64Table <0>;
1740 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1743 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1746 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
1747 dag ins, string asm, list<dag> pattern> {
1749 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1750 MUBUFAddr64Table <1>;
1753 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1756 // There is no VI version. If the pseudo is selected, it should be lowered
1757 // for VI appropriately.
1760 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1761 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1765 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
1766 string asm, list<dag> pattern, bit is_return> {
1768 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1769 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
1770 AtomicNoRet<NAME#"_OFFSET", is_return>;
1772 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
1774 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1777 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1781 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
1782 string asm, list<dag> pattern, bit is_return> {
1784 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1785 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
1786 AtomicNoRet<NAME#"_ADDR64", is_return>;
1788 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
1789 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1792 // There is no VI version. If the pseudo is selected, it should be lowered
1793 // for VI appropriately.
1796 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
1797 ValueType vt, SDPatternOperator atomic> {
1799 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1801 // No return variants
1804 defm _ADDR64 : MUBUFAtomicAddr64_m <
1805 op, name#"_addr64", (outs),
1806 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1807 mbuf_offset:$offset, SCSrc_32:$soffset, slc:$slc),
1808 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
1811 defm _OFFSET : MUBUFAtomicOffset_m <
1812 op, name#"_offset", (outs),
1813 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1814 SCSrc_32:$soffset, slc:$slc),
1815 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
1819 // Variant that return values
1820 let glc = 1, Constraints = "$vdata = $vdata_in",
1821 DisableEncoding = "$vdata_in" in {
1823 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
1824 op, name#"_rtn_addr64", (outs rc:$vdata),
1825 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1826 mbuf_offset:$offset, SSrc_32:$soffset, slc:$slc),
1827 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
1829 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
1830 i16:$offset, i1:$slc), vt:$vdata_in))], 1
1833 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
1834 op, name#"_rtn_offset", (outs rc:$vdata),
1835 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1836 SCSrc_32:$soffset, slc:$slc),
1837 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1839 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1840 i1:$slc), vt:$vdata_in))], 1
1845 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1848 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
1849 ValueType load_vt = i32,
1850 SDPatternOperator ld = null_frag> {
1852 let mayLoad = 1, mayStore = 0 in {
1853 let offen = 0, idxen = 0, vaddr = 0 in {
1854 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
1855 (ins SReg_128:$srsrc,
1856 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1857 slc:$slc, tfe:$tfe),
1858 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1859 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1860 i32:$soffset, i16:$offset,
1861 i1:$glc, i1:$slc, i1:$tfe)))]>;
1864 let offen = 1, idxen = 0 in {
1865 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
1866 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1867 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1869 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1872 let offen = 0, idxen = 1 in {
1873 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
1874 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1875 mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1876 slc:$slc, tfe:$tfe),
1877 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1880 let offen = 1, idxen = 1 in {
1881 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
1882 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1883 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1884 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1887 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
1888 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
1889 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1890 SCSrc_32:$soffset, mbuf_offset:$offset),
1891 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
1892 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1893 i64:$vaddr, i32:$soffset,
1899 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
1900 ValueType store_vt, SDPatternOperator st> {
1901 let mayLoad = 0, mayStore = 1 in {
1902 defm : MUBUF_m <op, name, (outs),
1903 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1904 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1906 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1907 "$glc"#"$slc"#"$tfe", []>;
1909 let offen = 0, idxen = 0, vaddr = 0 in {
1910 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
1911 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1912 SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1913 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1914 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1915 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
1916 } // offen = 0, idxen = 0, vaddr = 0
1918 let offen = 1, idxen = 0 in {
1919 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
1920 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1921 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1922 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1923 "$glc"#"$slc"#"$tfe", []>;
1924 } // end offen = 1, idxen = 0
1926 let offen = 0, idxen = 0, glc = 0, slc = 0, tfe = 0 in {
1927 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
1928 (ins vdataClass:$vdata, SReg_128:$srsrc,
1929 VReg_64:$vaddr, SCSrc_32:$soffset,
1930 mbuf_offset:$offset),
1931 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset",
1932 [(st store_vt:$vdata,
1933 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
1934 i32:$soffset, i16:$offset))]>;
1936 } // End mayLoad = 0, mayStore = 1
1939 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1940 FLAT <op, (outs regClass:$vdst),
1941 (ins VReg_64:$addr),
1942 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
1950 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1951 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1952 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1965 class MIMG_Mask <string op, int channels> {
1967 int Channels = channels;
1970 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1971 RegisterClass dst_rc,
1972 RegisterClass src_rc> : MIMG <
1974 (outs dst_rc:$vdata),
1975 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1976 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1978 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1979 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1984 let hasPostISelHook = 1;
1987 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1988 RegisterClass dst_rc,
1990 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
1991 MIMG_Mask<asm#"_V1", channels>;
1992 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1993 MIMG_Mask<asm#"_V2", channels>;
1994 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1995 MIMG_Mask<asm#"_V4", channels>;
1998 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1999 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2000 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2001 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2002 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2005 class MIMG_Sampler_Helper <bits<7> op, string asm,
2006 RegisterClass dst_rc,
2007 RegisterClass src_rc, int wqm> : MIMG <
2009 (outs dst_rc:$vdata),
2010 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2011 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2012 SReg_256:$srsrc, SReg_128:$ssamp),
2013 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2014 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2018 let hasPostISelHook = 1;
2022 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2023 RegisterClass dst_rc,
2024 int channels, int wqm> {
2025 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2026 MIMG_Mask<asm#"_V1", channels>;
2027 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2028 MIMG_Mask<asm#"_V2", channels>;
2029 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2030 MIMG_Mask<asm#"_V4", channels>;
2031 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2032 MIMG_Mask<asm#"_V8", channels>;
2033 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2034 MIMG_Mask<asm#"_V16", channels>;
2037 multiclass MIMG_Sampler <bits<7> op, string asm> {
2038 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2039 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2040 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2041 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2044 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2045 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2046 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2047 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2048 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2051 class MIMG_Gather_Helper <bits<7> op, string asm,
2052 RegisterClass dst_rc,
2053 RegisterClass src_rc, int wqm> : MIMG <
2055 (outs dst_rc:$vdata),
2056 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2057 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2058 SReg_256:$srsrc, SReg_128:$ssamp),
2059 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2060 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2065 // DMASK was repurposed for GATHER4. 4 components are always
2066 // returned and DMASK works like a swizzle - it selects
2067 // the component to fetch. The only useful DMASK values are
2068 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2069 // (red,red,red,red) etc.) The ISA document doesn't mention
2071 // Therefore, disable all code which updates DMASK by setting these two:
2073 let hasPostISelHook = 0;
2077 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2078 RegisterClass dst_rc,
2079 int channels, int wqm> {
2080 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2081 MIMG_Mask<asm#"_V1", channels>;
2082 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2083 MIMG_Mask<asm#"_V2", channels>;
2084 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2085 MIMG_Mask<asm#"_V4", channels>;
2086 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2087 MIMG_Mask<asm#"_V8", channels>;
2088 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2089 MIMG_Mask<asm#"_V16", channels>;
2092 multiclass MIMG_Gather <bits<7> op, string asm> {
2093 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2094 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2095 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2096 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2099 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2100 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2101 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2102 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2103 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2106 //===----------------------------------------------------------------------===//
2107 // Vector instruction mappings
2108 //===----------------------------------------------------------------------===//
2110 // Maps an opcode in e32 form to its e64 equivalent
2111 def getVOPe64 : InstrMapping {
2112 let FilterClass = "VOP";
2113 let RowFields = ["OpName"];
2114 let ColFields = ["Size"];
2116 let ValueCols = [["8"]];
2119 // Maps an opcode in e64 form to its e32 equivalent
2120 def getVOPe32 : InstrMapping {
2121 let FilterClass = "VOP";
2122 let RowFields = ["OpName"];
2123 let ColFields = ["Size"];
2125 let ValueCols = [["4"]];
2128 // Maps an original opcode to its commuted version
2129 def getCommuteRev : InstrMapping {
2130 let FilterClass = "VOP2_REV";
2131 let RowFields = ["RevOp"];
2132 let ColFields = ["IsOrig"];
2134 let ValueCols = [["0"]];
2137 def getMaskedMIMGOp : InstrMapping {
2138 let FilterClass = "MIMG_Mask";
2139 let RowFields = ["Op"];
2140 let ColFields = ["Channels"];
2142 let ValueCols = [["1"], ["2"], ["3"] ];
2145 // Maps an commuted opcode to its original version
2146 def getCommuteOrig : InstrMapping {
2147 let FilterClass = "VOP2_REV";
2148 let RowFields = ["RevOp"];
2149 let ColFields = ["IsOrig"];
2151 let ValueCols = [["1"]];
2154 def getMCOpcodeGen : InstrMapping {
2155 let FilterClass = "SIMCInstr";
2156 let RowFields = ["PseudoInstr"];
2157 let ColFields = ["Subtarget"];
2158 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2159 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2162 def getAddr64Inst : InstrMapping {
2163 let FilterClass = "MUBUFAddr64Table";
2164 let RowFields = ["OpName"];
2165 let ColFields = ["IsAddr64"];
2167 let ValueCols = [["1"]];
2170 // Maps an atomic opcode to its version with a return value.
2171 def getAtomicRetOp : InstrMapping {
2172 let FilterClass = "AtomicNoRet";
2173 let RowFields = ["NoRetOp"];
2174 let ColFields = ["IsRet"];
2176 let ValueCols = [["1"]];
2179 // Maps an atomic opcode to its returnless version.
2180 def getAtomicNoRetOp : InstrMapping {
2181 let FilterClass = "AtomicNoRet";
2182 let RowFields = ["NoRetOp"];
2183 let ColFields = ["IsRet"];
2185 let ValueCols = [["0"]];
2188 include "SIInstructions.td"
2189 include "CIInstructions.td"
2190 include "VIInstructions.td"