1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 // SMRD takes a 64bit memory address and can only add an 32bit offset
15 def SIadd64bit32bit : SDNode<"ISD::ADD",
16 SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVT<0, i64>, SDTCisVT<2, i32>]>
19 // Transformation function, extract the lower 32bit of a 64bit immediate
20 def LO32 : SDNodeXForm<imm, [{
21 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
24 // Transformation function, extract the upper 32bit of a 64bit immediate
25 def HI32 : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
29 def IMM8bitDWORD : ImmLeaf <
31 return (Imm & ~0x3FC) == 0;
32 }], SDNodeXForm<imm, [{
33 return CurDAG->getTargetConstant(
34 N->getZExtValue() >> 2, MVT::i32);
38 def IMM12bit : ImmLeaf <
40 [{return isUInt<12>(Imm);}]
43 class InlineImm <ValueType vt> : ImmLeaf <vt, [{
44 return -16 <= Imm && Imm <= 64;
48 //===----------------------------------------------------------------------===//
49 // SI assembler operands
50 //===----------------------------------------------------------------------===//
52 class SIOperand <ValueType vt, dag opInfo>: Operand <vt> {
53 let EncoderMethod = "encodeOperand";
54 let MIOperandInfo = opInfo;
57 class GPR4Align <RegisterClass rc> : Operand <vAny> {
58 let EncoderMethod = "GPR4AlignEncode";
59 let MIOperandInfo = (ops rc:$reg);
62 class GPR2Align <RegisterClass rc> : Operand <iPTR> {
63 let EncoderMethod = "GPR2AlignEncode";
64 let MIOperandInfo = (ops rc:$reg);
67 include "SIInstrFormats.td"
69 //===----------------------------------------------------------------------===//
71 // SI Instruction multiclass helpers.
73 // Instructions with _32 take 32-bit operands.
74 // Instructions with _64 take 64-bit operands.
76 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
77 // encoding is the standard encoding, but instruction that make use of
78 // any of the instruction modifiers must use the 64-bit encoding.
80 // Instructions with _e32 use the 32-bit encoding.
81 // Instructions with _e64 use the 64-bit encoding.
83 //===----------------------------------------------------------------------===//
85 //===----------------------------------------------------------------------===//
87 //===----------------------------------------------------------------------===//
89 class SOP1_32 <bits<8> op, string opName, list<dag> pattern>
90 : SOP1 <op, (outs SReg_32:$dst), (ins SSrc_32:$src0), opName, pattern>;
92 class SOP1_64 <bits<8> op, string opName, list<dag> pattern>
93 : SOP1 <op, (outs SReg_64:$dst), (ins SSrc_64:$src0), opName, pattern>;
95 class SOP2_32 <bits<7> op, string opName, list<dag> pattern>
96 : SOP2 <op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1), opName, pattern>;
98 class SOP2_64 <bits<7> op, string opName, list<dag> pattern>
99 : SOP2 <op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1), opName, pattern>;
101 class SOPC_32 <bits<7> op, string opName, list<dag> pattern>
102 : SOPC <op, (outs SCCReg:$dst), (ins SSrc_32:$src0, SSrc_32:$src1), opName, pattern>;
104 class SOPC_64 <bits<7> op, string opName, list<dag> pattern>
105 : SOPC <op, (outs SCCReg:$dst), (ins SSrc_64:$src0, SSrc_64:$src1), opName, pattern>;
107 class SOPK_32 <bits<5> op, string opName, list<dag> pattern>
108 : SOPK <op, (outs SReg_32:$dst), (ins i16imm:$src0), opName, pattern>;
110 class SOPK_64 <bits<5> op, string opName, list<dag> pattern>
111 : SOPK <op, (outs SReg_64:$dst), (ins i16imm:$src0), opName, pattern>;
113 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> {
115 op, 1, (outs dstClass:$dst),
116 (ins GPR2Align<SReg_64>:$sbase, i32imm:$offset),
121 op, 0, (outs dstClass:$dst),
122 (ins GPR2Align<SReg_64>:$sbase, SReg_32:$soff),
127 //===----------------------------------------------------------------------===//
128 // Vector ALU classes
129 //===----------------------------------------------------------------------===//
131 class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
132 op, (outs VReg_32:$dst),
133 (ins VSrc_32:$src0, VReg_32:$src1, VReg_32:$src2, i32imm:$src3,
134 i32imm:$src4, i32imm:$src5, i32imm:$src6),
138 class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
139 op, (outs VReg_64:$dst),
140 (ins VSrc_64:$src0, VReg_64:$src1, VReg_64:$src2,
141 i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6),
145 class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
146 string opName, list<dag> pattern> :
148 op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
151 multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> {
152 def _e32: VOP1_Helper <op, VReg_32, VSrc_32, opName, pattern>;
153 def _e64 : VOP3_32 <{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
158 multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern> {
160 def _e32 : VOP1_Helper <op, VReg_64, VSrc_64, opName, pattern>;
163 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
168 class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
169 string opName, list<dag> pattern> :
171 op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
174 multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> {
176 def _e32 : VOP2_Helper <op, VReg_32, VSrc_32, opName, pattern>;
178 def _e64 : VOP3_32 <{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
183 multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern> {
184 def _e32: VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>;
187 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
192 multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
193 string opName, list<dag> pattern> {
195 def _e32 : VOPC <op, (ins arc:$src0, vrc:$src1), opName, pattern>;
197 {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
199 (ins arc:$src0, vrc:$src1,
200 InstFlag:$abs, InstFlag:$clamp,
201 InstFlag:$omod, InstFlag:$neg),
208 multiclass VOPC_32 <bits<8> op, string opName, list<dag> pattern>
209 : VOPC_Helper <op, VReg_32, VSrc_32, opName, pattern>;
211 multiclass VOPC_64 <bits<8> op, string opName, list<dag> pattern>
212 : VOPC_Helper <op, VReg_64, VSrc_64, opName, pattern>;
214 //===----------------------------------------------------------------------===//
215 // Vector I/O classes
216 //===----------------------------------------------------------------------===//
218 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
221 (ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
222 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
223 GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
230 class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
232 (outs regClass:$dst),
233 (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
234 i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
235 i1imm:$tfe, SSrc_32:$soffset),
242 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
244 (outs regClass:$dst),
245 (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
246 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc,
247 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
254 class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
256 (outs VReg_128:$vdata),
257 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
258 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_32:$vaddr,
259 GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
266 include "SIInstructions.td"