1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
11 // in AMDGPUMCInstLower.h
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
22 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
23 [SDNPMayLoad, SDNPMemOperand]
26 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
28 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
29 SDTCisVT<1, iAny>, // vdata(VGPR)
30 SDTCisVT<2, i32>, // num_channels(imm)
31 SDTCisVT<3, i32>, // vaddr(VGPR)
32 SDTCisVT<4, i32>, // soffset(SGPR)
33 SDTCisVT<5, i32>, // inst_offset(imm)
34 SDTCisVT<6, i32>, // dfmt(imm)
35 SDTCisVT<7, i32>, // nfmt(imm)
36 SDTCisVT<8, i32>, // offen(imm)
37 SDTCisVT<9, i32>, // idxen(imm)
38 SDTCisVT<10, i32>, // glc(imm)
39 SDTCisVT<11, i32>, // slc(imm)
40 SDTCisVT<12, i32> // tfe(imm)
42 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
45 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
46 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
50 class SDSample<string opcode> : SDNode <opcode,
51 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
52 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
55 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
56 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
57 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
58 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
60 def SIconstdata_ptr : SDNode<
61 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
64 // Transformation function, extract the lower 32bit of a 64bit immediate
65 def LO32 : SDNodeXForm<imm, [{
66 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
69 def LO32f : SDNodeXForm<fpimm, [{
70 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
71 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
74 // Transformation function, extract the upper 32bit of a 64bit immediate
75 def HI32 : SDNodeXForm<imm, [{
76 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
79 def HI32f : SDNodeXForm<fpimm, [{
80 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
81 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
84 def IMM8bitDWORD : PatLeaf <(imm),
85 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
88 def as_dword_i32imm : SDNodeXForm<imm, [{
89 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
92 def as_i1imm : SDNodeXForm<imm, [{
93 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
96 def as_i8imm : SDNodeXForm<imm, [{
97 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
100 def as_i16imm : SDNodeXForm<imm, [{
101 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
104 def as_i32imm: SDNodeXForm<imm, [{
105 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
108 def IMM8bit : PatLeaf <(imm),
109 [{return isUInt<8>(N->getZExtValue());}]
112 def IMM12bit : PatLeaf <(imm),
113 [{return isUInt<12>(N->getZExtValue());}]
116 def IMM16bit : PatLeaf <(imm),
117 [{return isUInt<16>(N->getZExtValue());}]
120 def IMM32bit : PatLeaf <(imm),
121 [{return isUInt<32>(N->getZExtValue());}]
124 def mubuf_vaddr_offset : PatFrag<
125 (ops node:$ptr, node:$offset, node:$imm_offset),
126 (add (add node:$ptr, node:$offset), node:$imm_offset)
129 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
130 return isInlineImmediate(N);
133 class SGPRImm <dag frag> : PatLeaf<frag, [{
134 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
135 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
138 const SIRegisterInfo *SIRI =
139 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
140 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
142 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
149 //===----------------------------------------------------------------------===//
151 //===----------------------------------------------------------------------===//
153 def FRAMEri32 : Operand<iPTR> {
154 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
157 def sopp_brtarget : Operand<OtherVT> {
158 let EncoderMethod = "getSOPPBrEncoding";
159 let OperandType = "OPERAND_PCREL";
162 include "SIInstrFormats.td"
164 //===----------------------------------------------------------------------===//
166 //===----------------------------------------------------------------------===//
168 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
169 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
170 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
172 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
173 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
175 //===----------------------------------------------------------------------===//
176 // SI assembler operands
177 //===----------------------------------------------------------------------===//
196 //===----------------------------------------------------------------------===//
198 // SI Instruction multiclass helpers.
200 // Instructions with _32 take 32-bit operands.
201 // Instructions with _64 take 64-bit operands.
203 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
204 // encoding is the standard encoding, but instruction that make use of
205 // any of the instruction modifiers must use the 64-bit encoding.
207 // Instructions with _e32 use the 32-bit encoding.
208 // Instructions with _e64 use the 64-bit encoding.
210 //===----------------------------------------------------------------------===//
212 //===----------------------------------------------------------------------===//
214 //===----------------------------------------------------------------------===//
216 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
217 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
218 opName#" $dst, $src0", pattern
221 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
222 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
223 opName#" $dst, $src0", pattern
226 // 64-bit input, 32-bit output.
227 class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
228 op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
229 opName#" $dst, $src0", pattern
232 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
233 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
234 opName#" $dst, $src0, $src1", pattern
237 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
238 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
239 opName#" $dst, $src0, $src1", pattern
242 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
243 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
244 opName#" $dst, $src0, $src1", pattern
248 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
249 string opName, PatLeaf cond> : SOPC <
250 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
251 opName#" $dst, $src0, $src1", []>;
253 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
254 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
256 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
257 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
259 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
260 op, (outs SReg_32:$dst), (ins i16imm:$src0),
261 opName#" $dst, $src0", pattern
264 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
265 op, (outs SReg_64:$dst), (ins i16imm:$src0),
266 opName#" $dst, $src0", pattern
269 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass baseClass,
270 RegisterClass dstClass> {
272 op, 1, (outs dstClass:$dst),
273 (ins baseClass:$sbase, u32imm:$offset),
274 asm#" $dst, $sbase, $offset", []
278 op, 0, (outs dstClass:$dst),
279 (ins baseClass:$sbase, SReg_32:$soff),
280 asm#" $dst, $sbase, $soff", []
284 //===----------------------------------------------------------------------===//
285 // Vector ALU classes
286 //===----------------------------------------------------------------------===//
288 // This must always be right before the operand being input modified.
289 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
290 let PrintMethod = "printOperandAndMods";
292 def InputModsNoDefault : Operand <i32> {
293 let PrintMethod = "printOperandAndMods";
296 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
298 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
299 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
303 // Returns the register class to use for the destination of VOP[123C]
304 // instructions for the given VT.
305 class getVALUDstForVT<ValueType VT> {
306 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
309 // Returns the register class to use for source 0 of VOP[12C]
310 // instructions for the given VT.
311 class getVOPSrc0ForVT<ValueType VT> {
312 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
315 // Returns the register class to use for source 1 of VOP[12C] for the
317 class getVOPSrc1ForVT<ValueType VT> {
318 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
321 // Returns the register classes for the source arguments of a VOP[12C]
322 // instruction for the given SrcVTs.
323 class getInRC32 <list<ValueType> SrcVT> {
324 list<RegisterClass> ret = [
325 getVOPSrc0ForVT<SrcVT[0]>.ret,
326 getVOPSrc1ForVT<SrcVT[1]>.ret
330 // Returns the register class to use for sources of VOP3 instructions for the
332 class getVOP3SrcForVT<ValueType VT> {
333 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
336 // Returns the register classes for the source arguments of a VOP3
337 // instruction for the given SrcVTs.
338 class getInRC64 <list<ValueType> SrcVT> {
339 list<RegisterClass> ret = [
340 getVOP3SrcForVT<SrcVT[0]>.ret,
341 getVOP3SrcForVT<SrcVT[1]>.ret,
342 getVOP3SrcForVT<SrcVT[2]>.ret
346 // Returns 1 if the source arguments have modifiers, 0 if they do not.
347 class hasModifiers<ValueType SrcVT> {
348 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
349 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
352 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
353 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
354 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
355 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
359 // Returns the input arguments for VOP3 instructions for the given SrcVT.
360 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
361 RegisterClass Src2RC, int NumSrcArgs,
365 !if (!eq(NumSrcArgs, 1),
366 !if (!eq(HasModifiers, 1),
367 // VOP1 with modifiers
368 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
369 i32imm:$clamp, i32imm:$omod)
371 // VOP1 without modifiers
374 !if (!eq(NumSrcArgs, 2),
375 !if (!eq(HasModifiers, 1),
376 // VOP 2 with modifiers
377 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
378 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
379 i32imm:$clamp, i32imm:$omod)
381 // VOP2 without modifiers
382 (ins Src0RC:$src0, Src1RC:$src1)
384 /* NumSrcArgs == 3 */,
385 !if (!eq(HasModifiers, 1),
386 // VOP3 with modifiers
387 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
388 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
389 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
390 i32imm:$clamp, i32imm:$omod)
392 // VOP3 without modifiers
393 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
397 // Returns the assembly string for the inputs and outputs of a VOP[12C]
398 // instruction. This does not add the _e32 suffix, so it can be reused
400 class getAsm32 <int NumSrcArgs> {
401 string src1 = ", $src1";
402 string src2 = ", $src2";
403 string ret = " $dst, $src0"#
404 !if(!eq(NumSrcArgs, 1), "", src1)#
405 !if(!eq(NumSrcArgs, 3), src2, "");
408 // Returns the assembly string for the inputs and outputs of a VOP3
410 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
411 string src0 = "$src0_modifiers,";
412 string src1 = !if(!eq(NumSrcArgs, 1), "", " $src1_modifiers,");
413 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers,", "");
415 !if(!eq(HasModifiers, 0),
416 getAsm32<NumSrcArgs>.ret,
417 " $dst, "#src0#src1#src2#" $clamp, $omod");
421 class VOPProfile <list<ValueType> _ArgVT> {
423 field list<ValueType> ArgVT = _ArgVT;
425 field ValueType DstVT = ArgVT[0];
426 field ValueType Src0VT = ArgVT[1];
427 field ValueType Src1VT = ArgVT[2];
428 field ValueType Src2VT = ArgVT[3];
429 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
430 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
431 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
432 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
433 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
434 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
436 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
437 field bit HasModifiers = hasModifiers<Src0VT>.ret;
439 field dag Outs = (outs DstRC:$dst);
441 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
442 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
445 field string Asm32 = "_e32 "#getAsm32<NumSrcArgs>.ret;
446 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
449 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
450 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
451 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
452 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
453 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
454 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
455 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
456 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
457 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
459 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
460 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
461 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
462 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
463 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
464 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
465 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
466 let Src0RC32 = VReg_32;
468 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
469 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
471 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
472 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
473 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
474 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
477 class VOP <string opName> {
478 string OpName = opName;
481 class VOP2_REV <string revOp, bit isOrig> {
482 string RevOp = revOp;
486 class SIMCInstr <string pseudo, int subtarget> {
487 string PseudoInstr = pseudo;
488 int Subtarget = subtarget;
491 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
493 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
494 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
495 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
496 bits<2> omod = !if(HasModifiers, ?, 0);
497 bits<1> clamp = !if(HasModifiers, ?, 0);
498 bits<9> src1 = !if(HasSrc1, ?, 0);
499 bits<9> src2 = !if(HasSrc2, ?, 0);
502 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
503 VOP3Common <outs, ins, "", pattern>,
505 SIMCInstr<opName, SISubtarget.NONE> {
509 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
510 VOP3 <op, outs, ins, asm, []>,
511 SIMCInstr<opName, SISubtarget.SI>;
513 multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
514 string opName, int NumSrcArgs, bit HasMods = 1> {
516 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
518 def _si : VOP3_Real_si <op, outs, ins, asm, opName>,
519 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
520 !if(!eq(NumSrcArgs, 2), 0, 1),
525 multiclass VOP3_1_m <bits<8> op, dag outs, dag ins, string asm,
526 list<dag> pattern, string opName, bit HasMods = 1> {
528 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
530 def _si : VOP3_Real_si <
531 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
532 outs, ins, asm, opName>,
533 VOP3DisableFields<0, 0, HasMods>;
536 multiclass VOP3_2_m <bits<9> op, dag outs, dag ins, string asm,
537 list<dag> pattern, string opName, string revOp,
538 bit HasMods = 1, bit UseFullOp = 0> {
540 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
541 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
543 def _si : VOP3_Real_si <op,
544 outs, ins, asm, opName>,
545 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>,
546 VOP3DisableFields<1, 0, HasMods>;
549 multiclass VOP3b_2_m <bits<9> op, dag outs, dag ins, string asm,
550 list<dag> pattern, string opName, string revOp,
551 bit HasMods = 1, bit UseFullOp = 0> {
552 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
553 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
555 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
556 // can write it into any SGPR. We currently don't use the carry out,
557 // so for now hardcode it to VCC as well.
558 let sdst = SIOperand.VCC, Defs = [VCC] in {
559 def _si : VOP3b <op, outs, ins, asm, pattern>,
560 VOP3DisableFields<1, 0, HasMods>,
561 SIMCInstr<opName, SISubtarget.SI>,
562 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
563 } // End sdst = SIOperand.VCC, Defs = [VCC]
566 multiclass VOP3_C_m <bits<8> op, dag outs, dag ins, string asm,
567 list<dag> pattern, string opName,
568 bit HasMods, bit defExec> {
570 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
572 def _si : VOP3_Real_si <
573 {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
574 outs, ins, asm, opName>,
575 VOP3DisableFields<1, 0, HasMods> {
576 let Defs = !if(defExec, [EXEC], []);
580 multiclass VOP1_Helper <bits<8> op, string opName, dag outs,
581 dag ins32, string asm32, list<dag> pat32,
582 dag ins64, string asm64, list<dag> pat64,
585 def _e32 : VOP1 <op, outs, ins32, opName#asm32, pat32>, VOP<opName>;
587 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
590 multiclass VOP1Inst <bits<8> op, string opName, VOPProfile P,
591 SDPatternOperator node = null_frag> : VOP1_Helper <
593 P.Ins32, P.Asm32, [],
596 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
597 i32:$src0_modifiers, i32:$clamp, i32:$omod))))],
598 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
602 class VOP2_e32 <bits<6> op, string opName, dag outs, dag ins, string asm,
603 list<dag> pattern, string revOp> :
604 VOP2 <op, outs, ins, opName#asm, pattern>,
606 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
608 multiclass VOP2_Helper <bits<6> op, string opName, dag outs,
609 dag ins32, string asm32, list<dag> pat32,
610 dag ins64, string asm64, list<dag> pat64,
611 string revOp, bit HasMods> {
612 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
614 defm _e64 : VOP3_2_m <
615 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
616 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
620 multiclass VOP2Inst <bits<6> op, string opName, VOPProfile P,
621 SDPatternOperator node = null_frag,
622 string revOp = opName> : VOP2_Helper <
624 P.Ins32, P.Asm32, [],
628 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
629 i32:$clamp, i32:$omod)),
630 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
631 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
632 revOp, P.HasModifiers
635 multiclass VOP2b_Helper <bits<6> op, string opName, dag outs,
636 dag ins32, string asm32, list<dag> pat32,
637 dag ins64, string asm64, list<dag> pat64,
638 string revOp, bit HasMods> {
640 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
642 defm _e64 : VOP3b_2_m <
643 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
644 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
648 multiclass VOP2bInst <bits<6> op, string opName, VOPProfile P,
649 SDPatternOperator node = null_frag,
650 string revOp = opName> : VOP2b_Helper <
652 P.Ins32, P.Asm32, [],
656 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
657 i32:$clamp, i32:$omod)),
658 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
659 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
660 revOp, P.HasModifiers
663 multiclass VOPC_Helper <bits<8> op, string opName,
664 dag ins32, string asm32, list<dag> pat32,
665 dag out64, dag ins64, string asm64, list<dag> pat64,
666 bit HasMods, bit DefExec> {
667 def _e32 : VOPC <op, ins32, opName#asm32, pat32>, VOP <opName> {
668 let Defs = !if(DefExec, [EXEC], []);
671 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64, opName,
675 multiclass VOPCInst <bits<8> op, string opName,
676 VOPProfile P, PatLeaf cond = COND_NULL,
677 bit DefExec = 0> : VOPC_Helper <
679 P.Ins32, P.Asm32, [],
680 (outs SReg_64:$dst), P.Ins64, P.Asm64,
683 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
684 i32:$clamp, i32:$omod)),
685 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
687 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
688 P.HasModifiers, DefExec
691 multiclass VOPC_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
692 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
694 multiclass VOPC_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
695 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
697 multiclass VOPC_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
698 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
700 multiclass VOPC_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
701 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
704 multiclass VOPCX <bits<8> op, string opName, VOPProfile P,
705 PatLeaf cond = COND_NULL>
706 : VOPCInst <op, opName, P, cond, 1>;
708 multiclass VOPCX_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
709 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
711 multiclass VOPCX_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
712 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
714 multiclass VOPCX_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
715 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
717 multiclass VOPCX_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
718 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
720 multiclass VOP3_Helper <bits<9> op, string opName, dag outs, dag ins, string asm,
721 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
722 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
725 multiclass VOP3Inst <bits<9> op, string opName, VOPProfile P,
726 SDPatternOperator node = null_frag> : VOP3_Helper <
727 op, opName, P.Outs, P.Ins64, P.Asm64,
728 !if(!eq(P.NumSrcArgs, 3),
731 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
732 i32:$clamp, i32:$omod)),
733 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
734 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
735 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
737 !if(!eq(P.NumSrcArgs, 2),
740 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
741 i32:$clamp, i32:$omod)),
742 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
743 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
744 /* P.NumSrcArgs == 1 */,
747 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
748 i32:$clamp, i32:$omod))))],
749 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
750 P.NumSrcArgs, P.HasModifiers
753 multiclass VOP3b_Helper <bits<9> op, RegisterClass vrc, RegisterClass arc,
754 string opName, list<dag> pattern> :
756 op, (outs vrc:$dst0, SReg_64:$dst1),
757 (ins arc:$src0, arc:$src1, arc:$src2,
758 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
759 opName#" $dst0, $dst1, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern,
763 multiclass VOP3b_64 <bits<9> op, string opName, list<dag> pattern> :
764 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
766 multiclass VOP3b_32 <bits<9> op, string opName, list<dag> pattern> :
767 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
769 //===----------------------------------------------------------------------===//
770 // Vector I/O classes
771 //===----------------------------------------------------------------------===//
773 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
774 DS <op, outs, ins, asm, pat> {
777 // Single load interpret the 2 i8imm operands as a single i16 offset.
778 let offset0 = offset{7-0};
779 let offset1 = offset{15-8};
782 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
784 (outs regClass:$vdst),
785 (ins i1imm:$gds, VReg_32:$addr, u16imm:$offset),
786 asm#" $vdst, $addr, $offset, [M0]",
794 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
796 (outs regClass:$vdst),
797 (ins i1imm:$gds, VReg_32:$addr, u8imm:$offset0, u8imm:$offset1),
798 asm#" $vdst, $addr, $offset0, $offset1, [M0]",
806 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
809 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u16imm:$offset),
810 asm#" $addr, $data0, $offset [M0]",
818 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
821 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u8imm:$offset0, u8imm:$offset1),
822 asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]",
829 // 1 address, 1 data.
830 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
833 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
834 asm#" $vdst, $addr, $data0, $offset, [M0]",
842 // 1 address, 2 data.
843 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
846 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
847 asm#" $vdst, $addr, $data0, $data1, $offset, [M0]",
853 // 1 address, 2 data.
854 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
857 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
858 asm#" $addr, $data0, $data1, $offset, [M0]",
864 // 1 address, 1 data.
865 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
868 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
869 asm#" $addr, $data0, $offset, [M0]",
877 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
880 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
881 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
882 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
883 asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
884 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
890 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
891 ValueType load_vt = i32,
892 SDPatternOperator ld = null_frag> {
894 let lds = 0, mayLoad = 1 in {
898 let offen = 0, idxen = 0, vaddr = 0 in {
899 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
900 (ins SReg_128:$srsrc,
901 u16imm:$offset, SSrc_32:$soffset, i1imm:$glc,
902 i1imm:$slc, i1imm:$tfe),
903 asm#" $vdata, $srsrc + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
906 let offen = 1, idxen = 0 in {
907 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
908 (ins SReg_128:$srsrc, VReg_32:$vaddr,
909 SSrc_32:$soffset, u16imm:$offset, i1imm:$glc, i1imm:$slc,
911 asm#" $vdata, $srsrc + $vaddr + $soffset + $offset, glc=$glc, slc=$slc, tfe=$tfe", []>;
914 let offen = 0, idxen = 1 in {
915 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
916 (ins SReg_128:$srsrc, VReg_32:$vaddr,
917 u16imm:$offset, SSrc_32:$soffset, i1imm:$glc,
918 i1imm:$slc, i1imm:$tfe),
919 asm#" $vdata, $srsrc[$vaddr] + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
922 let offen = 1, idxen = 1 in {
923 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
924 (ins SReg_128:$srsrc, VReg_64:$vaddr,
925 SSrc_32:$soffset, i1imm:$glc,
926 i1imm:$slc, i1imm:$tfe),
927 asm#" $vdata, $srsrc[$vaddr[0]] + $vaddr[1] + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
931 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
932 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
933 (ins SReg_128:$srsrc, VReg_64:$vaddr, u16imm:$offset),
934 asm#" $vdata, $srsrc + $vaddr + $offset",
935 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
936 i64:$vaddr, u16imm:$offset)))]>;
941 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
942 ValueType store_vt, SDPatternOperator st> {
946 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
947 u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$slc,
949 name#" $vdata, $srsrc, $vaddr, $soffset, $offset $offen $idxen $glc $slc $tfe",
955 def _ADDR64 : MUBUF <
957 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, u16imm:$offset),
958 name#" $vdata, $srsrc + $vaddr + $offset",
959 [(st store_vt:$vdata,
960 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, u16imm:$offset))]> {
973 let soffset = 128; // ZERO
977 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
979 (outs regClass:$dst),
980 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
981 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
982 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
983 asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
984 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
990 class MIMG_Mask <string op, int channels> {
992 int Channels = channels;
995 class MIMG_NoSampler_Helper <bits<7> op, string asm,
996 RegisterClass dst_rc,
997 RegisterClass src_rc> : MIMG <
999 (outs dst_rc:$vdata),
1000 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1001 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1003 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1004 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1009 let hasPostISelHook = 1;
1012 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1013 RegisterClass dst_rc,
1015 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1016 MIMG_Mask<asm#"_V1", channels>;
1017 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1018 MIMG_Mask<asm#"_V2", channels>;
1019 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1020 MIMG_Mask<asm#"_V4", channels>;
1023 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1024 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1025 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1026 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1027 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1030 class MIMG_Sampler_Helper <bits<7> op, string asm,
1031 RegisterClass dst_rc,
1032 RegisterClass src_rc> : MIMG <
1034 (outs dst_rc:$vdata),
1035 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1036 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1037 SReg_256:$srsrc, SReg_128:$ssamp),
1038 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1039 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1043 let hasPostISelHook = 1;
1046 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1047 RegisterClass dst_rc,
1049 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1050 MIMG_Mask<asm#"_V1", channels>;
1051 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1052 MIMG_Mask<asm#"_V2", channels>;
1053 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1054 MIMG_Mask<asm#"_V4", channels>;
1055 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1056 MIMG_Mask<asm#"_V8", channels>;
1057 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1058 MIMG_Mask<asm#"_V16", channels>;
1061 multiclass MIMG_Sampler <bits<7> op, string asm> {
1062 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1063 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1064 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1065 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1068 class MIMG_Gather_Helper <bits<7> op, string asm,
1069 RegisterClass dst_rc,
1070 RegisterClass src_rc> : MIMG <
1072 (outs dst_rc:$vdata),
1073 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1074 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1075 SReg_256:$srsrc, SReg_128:$ssamp),
1076 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1077 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1082 // DMASK was repurposed for GATHER4. 4 components are always
1083 // returned and DMASK works like a swizzle - it selects
1084 // the component to fetch. The only useful DMASK values are
1085 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1086 // (red,red,red,red) etc.) The ISA document doesn't mention
1088 // Therefore, disable all code which updates DMASK by setting these two:
1090 let hasPostISelHook = 0;
1093 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1094 RegisterClass dst_rc,
1096 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1097 MIMG_Mask<asm#"_V1", channels>;
1098 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1099 MIMG_Mask<asm#"_V2", channels>;
1100 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1101 MIMG_Mask<asm#"_V4", channels>;
1102 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1103 MIMG_Mask<asm#"_V8", channels>;
1104 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1105 MIMG_Mask<asm#"_V16", channels>;
1108 multiclass MIMG_Gather <bits<7> op, string asm> {
1109 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1110 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1111 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1112 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1115 //===----------------------------------------------------------------------===//
1116 // Vector instruction mappings
1117 //===----------------------------------------------------------------------===//
1119 // Maps an opcode in e32 form to its e64 equivalent
1120 def getVOPe64 : InstrMapping {
1121 let FilterClass = "VOP";
1122 let RowFields = ["OpName"];
1123 let ColFields = ["Size"];
1125 let ValueCols = [["8"]];
1128 // Maps an opcode in e64 form to its e32 equivalent
1129 def getVOPe32 : InstrMapping {
1130 let FilterClass = "VOP";
1131 let RowFields = ["OpName"];
1132 let ColFields = ["Size"];
1134 let ValueCols = [["4"]];
1137 // Maps an original opcode to its commuted version
1138 def getCommuteRev : InstrMapping {
1139 let FilterClass = "VOP2_REV";
1140 let RowFields = ["RevOp"];
1141 let ColFields = ["IsOrig"];
1143 let ValueCols = [["0"]];
1146 def getMaskedMIMGOp : InstrMapping {
1147 let FilterClass = "MIMG_Mask";
1148 let RowFields = ["Op"];
1149 let ColFields = ["Channels"];
1151 let ValueCols = [["1"], ["2"], ["3"] ];
1154 // Maps an commuted opcode to its original version
1155 def getCommuteOrig : InstrMapping {
1156 let FilterClass = "VOP2_REV";
1157 let RowFields = ["RevOp"];
1158 let ColFields = ["IsOrig"];
1160 let ValueCols = [["1"]];
1163 def isDS : InstrMapping {
1164 let FilterClass = "DS";
1165 let RowFields = ["Inst"];
1166 let ColFields = ["Size"];
1168 let ValueCols = [["8"]];
1171 def getMCOpcode : InstrMapping {
1172 let FilterClass = "SIMCInstr";
1173 let RowFields = ["PseudoInstr"];
1174 let ColFields = ["Subtarget"];
1175 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1176 let ValueCols = [[!cast<string>(SISubtarget.SI)]];
1179 include "SIInstructions.td"