1 //===-- SIInstrInfo.td - SI Instruction Encodings ---------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 def SDTVCCBinaryOp : SDTypeProfile<1, 2, [
14 SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 2>
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 // and operation on 64-bit wide vcc
22 def SIsreg1_and : SDNode<"SIISD::VCC_AND", SDTVCCBinaryOp,
23 [SDNPCommutative, SDNPAssociative]
26 // Special bitcast node for sharing VCC register between VALU and SALU
27 def SIsreg1_bitcast : SDNode<"SIISD::VCC_BITCAST",
28 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>
31 // and operation on 64-bit wide vcc
32 def SIvcc_and : SDNode<"SIISD::VCC_AND", SDTVCCBinaryOp,
33 [SDNPCommutative, SDNPAssociative]
36 // Special bitcast node for sharing VCC register between VALU and SALU
37 def SIvcc_bitcast : SDNode<"SIISD::VCC_BITCAST",
38 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>
41 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
42 AMDGPUInst<outs, ins, asm, pattern> {
44 field bits<4> EncodingType = 0;
45 field bits<1> VM_CNT = 0;
46 field bits<1> EXP_CNT = 0;
47 field bits<1> LGKM_CNT = 0;
49 let TSFlags{3-0} = EncodingType;
50 let TSFlags{4} = VM_CNT;
51 let TSFlags{5} = EXP_CNT;
52 let TSFlags{6} = LGKM_CNT;
55 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
56 InstSI <outs, ins, asm, pattern> {
61 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
62 InstSI <outs, ins, asm, pattern> {
67 class SIOperand <ValueType vt, dag opInfo>: Operand <vt> {
68 let EncoderMethod = "encodeOperand";
69 let MIOperandInfo = opInfo;
72 def IMM16bit : ImmLeaf <
74 [{return isInt<16>(Imm);}]
77 def IMM8bit : ImmLeaf <
79 [{return (int32_t)Imm >= 0 && (int32_t)Imm <= 0xff;}]
82 def IMM12bit : ImmLeaf <
84 [{return (int16_t)Imm >= 0 && (int16_t)Imm <= 0xfff;}]
87 def IMM32bitIn64bit : ImmLeaf <
89 [{return isInt<32>(Imm);}]
92 class GPR4Align <RegisterClass rc> : Operand <vAny> {
93 let EncoderMethod = "GPR4AlignEncode";
94 let MIOperandInfo = (ops rc:$reg);
97 class GPR2Align <RegisterClass rc, ValueType vt> : Operand <vt> {
98 let EncoderMethod = "GPR2AlignEncode";
99 let MIOperandInfo = (ops rc:$reg);
102 def SMRDmemrr : Operand<iPTR> {
103 let MIOperandInfo = (ops SReg_64, SReg_32);
104 let EncoderMethod = "GPR2AlignEncode";
107 def SMRDmemri : Operand<iPTR> {
108 let MIOperandInfo = (ops SReg_64, i32imm);
109 let EncoderMethod = "SMRDmemriEncode";
112 def ADDR_Reg : ComplexPattern<i64, 2, "SelectADDRReg", [], []>;
113 def ADDR_Offset8 : ComplexPattern<i64, 2, "SelectADDR8BitOffset", [], []>;
115 let Uses = [EXEC] in {
119 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
120 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
121 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
136 let Inst{10} = COMPR;
139 let Inst{31-26} = 0x3e;
140 let Inst{39-32} = VSRC0;
141 let Inst{47-40} = VSRC1;
142 let Inst{55-48} = VSRC2;
143 let Inst{63-56} = VSRC3;
144 let EncodingType = 0; //SIInstrEncodingType::EXP
149 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
150 Enc64 <outs, ins, asm, pattern> {
165 let Inst{11-8} = DMASK;
166 let Inst{12} = UNORM;
172 let Inst{24-18} = op;
174 let Inst{31-26} = 0x3c;
175 let Inst{39-32} = VADDR;
176 let Inst{47-40} = VDATA;
177 let Inst{52-48} = SRSRC;
178 let Inst{57-53} = SSAMP;
179 let EncodingType = 2; //SIInstrEncodingType::MIMG
185 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
186 Enc64<outs, ins, asm, pattern> {
202 let Inst{11-0} = OFFSET;
203 let Inst{12} = OFFEN;
204 let Inst{13} = IDXEN;
206 let Inst{15} = ADDR64;
207 let Inst{18-16} = op;
208 let Inst{22-19} = DFMT;
209 let Inst{25-23} = NFMT;
210 let Inst{31-26} = 0x3a; //encoding
211 let Inst{39-32} = VADDR;
212 let Inst{47-40} = VDATA;
213 let Inst{52-48} = SRSRC;
216 let Inst{63-56} = SOFFSET;
217 let EncodingType = 3; //SIInstrEncodingType::MTBUF
222 let neverHasSideEffects = 1;
225 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
226 Enc64<outs, ins, asm, pattern> {
241 let Inst{11-0} = OFFSET;
242 let Inst{12} = OFFEN;
243 let Inst{13} = IDXEN;
245 let Inst{15} = ADDR64;
247 let Inst{24-18} = op;
248 let Inst{31-26} = 0x38; //encoding
249 let Inst{39-32} = VADDR;
250 let Inst{47-40} = VDATA;
251 let Inst{52-48} = SRSRC;
254 let Inst{63-56} = SOFFSET;
255 let EncodingType = 4; //SIInstrEncodingType::MUBUF
260 let neverHasSideEffects = 1;
263 } // End Uses = [EXEC]
265 class SMRD <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
266 Enc32<outs, ins, asm, pattern> {
270 bits<8> OFFSET = PTR{7-0};
271 bits<1> IMM = PTR{8};
272 bits<6> SBASE = PTR{14-9};
274 let Inst{7-0} = OFFSET;
276 let Inst{14-9} = SBASE;
277 let Inst{21-15} = SDST;
278 let Inst{26-22} = op;
279 let Inst{31-27} = 0x18; //encoding
280 let EncodingType = 5; //SIInstrEncodingType::SMRD
285 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
286 Enc32<outs, ins, asm, pattern> {
291 let Inst{7-0} = SSRC0;
293 let Inst{22-16} = SDST;
294 let Inst{31-23} = 0x17d; //encoding;
295 let EncodingType = 6; //SIInstrEncodingType::SOP1
299 let hasSideEffects = 0;
302 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
303 Enc32 <outs, ins, asm, pattern> {
309 let Inst{7-0} = SSRC0;
310 let Inst{15-8} = SSRC1;
311 let Inst{22-16} = SDST;
312 let Inst{29-23} = op;
313 let Inst{31-30} = 0x2; // encoding
314 let EncodingType = 7; // SIInstrEncodingType::SOP2
318 let hasSideEffects = 0;
321 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
322 Enc32<outs, ins, asm, pattern> {
327 let Inst{7-0} = SSRC0;
328 let Inst{15-8} = SSRC1;
329 let Inst{22-16} = op;
330 let Inst{31-23} = 0x17e;
331 let EncodingType = 8; // SIInstrEncodingType::SOPC
333 let DisableEncoding = "$dst";
336 let hasSideEffects = 0;
339 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
340 Enc32 <outs, ins , asm, pattern> {
345 let Inst{15-0} = SIMM16;
346 let Inst{22-16} = SDST;
347 let Inst{27-23} = op;
348 let Inst{31-28} = 0xb; //encoding
349 let EncodingType = 9; // SIInstrEncodingType::SOPK
353 let hasSideEffects = 0;
356 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 <
364 let Inst{15-0} = SIMM16;
365 let Inst{22-16} = op;
366 let Inst{31-23} = 0x17f; // encoding
367 let EncodingType = 10; // SIInstrEncodingType::SOPP
371 let hasSideEffects = 0;
374 let Uses = [EXEC] in {
376 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
377 Enc32 <outs, ins, asm, pattern> {
384 let Inst{7-0} = VSRC;
385 let Inst{9-8} = ATTRCHAN;
386 let Inst{15-10} = ATTR;
387 let Inst{17-16} = op;
388 let Inst{25-18} = VDST;
389 let Inst{31-26} = 0x32; // encoding
390 let EncodingType = 11; // SIInstrEncodingType::VINTRP
392 let neverHasSideEffects = 1;
397 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
398 Enc32 <outs, ins, asm, pattern> {
403 let Inst{8-0} = SRC0;
405 let Inst{24-17} = VDST;
406 let Inst{31-25} = 0x3f; //encoding
408 let EncodingType = 12; // SIInstrEncodingType::VOP1
409 let PostEncoderMethod = "VOPPostEncode";
413 let hasSideEffects = 0;
416 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
417 Enc32 <outs, ins, asm, pattern> {
423 let Inst{8-0} = SRC0;
424 let Inst{16-9} = VSRC1;
425 let Inst{24-17} = VDST;
426 let Inst{30-25} = op;
427 let Inst{31} = 0x0; //encoding
429 let EncodingType = 13; // SIInstrEncodingType::VOP2
430 let PostEncoderMethod = "VOPPostEncode";
434 let hasSideEffects = 0;
437 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
438 Enc64 <outs, ins, asm, pattern> {
449 let Inst{7-0} = VDST;
450 let Inst{10-8} = ABS;
451 let Inst{11} = CLAMP;
452 let Inst{25-17} = op;
453 let Inst{31-26} = 0x34; //encoding
454 let Inst{40-32} = SRC0;
455 let Inst{49-41} = SRC1;
456 let Inst{58-50} = SRC2;
457 let Inst{60-59} = OMOD;
458 let Inst{63-61} = NEG;
460 let EncodingType = 14; // SIInstrEncodingType::VOP3
461 let PostEncoderMethod = "VOPPostEncode";
465 let hasSideEffects = 0;
468 class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
469 Enc64 <outs, ins, asm, pattern> {
479 let Inst{7-0} = VDST;
480 let Inst{14-8} = SDST;
481 let Inst{25-17} = op;
482 let Inst{31-26} = 0x34; //encoding
483 let Inst{40-32} = SRC0;
484 let Inst{49-41} = SRC1;
485 let Inst{58-50} = SRC2;
486 let Inst{60-59} = OMOD;
487 let Inst{63-61} = NEG;
489 let EncodingType = 14; // SIInstrEncodingType::VOP3
490 let PostEncoderMethod = "VOPPostEncode";
494 let hasSideEffects = 0;
497 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
498 Enc32 <(outs VCCReg:$dst), ins, asm, pattern> {
503 let Inst{8-0} = SRC0;
504 let Inst{16-9} = VSRC1;
505 let Inst{24-17} = op;
506 let Inst{31-25} = 0x3e;
508 let EncodingType = 15; //SIInstrEncodingType::VOPC
509 let PostEncoderMethod = "VOPPostEncode";
510 let DisableEncoding = "$dst";
513 let hasSideEffects = 0;
516 } // End Uses = [EXEC]
518 class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
520 (outs VReg_128:$vdata),
521 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
522 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_32:$vaddr,
523 GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
530 class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
532 (outs regClass:$dst),
533 (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
534 i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
535 i1imm:$tfe, SReg_32:$soffset),
542 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
544 (outs regClass:$dst),
545 (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
546 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc,
547 i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
554 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
557 (ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
558 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
559 GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
566 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass,
570 (outs dstClass:$dst),
571 (ins SMRDmemri:$src0),
573 [(set (vt dstClass:$dst), (constant_load ADDR_Offset8:$src0))]
578 (outs dstClass:$dst),
579 (ins SMRDmemrr:$src0),
581 [(set (vt dstClass:$dst), (constant_load ADDR_Reg:$src0))]
585 multiclass SMRD_32 <bits<5> op, string asm, RegisterClass dstClass> {
586 defm _F32 : SMRD_Helper <op, asm, dstClass, f32>;
587 defm _I32 : SMRD_Helper <op, asm, dstClass, i32>;
590 include "SIInstrFormats.td"
591 include "SIInstructions.td"