1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
40 // that doesn't have VOP2 encoding on VI
41 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
45 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
50 class sop1 <bits<8> si, bits<8> vi = si> {
51 field bits<8> SI = si;
52 field bits<8> VI = vi;
55 class sop2 <bits<7> si, bits<7> vi = si> {
56 field bits<7> SI = si;
57 field bits<7> VI = vi;
60 class sopk <bits<5> si, bits<5> vi = si> {
61 field bits<5> SI = si;
62 field bits<5> VI = vi;
65 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66 // in AMDGPUInstrInfo.cpp
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79 [SDNPMayLoad, SDNPMemOperand]
82 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
84 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
85 SDTCisVT<1, iAny>, // vdata(VGPR)
86 SDTCisVT<2, i32>, // num_channels(imm)
87 SDTCisVT<3, i32>, // vaddr(VGPR)
88 SDTCisVT<4, i32>, // soffset(SGPR)
89 SDTCisVT<5, i32>, // inst_offset(imm)
90 SDTCisVT<6, i32>, // dfmt(imm)
91 SDTCisVT<7, i32>, // nfmt(imm)
92 SDTCisVT<8, i32>, // offen(imm)
93 SDTCisVT<9, i32>, // idxen(imm)
94 SDTCisVT<10, i32>, // glc(imm)
95 SDTCisVT<11, i32>, // slc(imm)
96 SDTCisVT<12, i32> // tfe(imm)
98 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
101 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
106 class SDSample<string opcode> : SDNode <opcode,
107 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
111 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
116 def SIconstdata_ptr : SDNode<
117 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
120 // Transformation function, extract the lower 32bit of a 64bit immediate
121 def LO32 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
125 def LO32f : SDNodeXForm<fpimm, [{
126 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
130 // Transformation function, extract the upper 32bit of a 64bit immediate
131 def HI32 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
135 def HI32f : SDNodeXForm<fpimm, [{
136 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
140 def IMM8bitDWORD : PatLeaf <(imm),
141 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
144 def as_dword_i32imm : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
148 def as_i1imm : SDNodeXForm<imm, [{
149 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
152 def as_i8imm : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
156 def as_i16imm : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
160 def as_i32imm: SDNodeXForm<imm, [{
161 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
164 def as_i64imm: SDNodeXForm<imm, [{
165 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
174 // Copied from the AArch64 backend:
175 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176 return CurDAG->getTargetConstant(
177 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
180 def IMM8bit : PatLeaf <(imm),
181 [{return isUInt<8>(N->getZExtValue());}]
184 def IMM12bit : PatLeaf <(imm),
185 [{return isUInt<12>(N->getZExtValue());}]
188 def IMM16bit : PatLeaf <(imm),
189 [{return isUInt<16>(N->getZExtValue());}]
192 def IMM20bit : PatLeaf <(imm),
193 [{return isUInt<20>(N->getZExtValue());}]
196 def IMM32bit : PatLeaf <(imm),
197 [{return isUInt<32>(N->getZExtValue());}]
200 def mubuf_vaddr_offset : PatFrag<
201 (ops node:$ptr, node:$offset, node:$imm_offset),
202 (add (add node:$ptr, node:$offset), node:$imm_offset)
205 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206 return isInlineImmediate(N);
209 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210 return isInlineImmediate(N);
213 class SGPRImm <dag frag> : PatLeaf<frag, [{
214 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
217 const SIRegisterInfo *SIRI =
218 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
219 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
221 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
228 //===----------------------------------------------------------------------===//
230 //===----------------------------------------------------------------------===//
232 def FRAMEri32 : Operand<iPTR> {
233 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
236 def sopp_brtarget : Operand<OtherVT> {
237 let EncoderMethod = "getSOPPBrEncoding";
238 let OperandType = "OPERAND_PCREL";
241 include "SIInstrFormats.td"
242 include "VIInstrFormats.td"
244 let OperandType = "OPERAND_IMMEDIATE" in {
246 def offen : Operand<i1> {
247 let PrintMethod = "printOffen";
249 def idxen : Operand<i1> {
250 let PrintMethod = "printIdxen";
252 def addr64 : Operand<i1> {
253 let PrintMethod = "printAddr64";
255 def mbuf_offset : Operand<i16> {
256 let PrintMethod = "printMBUFOffset";
258 def ds_offset : Operand<i16> {
259 let PrintMethod = "printDSOffset";
261 def ds_offset0 : Operand<i8> {
262 let PrintMethod = "printDSOffset0";
264 def ds_offset1 : Operand<i8> {
265 let PrintMethod = "printDSOffset1";
267 def gds : Operand <i1> {
268 let PrintMethod = "printGDS";
270 def glc : Operand <i1> {
271 let PrintMethod = "printGLC";
273 def slc : Operand <i1> {
274 let PrintMethod = "printSLC";
276 def tfe : Operand <i1> {
277 let PrintMethod = "printTFE";
280 def omod : Operand <i32> {
281 let PrintMethod = "printOModSI";
284 def ClampMod : Operand <i1> {
285 let PrintMethod = "printClampSI";
288 } // End OperandType = "OPERAND_IMMEDIATE"
290 //===----------------------------------------------------------------------===//
292 //===----------------------------------------------------------------------===//
294 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
295 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
297 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
298 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
299 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
300 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
301 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
302 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
304 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
305 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
306 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
307 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
309 //===----------------------------------------------------------------------===//
310 // SI assembler operands
311 //===----------------------------------------------------------------------===//
331 //===----------------------------------------------------------------------===//
333 // SI Instruction multiclass helpers.
335 // Instructions with _32 take 32-bit operands.
336 // Instructions with _64 take 64-bit operands.
338 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
339 // encoding is the standard encoding, but instruction that make use of
340 // any of the instruction modifiers must use the 64-bit encoding.
342 // Instructions with _e32 use the 32-bit encoding.
343 // Instructions with _e64 use the 64-bit encoding.
345 //===----------------------------------------------------------------------===//
347 class SIMCInstr <string pseudo, int subtarget> {
348 string PseudoInstr = pseudo;
349 int Subtarget = subtarget;
352 //===----------------------------------------------------------------------===//
354 //===----------------------------------------------------------------------===//
356 class EXPCommon : InstSI<
358 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
359 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
360 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
369 let isPseudo = 1, isCodeGenOnly = 1 in {
370 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
373 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
375 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
378 //===----------------------------------------------------------------------===//
380 //===----------------------------------------------------------------------===//
382 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
383 SOP1 <outs, ins, "", pattern>,
384 SIMCInstr<opName, SISubtarget.NONE> {
386 let isCodeGenOnly = 1;
389 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
390 SOP1 <outs, ins, asm, []>,
392 SIMCInstr<opName, SISubtarget.SI>;
394 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
395 SOP1 <outs, ins, asm, []>,
397 SIMCInstr<opName, SISubtarget.VI>;
399 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
402 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
404 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
406 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
410 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
411 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
412 opName#" $dst, $src0", pattern
415 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
416 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
417 opName#" $dst, $src0", pattern
420 // no input, 64-bit output.
421 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
422 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
424 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
429 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
435 // 64-bit input, no output
436 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
437 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
439 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
444 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
450 // 64-bit input, 32-bit output.
451 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
452 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
453 opName#" $dst, $src0", pattern
456 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
457 SOP2<outs, ins, "", pattern>,
458 SIMCInstr<opName, SISubtarget.NONE> {
460 let isCodeGenOnly = 1;
463 // Pseudo instructions have no encodings, but adding this field here allows
465 // let sdst = xxx in {
466 // for multiclasses that include both real and pseudo instructions.
467 field bits<7> sdst = 0;
470 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
471 SOP2<outs, ins, asm, []>,
473 SIMCInstr<opName, SISubtarget.SI>;
475 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
476 SOP2<outs, ins, asm, []>,
478 SIMCInstr<opName, SISubtarget.VI>;
480 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
481 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
482 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
484 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
485 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
486 opName#" $dst, $src0, $src1 [$scc]">;
488 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
489 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
490 opName#" $dst, $src0, $src1 [$scc]">;
493 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
496 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
498 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
500 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
504 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
505 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
506 opName#" $dst, $src0, $src1", pattern
509 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
510 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
511 opName#" $dst, $src0, $src1", pattern
514 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
515 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
516 opName#" $dst, $src0, $src1", pattern
519 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
520 string opName, PatLeaf cond> : SOPC <
521 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
522 opName#" $dst, $src0, $src1", []>;
524 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
525 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
527 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
528 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
530 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
531 SOPK <outs, ins, "", pattern>,
532 SIMCInstr<opName, SISubtarget.NONE> {
534 let isCodeGenOnly = 1;
537 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
538 SOPK <outs, ins, asm, []>,
540 SIMCInstr<opName, SISubtarget.SI>;
542 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
543 SOPK <outs, ins, asm, []>,
545 SIMCInstr<opName, SISubtarget.VI>;
547 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
548 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
551 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
552 opName#" $dst, $src0">;
554 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
555 opName#" $dst, $src0">;
558 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
559 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
560 (ins SReg_32:$src0, u16imm:$src1), pattern>;
562 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
563 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
565 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
566 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
569 //===----------------------------------------------------------------------===//
571 //===----------------------------------------------------------------------===//
573 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
574 SMRD <outs, ins, "", pattern>,
575 SIMCInstr<opName, SISubtarget.NONE> {
577 let isCodeGenOnly = 1;
580 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
582 SMRD <outs, ins, asm, []>,
584 SIMCInstr<opName, SISubtarget.SI>;
586 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
588 SMRD <outs, ins, asm, []>,
590 SIMCInstr<opName, SISubtarget.VI>;
592 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
593 string asm, list<dag> pattern> {
595 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
597 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
599 // glc is only applicable to scalar stores, which are not yet
602 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
606 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
607 RegisterClass dstClass> {
609 op, opName#"_IMM", 1, (outs dstClass:$dst),
610 (ins baseClass:$sbase, u32imm:$offset),
611 opName#" $dst, $sbase, $offset", []
614 defm _SGPR : SMRD_m <
615 op, opName#"_SGPR", 0, (outs dstClass:$dst),
616 (ins baseClass:$sbase, SReg_32:$soff),
617 opName#" $dst, $sbase, $soff", []
621 //===----------------------------------------------------------------------===//
622 // Vector ALU classes
623 //===----------------------------------------------------------------------===//
625 // This must always be right before the operand being input modified.
626 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
627 let PrintMethod = "printOperandAndMods";
629 def InputModsNoDefault : Operand <i32> {
630 let PrintMethod = "printOperandAndMods";
633 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
635 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
636 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
640 // Returns the register class to use for the destination of VOP[123C]
641 // instructions for the given VT.
642 class getVALUDstForVT<ValueType VT> {
643 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32,
644 !if(!eq(VT.Size, 64), VReg_64,
645 SReg_64)); // else VT == i1
648 // Returns the register class to use for source 0 of VOP[12C]
649 // instructions for the given VT.
650 class getVOPSrc0ForVT<ValueType VT> {
651 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
654 // Returns the register class to use for source 1 of VOP[12C] for the
656 class getVOPSrc1ForVT<ValueType VT> {
657 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
660 // Returns the register class to use for sources of VOP3 instructions for the
662 class getVOP3SrcForVT<ValueType VT> {
663 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
666 // Returns 1 if the source arguments have modifiers, 0 if they do not.
667 class hasModifiers<ValueType SrcVT> {
668 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
669 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
672 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
673 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
674 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
675 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
679 // Returns the input arguments for VOP3 instructions for the given SrcVT.
680 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
681 RegisterOperand Src2RC, int NumSrcArgs,
685 !if (!eq(NumSrcArgs, 1),
686 !if (!eq(HasModifiers, 1),
687 // VOP1 with modifiers
688 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
689 ClampMod:$clamp, omod:$omod)
691 // VOP1 without modifiers
694 !if (!eq(NumSrcArgs, 2),
695 !if (!eq(HasModifiers, 1),
696 // VOP 2 with modifiers
697 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
698 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
699 ClampMod:$clamp, omod:$omod)
701 // VOP2 without modifiers
702 (ins Src0RC:$src0, Src1RC:$src1)
704 /* NumSrcArgs == 3 */,
705 !if (!eq(HasModifiers, 1),
706 // VOP3 with modifiers
707 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
708 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
709 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
710 ClampMod:$clamp, omod:$omod)
712 // VOP3 without modifiers
713 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
717 // Returns the assembly string for the inputs and outputs of a VOP[12C]
718 // instruction. This does not add the _e32 suffix, so it can be reused
720 class getAsm32 <int NumSrcArgs> {
721 string src1 = ", $src1";
722 string src2 = ", $src2";
723 string ret = " $dst, $src0"#
724 !if(!eq(NumSrcArgs, 1), "", src1)#
725 !if(!eq(NumSrcArgs, 3), src2, "");
728 // Returns the assembly string for the inputs and outputs of a VOP3
730 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
731 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
732 string src1 = !if(!eq(NumSrcArgs, 1), "",
733 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
734 " $src1_modifiers,"));
735 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
737 !if(!eq(HasModifiers, 0),
738 getAsm32<NumSrcArgs>.ret,
739 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
743 class VOPProfile <list<ValueType> _ArgVT> {
745 field list<ValueType> ArgVT = _ArgVT;
747 field ValueType DstVT = ArgVT[0];
748 field ValueType Src0VT = ArgVT[1];
749 field ValueType Src1VT = ArgVT[2];
750 field ValueType Src2VT = ArgVT[3];
751 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
752 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
753 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
754 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
755 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
756 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
758 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
759 field bit HasModifiers = hasModifiers<Src0VT>.ret;
761 field dag Outs = (outs DstRC:$dst);
763 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
764 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
767 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
768 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
771 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
772 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
773 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
774 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
775 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
776 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
777 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
778 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
779 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
781 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
782 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
783 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
784 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
785 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
786 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
787 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
788 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
789 let Src0RC32 = VCSrc_32;
792 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
793 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
794 let Asm64 = " $dst, $src0_modifiers, $src1";
797 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
798 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
799 let Asm64 = " $dst, $src0_modifiers, $src1";
802 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
803 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
804 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
805 def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
806 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2);
807 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
808 let Asm64 = " $dst, $src0, $src1, $src2";
811 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
812 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
813 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
814 field string Asm = " $dst, $src0, $vsrc1, $src2";
816 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
817 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
818 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
821 class VOP <string opName> {
822 string OpName = opName;
825 class VOP2_REV <string revOp, bit isOrig> {
826 string RevOp = revOp;
830 class AtomicNoRet <string noRetOp, bit isRet> {
831 string NoRetOp = noRetOp;
835 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
836 VOP1Common <outs, ins, "", pattern>,
838 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
840 let isCodeGenOnly = 1;
846 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
848 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
850 def _si : VOP1<op.SI, outs, ins, asm, []>,
851 SIMCInstr <opName#"_e32", SISubtarget.SI>;
852 def _vi : VOP1<op.VI, outs, ins, asm, []>,
853 SIMCInstr <opName#"_e32", SISubtarget.VI>;
856 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
858 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
860 def _si : VOP1<op.SI, outs, ins, asm, []>,
861 SIMCInstr <opName#"_e32", SISubtarget.SI>;
862 // No VI instruction. This class is for SI only.
865 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
866 VOP2Common <outs, ins, "", pattern>,
868 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
870 let isCodeGenOnly = 1;
873 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
874 string opName, string revOp> {
875 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
876 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
878 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
879 SIMCInstr <opName#"_e32", SISubtarget.SI>;
882 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
883 string opName, string revOp> {
884 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
885 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
887 def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
888 SIMCInstr <opName#"_e32", SISubtarget.SI>;
889 def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
890 SIMCInstr <opName#"_e32", SISubtarget.VI>;
893 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
895 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
896 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
897 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
898 bits<2> omod = !if(HasModifiers, ?, 0);
899 bits<1> clamp = !if(HasModifiers, ?, 0);
900 bits<9> src1 = !if(HasSrc1, ?, 0);
901 bits<9> src2 = !if(HasSrc2, ?, 0);
904 class VOP3DisableModFields <bit HasSrc0Mods,
907 bit HasOutputMods = 0> {
908 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
909 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
910 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
911 bits<2> omod = !if(HasOutputMods, ?, 0);
912 bits<1> clamp = !if(HasOutputMods, ?, 0);
915 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
916 VOP3Common <outs, ins, "", pattern>,
918 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
920 let isCodeGenOnly = 1;
923 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
924 VOP3Common <outs, ins, asm, []>,
926 SIMCInstr<opName#"_e64", SISubtarget.SI>;
928 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
929 VOP3Common <outs, ins, asm, []>,
931 SIMCInstr <opName#"_e64", SISubtarget.VI>;
933 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
934 VOP3Common <outs, ins, asm, []>,
936 SIMCInstr<opName#"_e64", SISubtarget.SI>;
938 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
939 VOP3Common <outs, ins, asm, []>,
941 SIMCInstr <opName#"_e64", SISubtarget.VI>;
943 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
944 string opName, int NumSrcArgs, bit HasMods = 1> {
946 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
948 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
949 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
950 !if(!eq(NumSrcArgs, 2), 0, 1),
952 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
953 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
954 !if(!eq(NumSrcArgs, 2), 0, 1),
958 // VOP3_m without source modifiers
959 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
960 string opName, int NumSrcArgs, bit HasMods = 1> {
962 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
964 let src0_modifiers = 0,
969 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
970 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
974 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
975 list<dag> pattern, string opName, bit HasMods = 1> {
977 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
979 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
980 VOP3DisableFields<0, 0, HasMods>;
982 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
983 VOP3DisableFields<0, 0, HasMods>;
986 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
987 list<dag> pattern, string opName, bit HasMods = 1> {
989 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
991 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
992 VOP3DisableFields<0, 0, HasMods>;
993 // No VI instruction. This class is for SI only.
996 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
997 list<dag> pattern, string opName, string revOp,
998 bit HasMods = 1, bit UseFullOp = 0> {
1000 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1001 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1003 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1004 VOP3DisableFields<1, 0, HasMods>;
1006 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1007 VOP3DisableFields<1, 0, HasMods>;
1010 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1011 list<dag> pattern, string opName, string revOp,
1012 bit HasMods = 1, bit UseFullOp = 0> {
1014 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1015 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1017 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1018 VOP3DisableFields<1, 0, HasMods>;
1020 // No VI instruction. This class is for SI only.
1023 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1024 // option of implicit vcc use?
1025 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
1026 list<dag> pattern, string opName, string revOp,
1027 bit HasMods = 1, bit UseFullOp = 0> {
1028 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1029 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1031 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1032 // can write it into any SGPR. We currently don't use the carry out,
1033 // so for now hardcode it to VCC as well.
1034 let sdst = SIOperand.VCC, Defs = [VCC] in {
1035 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1036 VOP3DisableFields<1, 0, HasMods>;
1038 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1039 VOP3DisableFields<1, 0, HasMods>;
1040 } // End sdst = SIOperand.VCC, Defs = [VCC]
1043 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1044 list<dag> pattern, string opName, string revOp,
1045 bit HasMods = 1, bit UseFullOp = 0> {
1046 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1049 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1050 VOP3DisableFields<1, 1, HasMods>;
1052 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1053 VOP3DisableFields<1, 1, HasMods>;
1056 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1057 list<dag> pattern, string opName,
1058 bit HasMods, bit defExec> {
1060 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1062 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1063 VOP3DisableFields<1, 0, HasMods> {
1064 let Defs = !if(defExec, [EXEC], []);
1067 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1068 VOP3DisableFields<1, 0, HasMods> {
1069 let Defs = !if(defExec, [EXEC], []);
1073 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1074 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1075 string asm, list<dag> pattern = []> {
1076 let isPseudo = 1, isCodeGenOnly = 1 in {
1077 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1078 SIMCInstr<opName, SISubtarget.NONE>;
1081 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1082 SIMCInstr <opName, SISubtarget.SI>;
1084 def _vi : VOP3Common <outs, ins, asm, []>,
1086 VOP3DisableFields <1, 0, 0>,
1087 SIMCInstr <opName, SISubtarget.VI>;
1090 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1091 dag ins32, string asm32, list<dag> pat32,
1092 dag ins64, string asm64, list<dag> pat64,
1095 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1097 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
1100 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1101 SDPatternOperator node = null_frag> : VOP1_Helper <
1103 P.Ins32, P.Asm32, [],
1106 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1107 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1108 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1112 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1113 SDPatternOperator node = null_frag> {
1115 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1117 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1119 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1120 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1121 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1122 opName, P.HasModifiers>;
1125 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1126 dag ins32, string asm32, list<dag> pat32,
1127 dag ins64, string asm64, list<dag> pat64,
1128 string revOp, bit HasMods> {
1129 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1131 defm _e64 : VOP3_2_m <op,
1132 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1136 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1137 SDPatternOperator node = null_frag,
1138 string revOp = opName> : VOP2_Helper <
1140 P.Ins32, P.Asm32, [],
1144 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1145 i1:$clamp, i32:$omod)),
1146 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1147 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1148 revOp, P.HasModifiers
1151 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1152 SDPatternOperator node = null_frag,
1153 string revOp = opName> {
1154 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1156 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#"_e64"#P.Asm64,
1159 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1160 i1:$clamp, i32:$omod)),
1161 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1162 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1163 opName, revOp, P.HasModifiers>;
1166 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1167 dag ins32, string asm32, list<dag> pat32,
1168 dag ins64, string asm64, list<dag> pat64,
1169 string revOp, bit HasMods> {
1171 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1173 defm _e64 : VOP3b_2_m <op,
1174 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1178 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1179 SDPatternOperator node = null_frag,
1180 string revOp = opName> : VOP2b_Helper <
1182 P.Ins32, P.Asm32, [],
1186 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1187 i1:$clamp, i32:$omod)),
1188 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1189 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1190 revOp, P.HasModifiers
1193 // A VOP2 instruction that is VOP3-only on VI.
1194 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1195 dag ins32, string asm32, list<dag> pat32,
1196 dag ins64, string asm64, list<dag> pat64,
1197 string revOp, bit HasMods> {
1198 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1200 defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
1204 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1205 SDPatternOperator node = null_frag,
1206 string revOp = opName>
1209 P.Ins32, P.Asm32, [],
1213 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1214 i1:$clamp, i32:$omod)),
1215 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1216 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1217 revOp, P.HasModifiers
1220 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1222 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1224 let isCodeGenOnly = 0 in {
1225 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1226 !strconcat(opName, VOP_MADK.Asm), []>,
1227 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1230 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1231 !strconcat(opName, VOP_MADK.Asm), []>,
1232 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1234 } // End isCodeGenOnly = 0
1237 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1238 VOPCCommon <ins, "", pattern>,
1240 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1242 let isCodeGenOnly = 1;
1245 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1246 string opName, bit DefExec> {
1247 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1249 def _si : VOPC<op.SI, ins, asm, []>,
1250 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1251 let Defs = !if(DefExec, [EXEC], []);
1254 def _vi : VOPC<op.VI, ins, asm, []>,
1255 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1256 let Defs = !if(DefExec, [EXEC], []);
1260 multiclass VOPC_Helper <vopc op, string opName,
1261 dag ins32, string asm32, list<dag> pat32,
1262 dag out64, dag ins64, string asm64, list<dag> pat64,
1263 bit HasMods, bit DefExec> {
1264 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1266 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1267 opName, HasMods, DefExec>;
1270 // Special case for class instructions which only have modifiers on
1271 // the 1st source operand.
1272 multiclass VOPC_Class_Helper <vopc op, string opName,
1273 dag ins32, string asm32, list<dag> pat32,
1274 dag out64, dag ins64, string asm64, list<dag> pat64,
1275 bit HasMods, bit DefExec> {
1276 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1278 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1279 opName, HasMods, DefExec>,
1280 VOP3DisableModFields<1, 0, 0>;
1283 multiclass VOPCInst <vopc op, string opName,
1284 VOPProfile P, PatLeaf cond = COND_NULL,
1285 bit DefExec = 0> : VOPC_Helper <
1287 P.Ins32, P.Asm32, [],
1288 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1291 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1292 i1:$clamp, i32:$omod)),
1293 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1295 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1296 P.HasModifiers, DefExec
1299 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1300 bit DefExec = 0> : VOPC_Class_Helper <
1302 P.Ins32, P.Asm32, [],
1303 (outs SReg_64:$dst), P.Ins64, P.Asm64,
1306 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1307 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1308 P.HasModifiers, DefExec
1312 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1313 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1315 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1316 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1318 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1319 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1321 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1322 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1325 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1326 PatLeaf cond = COND_NULL>
1327 : VOPCInst <op, opName, P, cond, 1>;
1329 multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1330 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1332 multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1333 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1335 multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1336 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1338 multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1339 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1341 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1342 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1343 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
1346 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1347 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1349 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1350 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1352 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1353 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1355 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1356 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1358 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1359 SDPatternOperator node = null_frag> : VOP3_Helper <
1360 op, opName, P.Outs, P.Ins64, P.Asm64,
1361 !if(!eq(P.NumSrcArgs, 3),
1364 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1365 i1:$clamp, i32:$omod)),
1366 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1367 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1368 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1370 !if(!eq(P.NumSrcArgs, 2),
1373 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1374 i1:$clamp, i32:$omod)),
1375 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1376 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1377 /* P.NumSrcArgs == 1 */,
1380 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1381 i1:$clamp, i32:$omod))))],
1382 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1383 P.NumSrcArgs, P.HasModifiers
1386 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1387 // only VOP instruction that implicitly reads VCC.
1388 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1390 SDPatternOperator node = null_frag> : VOP3_Helper <
1393 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1394 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1395 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1398 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1400 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1401 i1:$clamp, i32:$omod)),
1402 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1403 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1408 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1409 string opName, list<dag> pattern> :
1411 op, (outs vrc:$vdst, SReg_64:$sdst),
1412 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1413 InputModsNoDefault:$src1_modifiers, arc:$src1,
1414 InputModsNoDefault:$src2_modifiers, arc:$src2,
1415 ClampMod:$clamp, omod:$omod),
1416 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1417 opName, opName, 1, 1
1420 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1421 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1423 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1424 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1427 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1428 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1429 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1430 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1431 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1432 i32:$src1_modifiers, P.Src1VT:$src1,
1433 i32:$src2_modifiers, P.Src2VT:$src2,
1437 //===----------------------------------------------------------------------===//
1438 // Interpolation opcodes
1439 //===----------------------------------------------------------------------===//
1441 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1442 VINTRPCommon <outs, ins, "", pattern>,
1443 SIMCInstr<opName, SISubtarget.NONE> {
1445 let isCodeGenOnly = 1;
1448 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1450 VINTRPCommon <outs, ins, asm, []>,
1452 SIMCInstr<opName, SISubtarget.SI>;
1454 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1456 VINTRPCommon <outs, ins, asm, []>,
1458 SIMCInstr<opName, SISubtarget.VI>;
1460 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1461 string disableEncoding = "", string constraints = "",
1462 list<dag> pattern = []> {
1463 let DisableEncoding = disableEncoding,
1464 Constraints = constraints in {
1465 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1467 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1469 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1473 //===----------------------------------------------------------------------===//
1474 // Vector I/O classes
1475 //===----------------------------------------------------------------------===//
1477 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1478 DS <outs, ins, "", pattern>,
1479 SIMCInstr <opName, SISubtarget.NONE> {
1481 let isCodeGenOnly = 1;
1484 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1485 DS <outs, ins, asm, []>,
1487 SIMCInstr <opName, SISubtarget.SI>;
1489 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1490 DS <outs, ins, asm, []>,
1492 SIMCInstr <opName, SISubtarget.VI>;
1494 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1495 DS_Real_si <op,opName, outs, ins, asm> {
1497 // Single load interpret the 2 i8imm operands as a single i16 offset.
1499 let offset0 = offset{7-0};
1500 let offset1 = offset{15-8};
1503 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1504 DS_Real_vi <op, opName, outs, ins, asm> {
1506 // Single load interpret the 2 i8imm operands as a single i16 offset.
1508 let offset0 = offset{7-0};
1509 let offset1 = offset{15-8};
1512 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
1513 dag outs = (outs rc:$vdst),
1514 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds, M0Reg:$m0),
1515 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
1517 def "" : DS_Pseudo <opName, outs, ins, []>;
1519 let data0 = 0, data1 = 0 in {
1520 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1521 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1525 multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
1526 dag outs = (outs rc:$vdst),
1527 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1528 gds:$gds, M0Reg:$m0),
1529 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
1531 def "" : DS_Pseudo <opName, outs, ins, []>;
1533 let data0 = 0, data1 = 0 in {
1534 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1535 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1539 multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
1541 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds,
1543 string asm = opName#" $addr, $data0"#"$offset$gds"> {
1545 def "" : DS_Pseudo <opName, outs, ins, []>,
1546 AtomicNoRet<opName, 0>;
1548 let data1 = 0, vdst = 0 in {
1549 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1550 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1554 multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
1556 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1557 ds_offset0:$offset0, ds_offset1:$offset1, gds:$gds, M0Reg:$m0),
1558 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
1560 def "" : DS_Pseudo <opName, outs, ins, []>;
1563 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1564 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1568 multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
1569 string noRetOp = "",
1570 dag outs = (outs rc:$vdst),
1571 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds,
1573 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
1575 def "" : DS_Pseudo <opName, outs, ins, []>,
1576 AtomicNoRet<noRetOp, 1>;
1579 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1580 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1584 multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
1585 string noRetOp = "", dag ins,
1586 dag outs = (outs rc:$vdst),
1587 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
1589 def "" : DS_Pseudo <opName, outs, ins, []>,
1590 AtomicNoRet<noRetOp, 1>;
1592 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1593 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1596 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1597 string noRetOp = "", RegisterClass src = rc> :
1598 DS_1A2D_RET_m <op, asm, rc, noRetOp,
1599 (ins VGPR_32:$addr, src:$data0, src:$data1,
1600 ds_offset:$offset, gds:$gds, M0Reg:$m0)
1603 multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
1604 string noRetOp = opName,
1606 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1607 ds_offset:$offset, gds:$gds, M0Reg:$m0),
1608 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
1610 def "" : DS_Pseudo <opName, outs, ins, []>,
1611 AtomicNoRet<noRetOp, 0>;
1614 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1615 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1619 multiclass DS_0A_RET <bits<8> op, string opName,
1620 dag outs = (outs VGPR_32:$vdst),
1621 dag ins = (ins ds_offset:$offset, gds:$gds, M0Reg:$m0),
1622 string asm = opName#" $vdst"#"$offset"#"$gds"> {
1624 let mayLoad = 1, mayStore = 1 in {
1625 def "" : DS_Pseudo <opName, outs, ins, []>;
1627 let addr = 0, data0 = 0, data1 = 0 in {
1628 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1629 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1630 } // end addr = 0, data0 = 0, data1 = 0
1631 } // end mayLoad = 1, mayStore = 1
1634 multiclass DS_1A_RET_GDS <bits<8> op, string opName,
1635 dag outs = (outs VGPR_32:$vdst),
1636 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1637 string asm = opName#" $vdst, $addr"#"$offset gds"> {
1639 def "" : DS_Pseudo <opName, outs, ins, []>;
1641 let data0 = 0, data1 = 0, gds = 1 in {
1642 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1643 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1644 } // end data0 = 0, data1 = 0, gds = 1
1647 multiclass DS_1A_GDS <bits<8> op, string opName,
1649 dag ins = (ins VGPR_32:$addr, M0Reg:$m0),
1650 string asm = opName#" $addr gds"> {
1652 def "" : DS_Pseudo <opName, outs, ins, []>;
1654 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
1655 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1656 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1657 } // end vdst = 0, data = 0, data1 = 0, gds = 1
1660 multiclass DS_1A <bits<8> op, string opName,
1662 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0, gds:$gds),
1663 string asm = opName#" $addr"#"$offset"#"$gds"> {
1665 let mayLoad = 1, mayStore = 1 in {
1666 def "" : DS_Pseudo <opName, outs, ins, []>;
1668 let vdst = 0, data0 = 0, data1 = 0 in {
1669 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1670 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1671 } // let vdst = 0, data0 = 0, data1 = 0
1672 } // end mayLoad = 1, mayStore = 1
1675 //===----------------------------------------------------------------------===//
1677 //===----------------------------------------------------------------------===//
1679 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1680 MTBUF <outs, ins, "", pattern>,
1681 SIMCInstr<opName, SISubtarget.NONE> {
1683 let isCodeGenOnly = 1;
1686 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1688 MTBUF <outs, ins, asm, []>,
1690 SIMCInstr<opName, SISubtarget.SI>;
1692 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1693 MTBUF <outs, ins, asm, []>,
1695 SIMCInstr <opName, SISubtarget.VI>;
1697 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1698 list<dag> pattern> {
1700 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1702 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1704 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1708 let mayStore = 1, mayLoad = 0 in {
1710 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1711 RegisterClass regClass> : MTBUF_m <
1713 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1714 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1715 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1716 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1717 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1720 } // mayStore = 1, mayLoad = 0
1722 let mayLoad = 1, mayStore = 0 in {
1724 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1725 RegisterClass regClass> : MTBUF_m <
1726 op, opName, (outs regClass:$dst),
1727 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1728 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1729 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1730 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1731 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1734 } // mayLoad = 1, mayStore = 0
1736 //===----------------------------------------------------------------------===//
1738 //===----------------------------------------------------------------------===//
1740 class mubuf <bits<7> si, bits<7> vi = si> {
1741 field bits<7> SI = si;
1742 field bits<7> VI = vi;
1745 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1746 bit IsAddr64 = is_addr64;
1747 string OpName = NAME # suffix;
1750 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1751 MUBUF <outs, ins, "", pattern>,
1752 SIMCInstr<opName, SISubtarget.NONE> {
1754 let isCodeGenOnly = 1;
1756 // dummy fields, so that we can use let statements around multiclasses
1766 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1768 MUBUF <outs, ins, asm, []>,
1770 SIMCInstr<opName, SISubtarget.SI> {
1774 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
1776 MUBUF <outs, ins, asm, []>,
1778 SIMCInstr<opName, SISubtarget.VI> {
1782 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
1783 list<dag> pattern> {
1785 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1786 MUBUFAddr64Table <0>;
1789 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1792 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1795 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
1796 dag ins, string asm, list<dag> pattern> {
1798 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1799 MUBUFAddr64Table <1>;
1802 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1805 // There is no VI version. If the pseudo is selected, it should be lowered
1806 // for VI appropriately.
1809 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1810 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1814 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
1815 string asm, list<dag> pattern, bit is_return> {
1817 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1818 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
1819 AtomicNoRet<NAME#"_OFFSET", is_return>;
1821 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
1823 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1826 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1830 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
1831 string asm, list<dag> pattern, bit is_return> {
1833 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1834 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
1835 AtomicNoRet<NAME#"_ADDR64", is_return>;
1837 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
1838 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1841 // There is no VI version. If the pseudo is selected, it should be lowered
1842 // for VI appropriately.
1845 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
1846 ValueType vt, SDPatternOperator atomic> {
1848 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1850 // No return variants
1853 defm _ADDR64 : MUBUFAtomicAddr64_m <
1854 op, name#"_addr64", (outs),
1855 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1856 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
1857 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
1860 defm _OFFSET : MUBUFAtomicOffset_m <
1861 op, name#"_offset", (outs),
1862 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
1864 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
1868 // Variant that return values
1869 let glc = 1, Constraints = "$vdata = $vdata_in",
1870 DisableEncoding = "$vdata_in" in {
1872 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
1873 op, name#"_rtn_addr64", (outs rc:$vdata),
1874 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1875 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
1876 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
1878 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
1879 i16:$offset, i1:$slc), vt:$vdata_in))], 1
1882 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
1883 op, name#"_rtn_offset", (outs rc:$vdata),
1884 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
1885 mbuf_offset:$offset, slc:$slc),
1886 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1888 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1889 i1:$slc), vt:$vdata_in))], 1
1894 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1897 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
1898 ValueType load_vt = i32,
1899 SDPatternOperator ld = null_frag> {
1901 let mayLoad = 1, mayStore = 0 in {
1902 let offen = 0, idxen = 0, vaddr = 0 in {
1903 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
1904 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
1905 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1906 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1907 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1908 i32:$soffset, i16:$offset,
1909 i1:$glc, i1:$slc, i1:$tfe)))]>;
1912 let offen = 1, idxen = 0 in {
1913 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
1914 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1915 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1917 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1920 let offen = 0, idxen = 1 in {
1921 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
1922 (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1923 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
1924 slc:$slc, tfe:$tfe),
1925 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1928 let offen = 1, idxen = 1 in {
1929 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
1930 (ins SReg_128:$srsrc, VReg_64:$vaddr, SCSrc_32:$soffset,
1931 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1932 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1935 let offen = 0, idxen = 0 in {
1936 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
1937 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1938 SCSrc_32:$soffset, mbuf_offset:$offset,
1939 glc:$glc, slc:$slc, tfe:$tfe),
1940 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
1941 "$glc"#"$slc"#"$tfe",
1942 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1943 i64:$vaddr, i32:$soffset,
1944 i16:$offset, i1:$glc, i1:$slc,
1950 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
1951 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
1952 let mayLoad = 0, mayStore = 1 in {
1953 defm : MUBUF_m <op, name, (outs),
1954 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1955 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1957 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1958 "$glc"#"$slc"#"$tfe", []>;
1960 let offen = 0, idxen = 0, vaddr = 0 in {
1961 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
1962 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
1963 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1964 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1965 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1966 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
1967 } // offen = 0, idxen = 0, vaddr = 0
1969 let offen = 1, idxen = 0 in {
1970 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
1971 (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr,
1972 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
1973 slc:$slc, tfe:$tfe),
1974 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1975 "$glc"#"$slc"#"$tfe", []>;
1976 } // end offen = 1, idxen = 0
1978 let offen = 0, idxen = 0 in {
1979 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
1980 (ins vdataClass:$vdata, SReg_128:$srsrc,
1981 VReg_64:$vaddr, SCSrc_32:$soffset,
1982 mbuf_offset:$offset, glc:$glc, slc:$slc,
1984 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
1985 "$offset"#"$glc"#"$slc"#"$tfe",
1986 [(st store_vt:$vdata,
1987 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
1988 i32:$soffset, i16:$offset,
1989 i1:$glc, i1:$slc, i1:$tfe))]>;
1991 } // End mayLoad = 0, mayStore = 1
1994 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1995 FLAT <op, (outs regClass:$vdst),
1996 (ins VReg_64:$addr),
1997 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
2005 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
2006 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
2007 name#" $data, $addr, [M0, FLAT_SCRATCH]",
2020 class MIMG_Mask <string op, int channels> {
2022 int Channels = channels;
2025 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2026 RegisterClass dst_rc,
2027 RegisterClass src_rc> : MIMG <
2029 (outs dst_rc:$vdata),
2030 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2031 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2033 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2034 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2039 let hasPostISelHook = 1;
2042 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2043 RegisterClass dst_rc,
2045 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2046 MIMG_Mask<asm#"_V1", channels>;
2047 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2048 MIMG_Mask<asm#"_V2", channels>;
2049 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2050 MIMG_Mask<asm#"_V4", channels>;
2053 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2054 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2055 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2056 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2057 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2060 class MIMG_Sampler_Helper <bits<7> op, string asm,
2061 RegisterClass dst_rc,
2062 RegisterClass src_rc, int wqm> : MIMG <
2064 (outs dst_rc:$vdata),
2065 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2066 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2067 SReg_256:$srsrc, SReg_128:$ssamp),
2068 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2069 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2073 let hasPostISelHook = 1;
2077 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2078 RegisterClass dst_rc,
2079 int channels, int wqm> {
2080 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2081 MIMG_Mask<asm#"_V1", channels>;
2082 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2083 MIMG_Mask<asm#"_V2", channels>;
2084 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2085 MIMG_Mask<asm#"_V4", channels>;
2086 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2087 MIMG_Mask<asm#"_V8", channels>;
2088 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2089 MIMG_Mask<asm#"_V16", channels>;
2092 multiclass MIMG_Sampler <bits<7> op, string asm> {
2093 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2094 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2095 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2096 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2099 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2100 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2101 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2102 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2103 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2106 class MIMG_Gather_Helper <bits<7> op, string asm,
2107 RegisterClass dst_rc,
2108 RegisterClass src_rc, int wqm> : MIMG <
2110 (outs dst_rc:$vdata),
2111 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2112 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2113 SReg_256:$srsrc, SReg_128:$ssamp),
2114 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2115 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2120 // DMASK was repurposed for GATHER4. 4 components are always
2121 // returned and DMASK works like a swizzle - it selects
2122 // the component to fetch. The only useful DMASK values are
2123 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2124 // (red,red,red,red) etc.) The ISA document doesn't mention
2126 // Therefore, disable all code which updates DMASK by setting these two:
2128 let hasPostISelHook = 0;
2132 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2133 RegisterClass dst_rc,
2134 int channels, int wqm> {
2135 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2136 MIMG_Mask<asm#"_V1", channels>;
2137 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2138 MIMG_Mask<asm#"_V2", channels>;
2139 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2140 MIMG_Mask<asm#"_V4", channels>;
2141 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2142 MIMG_Mask<asm#"_V8", channels>;
2143 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2144 MIMG_Mask<asm#"_V16", channels>;
2147 multiclass MIMG_Gather <bits<7> op, string asm> {
2148 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2149 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2150 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2151 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2154 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2155 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2156 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2157 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2158 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2161 //===----------------------------------------------------------------------===//
2162 // Vector instruction mappings
2163 //===----------------------------------------------------------------------===//
2165 // Maps an opcode in e32 form to its e64 equivalent
2166 def getVOPe64 : InstrMapping {
2167 let FilterClass = "VOP";
2168 let RowFields = ["OpName"];
2169 let ColFields = ["Size"];
2171 let ValueCols = [["8"]];
2174 // Maps an opcode in e64 form to its e32 equivalent
2175 def getVOPe32 : InstrMapping {
2176 let FilterClass = "VOP";
2177 let RowFields = ["OpName"];
2178 let ColFields = ["Size"];
2180 let ValueCols = [["4"]];
2183 // Maps an original opcode to its commuted version
2184 def getCommuteRev : InstrMapping {
2185 let FilterClass = "VOP2_REV";
2186 let RowFields = ["RevOp"];
2187 let ColFields = ["IsOrig"];
2189 let ValueCols = [["0"]];
2192 def getMaskedMIMGOp : InstrMapping {
2193 let FilterClass = "MIMG_Mask";
2194 let RowFields = ["Op"];
2195 let ColFields = ["Channels"];
2197 let ValueCols = [["1"], ["2"], ["3"] ];
2200 // Maps an commuted opcode to its original version
2201 def getCommuteOrig : InstrMapping {
2202 let FilterClass = "VOP2_REV";
2203 let RowFields = ["RevOp"];
2204 let ColFields = ["IsOrig"];
2206 let ValueCols = [["1"]];
2209 def getMCOpcodeGen : InstrMapping {
2210 let FilterClass = "SIMCInstr";
2211 let RowFields = ["PseudoInstr"];
2212 let ColFields = ["Subtarget"];
2213 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2214 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2217 def getAddr64Inst : InstrMapping {
2218 let FilterClass = "MUBUFAddr64Table";
2219 let RowFields = ["OpName"];
2220 let ColFields = ["IsAddr64"];
2222 let ValueCols = [["1"]];
2225 // Maps an atomic opcode to its version with a return value.
2226 def getAtomicRetOp : InstrMapping {
2227 let FilterClass = "AtomicNoRet";
2228 let RowFields = ["NoRetOp"];
2229 let ColFields = ["IsRet"];
2231 let ValueCols = [["1"]];
2234 // Maps an atomic opcode to its returnless version.
2235 def getAtomicNoRetOp : InstrMapping {
2236 let FilterClass = "AtomicNoRet";
2237 let RowFields = ["NoRetOp"];
2238 let ColFields = ["IsRet"];
2240 let ValueCols = [["0"]];
2243 include "SIInstructions.td"
2244 include "CIInstructions.td"
2245 include "VIInstructions.td"