1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
15 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16 field bits<8> SI = si;
17 field bits<8> VI = vi;
19 field bits<9> SI3 = {0, si{7-0}};
20 field bits<10> VI3 = {0, 0, vi{7-0}};
23 class vop1 <bits<8> si, bits<8> vi = si> : vop {
24 field bits<8> SI = si;
25 field bits<8> VI = vi;
27 field bits<9> SI3 = {1, 1, si{6-0}};
28 field bits<10> VI3 = !add(0x140, vi);
31 class vop2 <bits<6> si, bits<6> vi = si> : vop {
32 field bits<6> SI = si;
33 field bits<6> VI = vi;
35 field bits<9> SI3 = {1, 0, 0, si{5-0}};
36 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
39 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
40 // that doesn't have VOP2 encoding on VI
41 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
45 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
50 class sop1 <bits<8> si, bits<8> vi = si> {
51 field bits<8> SI = si;
52 field bits<8> VI = vi;
55 class sop2 <bits<7> si, bits<7> vi = si> {
56 field bits<7> SI = si;
57 field bits<7> VI = vi;
60 class sopk <bits<5> si, bits<5> vi = si> {
61 field bits<5> SI = si;
62 field bits<5> VI = vi;
65 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66 // in AMDGPUInstrInfo.cpp
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79 [SDNPMayLoad, SDNPMemOperand]
82 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
84 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
85 SDTCisVT<1, iAny>, // vdata(VGPR)
86 SDTCisVT<2, i32>, // num_channels(imm)
87 SDTCisVT<3, i32>, // vaddr(VGPR)
88 SDTCisVT<4, i32>, // soffset(SGPR)
89 SDTCisVT<5, i32>, // inst_offset(imm)
90 SDTCisVT<6, i32>, // dfmt(imm)
91 SDTCisVT<7, i32>, // nfmt(imm)
92 SDTCisVT<8, i32>, // offen(imm)
93 SDTCisVT<9, i32>, // idxen(imm)
94 SDTCisVT<10, i32>, // glc(imm)
95 SDTCisVT<11, i32>, // slc(imm)
96 SDTCisVT<12, i32> // tfe(imm)
98 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
101 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
106 class SDSample<string opcode> : SDNode <opcode,
107 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
111 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
116 def SIconstdata_ptr : SDNode<
117 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
120 // Transformation function, extract the lower 32bit of a 64bit immediate
121 def LO32 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
125 def LO32f : SDNodeXForm<fpimm, [{
126 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
130 // Transformation function, extract the upper 32bit of a 64bit immediate
131 def HI32 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
135 def HI32f : SDNodeXForm<fpimm, [{
136 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
140 def IMM8bitDWORD : PatLeaf <(imm),
141 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
144 def as_dword_i32imm : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
148 def as_i1imm : SDNodeXForm<imm, [{
149 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
152 def as_i8imm : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
156 def as_i16imm : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
160 def as_i32imm: SDNodeXForm<imm, [{
161 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
164 def as_i64imm: SDNodeXForm<imm, [{
165 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
168 // Copied from the AArch64 backend:
169 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170 return CurDAG->getTargetConstant(
171 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
174 // Copied from the AArch64 backend:
175 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176 return CurDAG->getTargetConstant(
177 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
180 def IMM8bit : PatLeaf <(imm),
181 [{return isUInt<8>(N->getZExtValue());}]
184 def IMM12bit : PatLeaf <(imm),
185 [{return isUInt<12>(N->getZExtValue());}]
188 def IMM16bit : PatLeaf <(imm),
189 [{return isUInt<16>(N->getZExtValue());}]
192 def IMM20bit : PatLeaf <(imm),
193 [{return isUInt<20>(N->getZExtValue());}]
196 def IMM32bit : PatLeaf <(imm),
197 [{return isUInt<32>(N->getZExtValue());}]
200 def mubuf_vaddr_offset : PatFrag<
201 (ops node:$ptr, node:$offset, node:$imm_offset),
202 (add (add node:$ptr, node:$offset), node:$imm_offset)
205 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206 return isInlineImmediate(N);
209 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210 return isInlineImmediate(N);
213 class SGPRImm <dag frag> : PatLeaf<frag, [{
214 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
217 const SIRegisterInfo *SIRI =
218 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
219 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
221 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
228 //===----------------------------------------------------------------------===//
230 //===----------------------------------------------------------------------===//
232 def FRAMEri32 : Operand<iPTR> {
233 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
236 def sopp_brtarget : Operand<OtherVT> {
237 let EncoderMethod = "getSOPPBrEncoding";
238 let OperandType = "OPERAND_PCREL";
241 include "SIInstrFormats.td"
242 include "VIInstrFormats.td"
244 let OperandType = "OPERAND_IMMEDIATE" in {
246 def offen : Operand<i1> {
247 let PrintMethod = "printOffen";
249 def idxen : Operand<i1> {
250 let PrintMethod = "printIdxen";
252 def addr64 : Operand<i1> {
253 let PrintMethod = "printAddr64";
255 def mbuf_offset : Operand<i16> {
256 let PrintMethod = "printMBUFOffset";
258 def ds_offset : Operand<i16> {
259 let PrintMethod = "printDSOffset";
261 def ds_offset0 : Operand<i8> {
262 let PrintMethod = "printDSOffset0";
264 def ds_offset1 : Operand<i8> {
265 let PrintMethod = "printDSOffset1";
267 def gds : Operand <i1> {
268 let PrintMethod = "printGDS";
270 def glc : Operand <i1> {
271 let PrintMethod = "printGLC";
273 def slc : Operand <i1> {
274 let PrintMethod = "printSLC";
276 def tfe : Operand <i1> {
277 let PrintMethod = "printTFE";
280 def omod : Operand <i32> {
281 let PrintMethod = "printOModSI";
284 def ClampMod : Operand <i1> {
285 let PrintMethod = "printClampSI";
288 } // End OperandType = "OPERAND_IMMEDIATE"
290 def VOPDstS64 : VOPDstOperand <SReg_64>;
292 //===----------------------------------------------------------------------===//
294 //===----------------------------------------------------------------------===//
296 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
297 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
299 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
300 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
301 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
302 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
303 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
304 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
306 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
307 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
308 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
309 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
311 //===----------------------------------------------------------------------===//
312 // SI assembler operands
313 //===----------------------------------------------------------------------===//
333 //===----------------------------------------------------------------------===//
335 // SI Instruction multiclass helpers.
337 // Instructions with _32 take 32-bit operands.
338 // Instructions with _64 take 64-bit operands.
340 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
341 // encoding is the standard encoding, but instruction that make use of
342 // any of the instruction modifiers must use the 64-bit encoding.
344 // Instructions with _e32 use the 32-bit encoding.
345 // Instructions with _e64 use the 64-bit encoding.
347 //===----------------------------------------------------------------------===//
349 class SIMCInstr <string pseudo, int subtarget> {
350 string PseudoInstr = pseudo;
351 int Subtarget = subtarget;
354 //===----------------------------------------------------------------------===//
356 //===----------------------------------------------------------------------===//
358 class EXPCommon : InstSI<
360 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
361 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
362 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
371 let isPseudo = 1, isCodeGenOnly = 1 in {
372 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
375 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
377 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
380 //===----------------------------------------------------------------------===//
382 //===----------------------------------------------------------------------===//
384 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
385 SOP1 <outs, ins, "", pattern>,
386 SIMCInstr<opName, SISubtarget.NONE> {
388 let isCodeGenOnly = 1;
391 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
392 SOP1 <outs, ins, asm, []>,
394 SIMCInstr<opName, SISubtarget.SI>;
396 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
397 SOP1 <outs, ins, asm, []>,
399 SIMCInstr<opName, SISubtarget.VI>;
401 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
404 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
406 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
408 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
412 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
413 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
414 opName#" $dst, $src0", pattern
417 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
418 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
419 opName#" $dst, $src0", pattern
422 // no input, 64-bit output.
423 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
424 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
426 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
431 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
437 // 64-bit input, no output
438 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
439 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
441 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
446 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
452 // 64-bit input, 32-bit output.
453 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
454 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
455 opName#" $dst, $src0", pattern
458 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
459 SOP2<outs, ins, "", pattern>,
460 SIMCInstr<opName, SISubtarget.NONE> {
462 let isCodeGenOnly = 1;
465 // Pseudo instructions have no encodings, but adding this field here allows
467 // let sdst = xxx in {
468 // for multiclasses that include both real and pseudo instructions.
469 field bits<7> sdst = 0;
472 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
473 SOP2<outs, ins, asm, []>,
475 SIMCInstr<opName, SISubtarget.SI>;
477 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
478 SOP2<outs, ins, asm, []>,
480 SIMCInstr<opName, SISubtarget.VI>;
482 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
483 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
484 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
486 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
487 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
488 opName#" $dst, $src0, $src1 [$scc]">;
490 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
491 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
492 opName#" $dst, $src0, $src1 [$scc]">;
495 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
498 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
500 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
502 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
506 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
507 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
508 opName#" $dst, $src0, $src1", pattern
511 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
512 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
513 opName#" $dst, $src0, $src1", pattern
516 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
517 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
518 opName#" $dst, $src0, $src1", pattern
521 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
522 string opName, PatLeaf cond> : SOPC <
523 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
524 opName#" $src0, $src1", []>;
526 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
527 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
529 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
530 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
532 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
533 SOPK <outs, ins, "", pattern>,
534 SIMCInstr<opName, SISubtarget.NONE> {
536 let isCodeGenOnly = 1;
539 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
540 SOPK <outs, ins, asm, []>,
542 SIMCInstr<opName, SISubtarget.SI>;
544 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
545 SOPK <outs, ins, asm, []>,
547 SIMCInstr<opName, SISubtarget.VI>;
549 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
550 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
553 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
554 opName#" $dst, $src0">;
556 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
557 opName#" $dst, $src0">;
560 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
561 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
562 (ins SReg_32:$src0, u16imm:$src1), pattern>;
564 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
565 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
567 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
568 (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
571 //===----------------------------------------------------------------------===//
573 //===----------------------------------------------------------------------===//
575 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
576 SMRD <outs, ins, "", pattern>,
577 SIMCInstr<opName, SISubtarget.NONE> {
579 let isCodeGenOnly = 1;
582 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
584 SMRD <outs, ins, asm, []>,
586 SIMCInstr<opName, SISubtarget.SI>;
588 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
590 SMRD <outs, ins, asm, []>,
592 SIMCInstr<opName, SISubtarget.VI>;
594 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
595 string asm, list<dag> pattern> {
597 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
599 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
601 // glc is only applicable to scalar stores, which are not yet
604 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
608 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
609 RegisterClass dstClass> {
611 op, opName#"_IMM", 1, (outs dstClass:$dst),
612 (ins baseClass:$sbase, u32imm:$offset),
613 opName#" $dst, $sbase, $offset", []
616 defm _SGPR : SMRD_m <
617 op, opName#"_SGPR", 0, (outs dstClass:$dst),
618 (ins baseClass:$sbase, SReg_32:$soff),
619 opName#" $dst, $sbase, $soff", []
623 //===----------------------------------------------------------------------===//
624 // Vector ALU classes
625 //===----------------------------------------------------------------------===//
627 // This must always be right before the operand being input modified.
628 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
629 let PrintMethod = "printOperandAndMods";
631 def InputModsNoDefault : Operand <i32> {
632 let PrintMethod = "printOperandAndMods";
635 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
637 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
638 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
642 // Returns the register class to use for the destination of VOP[123C]
643 // instructions for the given VT.
644 class getVALUDstForVT<ValueType VT> {
645 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
646 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
647 VOPDstOperand<SReg_64>)); // else VT == i1
650 // Returns the register class to use for source 0 of VOP[12C]
651 // instructions for the given VT.
652 class getVOPSrc0ForVT<ValueType VT> {
653 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
656 // Returns the register class to use for source 1 of VOP[12C] for the
658 class getVOPSrc1ForVT<ValueType VT> {
659 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
662 // Returns the register class to use for sources of VOP3 instructions for the
664 class getVOP3SrcForVT<ValueType VT> {
665 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
668 // Returns 1 if the source arguments have modifiers, 0 if they do not.
669 class hasModifiers<ValueType SrcVT> {
670 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
671 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
674 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
675 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
676 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
677 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
681 // Returns the input arguments for VOP3 instructions for the given SrcVT.
682 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
683 RegisterOperand Src2RC, int NumSrcArgs,
687 !if (!eq(NumSrcArgs, 1),
688 !if (!eq(HasModifiers, 1),
689 // VOP1 with modifiers
690 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
691 ClampMod:$clamp, omod:$omod)
693 // VOP1 without modifiers
696 !if (!eq(NumSrcArgs, 2),
697 !if (!eq(HasModifiers, 1),
698 // VOP 2 with modifiers
699 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
700 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
701 ClampMod:$clamp, omod:$omod)
703 // VOP2 without modifiers
704 (ins Src0RC:$src0, Src1RC:$src1)
706 /* NumSrcArgs == 3 */,
707 !if (!eq(HasModifiers, 1),
708 // VOP3 with modifiers
709 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
710 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
711 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
712 ClampMod:$clamp, omod:$omod)
714 // VOP3 without modifiers
715 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
719 // Returns the assembly string for the inputs and outputs of a VOP[12C]
720 // instruction. This does not add the _e32 suffix, so it can be reused
722 class getAsm32 <int NumSrcArgs> {
723 string src1 = ", $src1";
724 string src2 = ", $src2";
725 string ret = "$dst, $src0"#
726 !if(!eq(NumSrcArgs, 1), "", src1)#
727 !if(!eq(NumSrcArgs, 3), src2, "");
730 // Returns the assembly string for the inputs and outputs of a VOP3
732 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
733 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
734 string src1 = !if(!eq(NumSrcArgs, 1), "",
735 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
736 " $src1_modifiers,"));
737 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
739 !if(!eq(HasModifiers, 0),
740 getAsm32<NumSrcArgs>.ret,
741 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
745 class VOPProfile <list<ValueType> _ArgVT> {
747 field list<ValueType> ArgVT = _ArgVT;
749 field ValueType DstVT = ArgVT[0];
750 field ValueType Src0VT = ArgVT[1];
751 field ValueType Src1VT = ArgVT[2];
752 field ValueType Src2VT = ArgVT[3];
753 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
754 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
755 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
756 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
757 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
758 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
760 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
761 field bit HasModifiers = hasModifiers<Src0VT>.ret;
763 field dag Outs = (outs DstRC:$dst);
765 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
766 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
769 field string Asm32 = getAsm32<NumSrcArgs>.ret;
770 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
773 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
774 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
775 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
776 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
777 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
778 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
779 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
780 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
781 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
783 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
784 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
785 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
786 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
787 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
788 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
789 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
790 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
791 let Src0RC32 = VCSrc_32;
794 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
795 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
796 let Asm64 = "$dst, $src0_modifiers, $src1";
799 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
800 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
801 let Asm64 = "$dst, $src0_modifiers, $src1";
804 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
805 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
806 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
807 def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
808 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2);
809 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
810 let Asm64 = "$dst, $src0, $src1, $src2";
813 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
814 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
815 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
816 field string Asm = "$dst, $src0, $vsrc1, $src2";
818 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
819 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
820 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
823 class VOP <string opName> {
824 string OpName = opName;
827 class VOP2_REV <string revOp, bit isOrig> {
828 string RevOp = revOp;
832 class VOPC_REV <string revOp, bit isOrig> {
833 string RevOp = revOp;
837 class AtomicNoRet <string noRetOp, bit isRet> {
838 string NoRetOp = noRetOp;
842 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
843 VOP1Common <outs, ins, "", pattern>,
845 SIMCInstr <opName#"_e32", SISubtarget.NONE> {
847 let isCodeGenOnly = 1;
853 class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
854 VOP1<op.SI, outs, ins, asm, []>,
855 SIMCInstr <opName#"_e32", SISubtarget.SI>;
857 class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
858 VOP1<op.VI, outs, ins, asm, []>,
859 SIMCInstr <opName#"_e32", SISubtarget.VI>;
861 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
863 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
865 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
867 def _vi : VOP1_Real_vi <opName, op, outs, ins, asm>;
870 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
872 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
874 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
877 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
878 VOP2Common <outs, ins, "", pattern>,
880 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
882 let isCodeGenOnly = 1;
885 class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> :
886 VOP2 <op.SI, outs, ins, opName#asm, []>,
887 SIMCInstr <opName#"_e32", SISubtarget.SI>;
889 class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :
890 VOP2 <op.SI, outs, ins, opName#asm, []>,
891 SIMCInstr <opName#"_e32", SISubtarget.VI>;
893 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
894 string opName, string revOp> {
895 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
896 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
898 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
901 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
902 string opName, string revOp> {
903 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
904 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
906 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
908 def _vi : VOP2_Real_vi <opName, op, outs, ins, asm>;
912 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
914 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
915 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
916 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
917 bits<2> omod = !if(HasModifiers, ?, 0);
918 bits<1> clamp = !if(HasModifiers, ?, 0);
919 bits<9> src1 = !if(HasSrc1, ?, 0);
920 bits<9> src2 = !if(HasSrc2, ?, 0);
923 class VOP3DisableModFields <bit HasSrc0Mods,
926 bit HasOutputMods = 0> {
927 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
928 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
929 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
930 bits<2> omod = !if(HasOutputMods, ?, 0);
931 bits<1> clamp = !if(HasOutputMods, ?, 0);
934 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
935 VOP3Common <outs, ins, "", pattern>,
937 SIMCInstr<opName#"_e64", SISubtarget.NONE> {
939 let isCodeGenOnly = 1;
942 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
943 VOP3Common <outs, ins, asm, []>,
945 SIMCInstr<opName#"_e64", SISubtarget.SI>;
947 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
948 VOP3Common <outs, ins, asm, []>,
950 SIMCInstr <opName#"_e64", SISubtarget.VI>;
952 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
953 VOP3Common <outs, ins, asm, []>,
955 SIMCInstr<opName#"_e64", SISubtarget.SI>;
957 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
958 VOP3Common <outs, ins, asm, []>,
960 SIMCInstr <opName#"_e64", SISubtarget.VI>;
962 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
963 string opName, int NumSrcArgs, bit HasMods = 1> {
965 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
967 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
968 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
969 !if(!eq(NumSrcArgs, 2), 0, 1),
971 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
972 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
973 !if(!eq(NumSrcArgs, 2), 0, 1),
977 // VOP3_m without source modifiers
978 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
979 string opName, int NumSrcArgs, bit HasMods = 1> {
981 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
983 let src0_modifiers = 0,
988 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
989 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
993 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
994 list<dag> pattern, string opName, bit HasMods = 1> {
996 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
998 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
999 VOP3DisableFields<0, 0, HasMods>;
1001 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1002 VOP3DisableFields<0, 0, HasMods>;
1005 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
1006 list<dag> pattern, string opName, bit HasMods = 1> {
1008 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1010 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1011 VOP3DisableFields<0, 0, HasMods>;
1012 // No VI instruction. This class is for SI only.
1015 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
1016 list<dag> pattern, string opName, string revOp,
1017 bit HasMods = 1, bit UseFullOp = 0> {
1019 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1020 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1022 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1023 VOP3DisableFields<1, 0, HasMods>;
1025 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1026 VOP3DisableFields<1, 0, HasMods>;
1029 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1030 list<dag> pattern, string opName, string revOp,
1031 bit HasMods = 1, bit UseFullOp = 0> {
1033 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1034 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1036 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1037 VOP3DisableFields<1, 0, HasMods>;
1039 // No VI instruction. This class is for SI only.
1042 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1043 // option of implicit vcc use?
1044 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
1045 list<dag> pattern, string opName, string revOp,
1046 bit HasMods = 1, bit UseFullOp = 0> {
1047 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1048 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1050 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1051 // can write it into any SGPR. We currently don't use the carry out,
1052 // so for now hardcode it to VCC as well.
1053 let sdst = SIOperand.VCC, Defs = [VCC] in {
1054 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1055 VOP3DisableFields<1, 0, HasMods>;
1057 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1058 VOP3DisableFields<1, 0, HasMods>;
1059 } // End sdst = SIOperand.VCC, Defs = [VCC]
1062 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1063 list<dag> pattern, string opName, string revOp,
1064 bit HasMods = 1, bit UseFullOp = 0> {
1065 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1068 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1069 VOP3DisableFields<1, 1, HasMods>;
1071 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1072 VOP3DisableFields<1, 1, HasMods>;
1075 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1076 list<dag> pattern, string opName,
1077 bit HasMods, bit defExec, string revOp> {
1079 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1080 VOPC_REV<revOp#"_e64", !eq(revOp, opName)>;
1082 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1083 VOP3DisableFields<1, 0, HasMods> {
1084 let Defs = !if(defExec, [EXEC], []);
1087 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1088 VOP3DisableFields<1, 0, HasMods> {
1089 let Defs = !if(defExec, [EXEC], []);
1093 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1094 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1095 string asm, list<dag> pattern = []> {
1096 let isPseudo = 1, isCodeGenOnly = 1 in {
1097 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1098 SIMCInstr<opName, SISubtarget.NONE>;
1101 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1102 SIMCInstr <opName, SISubtarget.SI>;
1104 def _vi : VOP3Common <outs, ins, asm, []>,
1106 VOP3DisableFields <1, 0, 0>,
1107 SIMCInstr <opName, SISubtarget.VI>;
1110 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1111 dag ins32, string asm32, list<dag> pat32,
1112 dag ins64, string asm64, list<dag> pat64,
1115 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1117 defm _e64 : VOP3_1_m <op, outs, ins64, opName#asm64, pat64, opName, HasMods>;
1120 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1121 SDPatternOperator node = null_frag> : VOP1_Helper <
1123 P.Ins32, P.Asm32, [],
1126 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1127 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1128 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1132 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1133 SDPatternOperator node = null_frag> {
1135 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1137 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1139 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1140 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1141 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1142 opName, P.HasModifiers>;
1145 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1146 dag ins32, string asm32, list<dag> pat32,
1147 dag ins64, string asm64, list<dag> pat64,
1148 string revOp, bit HasMods> {
1149 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1151 defm _e64 : VOP3_2_m <op,
1152 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1156 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1157 SDPatternOperator node = null_frag,
1158 string revOp = opName> : VOP2_Helper <
1160 P.Ins32, P.Asm32, [],
1164 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1165 i1:$clamp, i32:$omod)),
1166 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1167 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1168 revOp, P.HasModifiers
1171 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1172 SDPatternOperator node = null_frag,
1173 string revOp = opName> {
1174 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1176 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1179 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1180 i1:$clamp, i32:$omod)),
1181 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1182 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1183 opName, revOp, P.HasModifiers>;
1186 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1187 dag ins32, string asm32, list<dag> pat32,
1188 dag ins64, string asm64, list<dag> pat64,
1189 string revOp, bit HasMods> {
1191 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1193 defm _e64 : VOP3b_2_m <op,
1194 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1198 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1199 SDPatternOperator node = null_frag,
1200 string revOp = opName> : VOP2b_Helper <
1202 P.Ins32, P.Asm32, [],
1206 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1207 i1:$clamp, i32:$omod)),
1208 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1209 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1210 revOp, P.HasModifiers
1213 // A VOP2 instruction that is VOP3-only on VI.
1214 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1215 dag ins32, string asm32, list<dag> pat32,
1216 dag ins64, string asm64, list<dag> pat64,
1217 string revOp, bit HasMods> {
1218 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1220 defm _e64 : VOP3_2_m <op, outs, ins64, opName#asm64, pat64, opName,
1224 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1225 SDPatternOperator node = null_frag,
1226 string revOp = opName>
1229 P.Ins32, P.Asm32, [],
1233 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1234 i1:$clamp, i32:$omod)),
1235 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1236 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1237 revOp, P.HasModifiers
1240 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1242 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1244 let isCodeGenOnly = 0 in {
1245 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1246 !strconcat(opName, VOP_MADK.Asm), []>,
1247 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1250 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1251 !strconcat(opName, VOP_MADK.Asm), []>,
1252 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1254 } // End isCodeGenOnly = 0
1257 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1258 VOPCCommon <ins, "", pattern>,
1260 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1262 let isCodeGenOnly = 1;
1265 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1266 string opName, bit DefExec, string revOpName = ""> {
1267 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1269 def _si : VOPC<op.SI, ins, asm, []>,
1270 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1271 let Defs = !if(DefExec, [EXEC], []);
1272 let hasSideEffects = DefExec;
1275 def _vi : VOPC<op.VI, ins, asm, []>,
1276 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1277 let Defs = !if(DefExec, [EXEC], []);
1278 let hasSideEffects = DefExec;
1282 multiclass VOPC_Helper <vopc op, string opName,
1283 dag ins32, string asm32, list<dag> pat32,
1284 dag out64, dag ins64, string asm64, list<dag> pat64,
1285 bit HasMods, bit DefExec, string revOp> {
1286 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1288 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1289 opName, HasMods, DefExec, revOp>;
1292 // Special case for class instructions which only have modifiers on
1293 // the 1st source operand.
1294 multiclass VOPC_Class_Helper <vopc op, string opName,
1295 dag ins32, string asm32, list<dag> pat32,
1296 dag out64, dag ins64, string asm64, list<dag> pat64,
1297 bit HasMods, bit DefExec, string revOp> {
1298 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1300 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1301 opName, HasMods, DefExec, revOp>,
1302 VOP3DisableModFields<1, 0, 0>;
1305 multiclass VOPCInst <vopc op, string opName,
1306 VOPProfile P, PatLeaf cond = COND_NULL,
1307 string revOp = opName,
1308 bit DefExec = 0> : VOPC_Helper <
1310 P.Ins32, P.Asm32, [],
1311 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1314 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1315 i1:$clamp, i32:$omod)),
1316 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1318 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1319 P.HasModifiers, DefExec, revOp
1322 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1323 bit DefExec = 0> : VOPC_Class_Helper <
1325 P.Ins32, P.Asm32, [],
1326 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1329 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1330 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1331 P.HasModifiers, DefExec, opName
1335 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1336 VOPCInst <op, opName, VOP_F32_F32_F32, cond, revOp>;
1338 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1339 VOPCInst <op, opName, VOP_F64_F64_F64, cond, revOp>;
1341 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1342 VOPCInst <op, opName, VOP_I32_I32_I32, cond, revOp>;
1344 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1345 VOPCInst <op, opName, VOP_I64_I64_I64, cond, revOp>;
1348 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1349 PatLeaf cond = COND_NULL,
1351 : VOPCInst <op, opName, P, cond, revOp, 1>;
1353 multiclass VOPCX_F32 <vopc op, string opName, string revOp = opName> :
1354 VOPCX <op, opName, VOP_F32_F32_F32, COND_NULL, revOp>;
1356 multiclass VOPCX_F64 <vopc op, string opName, string revOp = opName> :
1357 VOPCX <op, opName, VOP_F64_F64_F64, COND_NULL, revOp>;
1359 multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> :
1360 VOPCX <op, opName, VOP_I32_I32_I32, COND_NULL, revOp>;
1362 multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
1363 VOPCX <op, opName, VOP_I64_I64_I64, COND_NULL, revOp>;
1365 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1366 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1367 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
1370 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1371 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1373 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1374 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1376 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1377 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1379 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1380 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1382 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1383 SDPatternOperator node = null_frag> : VOP3_Helper <
1384 op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
1385 !if(!eq(P.NumSrcArgs, 3),
1388 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1389 i1:$clamp, i32:$omod)),
1390 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1391 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1392 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1394 !if(!eq(P.NumSrcArgs, 2),
1397 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1398 i1:$clamp, i32:$omod)),
1399 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1400 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1401 /* P.NumSrcArgs == 1 */,
1404 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1405 i1:$clamp, i32:$omod))))],
1406 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1407 P.NumSrcArgs, P.HasModifiers
1410 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1411 // only VOP instruction that implicitly reads VCC.
1412 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1414 SDPatternOperator node = null_frag> : VOP3_Helper <
1416 (outs P.DstRC.RegClass:$dst),
1417 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1418 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1419 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1422 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1424 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1425 i1:$clamp, i32:$omod)),
1426 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1427 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1432 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1433 string opName, list<dag> pattern> :
1435 op, (outs vrc:$vdst, SReg_64:$sdst),
1436 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1437 InputModsNoDefault:$src1_modifiers, arc:$src1,
1438 InputModsNoDefault:$src2_modifiers, arc:$src2,
1439 ClampMod:$clamp, omod:$omod),
1440 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1441 opName, opName, 1, 1
1444 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1445 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1447 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1448 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1451 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1452 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1453 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1454 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1455 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1456 i32:$src1_modifiers, P.Src1VT:$src1,
1457 i32:$src2_modifiers, P.Src2VT:$src2,
1461 //===----------------------------------------------------------------------===//
1462 // Interpolation opcodes
1463 //===----------------------------------------------------------------------===//
1465 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1466 VINTRPCommon <outs, ins, "", pattern>,
1467 SIMCInstr<opName, SISubtarget.NONE> {
1469 let isCodeGenOnly = 1;
1472 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1474 VINTRPCommon <outs, ins, asm, []>,
1476 SIMCInstr<opName, SISubtarget.SI>;
1478 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1480 VINTRPCommon <outs, ins, asm, []>,
1482 SIMCInstr<opName, SISubtarget.VI>;
1484 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1485 string disableEncoding = "", string constraints = "",
1486 list<dag> pattern = []> {
1487 let DisableEncoding = disableEncoding,
1488 Constraints = constraints in {
1489 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1491 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1493 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1497 //===----------------------------------------------------------------------===//
1498 // Vector I/O classes
1499 //===----------------------------------------------------------------------===//
1501 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1502 DS <outs, ins, "", pattern>,
1503 SIMCInstr <opName, SISubtarget.NONE> {
1505 let isCodeGenOnly = 1;
1508 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1509 DS <outs, ins, asm, []>,
1511 SIMCInstr <opName, SISubtarget.SI>;
1513 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1514 DS <outs, ins, asm, []>,
1516 SIMCInstr <opName, SISubtarget.VI>;
1518 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1519 DS_Real_si <op,opName, outs, ins, asm> {
1521 // Single load interpret the 2 i8imm operands as a single i16 offset.
1523 let offset0 = offset{7-0};
1524 let offset1 = offset{15-8};
1527 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1528 DS_Real_vi <op, opName, outs, ins, asm> {
1530 // Single load interpret the 2 i8imm operands as a single i16 offset.
1532 let offset0 = offset{7-0};
1533 let offset1 = offset{15-8};
1536 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
1537 dag outs = (outs rc:$vdst),
1538 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds, M0Reg:$m0),
1539 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
1541 def "" : DS_Pseudo <opName, outs, ins, []>;
1543 let data0 = 0, data1 = 0 in {
1544 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1545 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1549 multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
1550 dag outs = (outs rc:$vdst),
1551 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1552 gds:$gds, M0Reg:$m0),
1553 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
1555 def "" : DS_Pseudo <opName, outs, ins, []>;
1557 let data0 = 0, data1 = 0 in {
1558 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1559 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1563 multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
1565 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds,
1567 string asm = opName#" $addr, $data0"#"$offset$gds"> {
1569 def "" : DS_Pseudo <opName, outs, ins, []>,
1570 AtomicNoRet<opName, 0>;
1572 let data1 = 0, vdst = 0 in {
1573 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1574 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1578 multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
1580 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1581 ds_offset0:$offset0, ds_offset1:$offset1, gds:$gds, M0Reg:$m0),
1582 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
1584 def "" : DS_Pseudo <opName, outs, ins, []>;
1587 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1588 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1592 multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
1593 string noRetOp = "",
1594 dag outs = (outs rc:$vdst),
1595 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds,
1597 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
1599 def "" : DS_Pseudo <opName, outs, ins, []>,
1600 AtomicNoRet<noRetOp, 1>;
1603 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1604 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1608 multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
1609 string noRetOp = "", dag ins,
1610 dag outs = (outs rc:$vdst),
1611 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
1613 def "" : DS_Pseudo <opName, outs, ins, []>,
1614 AtomicNoRet<noRetOp, 1>;
1616 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1617 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1620 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1621 string noRetOp = "", RegisterClass src = rc> :
1622 DS_1A2D_RET_m <op, asm, rc, noRetOp,
1623 (ins VGPR_32:$addr, src:$data0, src:$data1,
1624 ds_offset:$offset, gds:$gds, M0Reg:$m0)
1627 multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
1628 string noRetOp = opName,
1630 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1631 ds_offset:$offset, gds:$gds, M0Reg:$m0),
1632 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
1634 def "" : DS_Pseudo <opName, outs, ins, []>,
1635 AtomicNoRet<noRetOp, 0>;
1638 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1639 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1643 multiclass DS_0A_RET <bits<8> op, string opName,
1644 dag outs = (outs VGPR_32:$vdst),
1645 dag ins = (ins ds_offset:$offset, gds:$gds, M0Reg:$m0),
1646 string asm = opName#" $vdst"#"$offset"#"$gds"> {
1648 let mayLoad = 1, mayStore = 1 in {
1649 def "" : DS_Pseudo <opName, outs, ins, []>;
1651 let addr = 0, data0 = 0, data1 = 0 in {
1652 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1653 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1654 } // end addr = 0, data0 = 0, data1 = 0
1655 } // end mayLoad = 1, mayStore = 1
1658 multiclass DS_1A_RET_GDS <bits<8> op, string opName,
1659 dag outs = (outs VGPR_32:$vdst),
1660 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1661 string asm = opName#" $vdst, $addr"#"$offset gds"> {
1663 def "" : DS_Pseudo <opName, outs, ins, []>;
1665 let data0 = 0, data1 = 0, gds = 1 in {
1666 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1667 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1668 } // end data0 = 0, data1 = 0, gds = 1
1671 multiclass DS_1A_GDS <bits<8> op, string opName,
1673 dag ins = (ins VGPR_32:$addr, M0Reg:$m0),
1674 string asm = opName#" $addr gds"> {
1676 def "" : DS_Pseudo <opName, outs, ins, []>;
1678 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
1679 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1680 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1681 } // end vdst = 0, data = 0, data1 = 0, gds = 1
1684 multiclass DS_1A <bits<8> op, string opName,
1686 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0, gds:$gds),
1687 string asm = opName#" $addr"#"$offset"#"$gds"> {
1689 let mayLoad = 1, mayStore = 1 in {
1690 def "" : DS_Pseudo <opName, outs, ins, []>;
1692 let vdst = 0, data0 = 0, data1 = 0 in {
1693 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1694 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1695 } // let vdst = 0, data0 = 0, data1 = 0
1696 } // end mayLoad = 1, mayStore = 1
1699 //===----------------------------------------------------------------------===//
1701 //===----------------------------------------------------------------------===//
1703 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1704 MTBUF <outs, ins, "", pattern>,
1705 SIMCInstr<opName, SISubtarget.NONE> {
1707 let isCodeGenOnly = 1;
1710 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1712 MTBUF <outs, ins, asm, []>,
1714 SIMCInstr<opName, SISubtarget.SI>;
1716 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1717 MTBUF <outs, ins, asm, []>,
1719 SIMCInstr <opName, SISubtarget.VI>;
1721 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1722 list<dag> pattern> {
1724 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1726 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1728 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1732 let mayStore = 1, mayLoad = 0 in {
1734 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1735 RegisterClass regClass> : MTBUF_m <
1737 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1738 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1739 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1740 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1741 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1744 } // mayStore = 1, mayLoad = 0
1746 let mayLoad = 1, mayStore = 0 in {
1748 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1749 RegisterClass regClass> : MTBUF_m <
1750 op, opName, (outs regClass:$dst),
1751 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1752 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1753 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1754 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1755 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1758 } // mayLoad = 1, mayStore = 0
1760 //===----------------------------------------------------------------------===//
1762 //===----------------------------------------------------------------------===//
1764 class mubuf <bits<7> si, bits<7> vi = si> {
1765 field bits<7> SI = si;
1766 field bits<7> VI = vi;
1769 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1770 bit IsAddr64 = is_addr64;
1771 string OpName = NAME # suffix;
1774 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1775 MUBUF <outs, ins, "", pattern>,
1776 SIMCInstr<opName, SISubtarget.NONE> {
1778 let isCodeGenOnly = 1;
1780 // dummy fields, so that we can use let statements around multiclasses
1790 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1792 MUBUF <outs, ins, asm, []>,
1794 SIMCInstr<opName, SISubtarget.SI> {
1798 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
1800 MUBUF <outs, ins, asm, []>,
1802 SIMCInstr<opName, SISubtarget.VI> {
1806 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
1807 list<dag> pattern> {
1809 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1810 MUBUFAddr64Table <0>;
1813 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1816 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1819 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
1820 dag ins, string asm, list<dag> pattern> {
1822 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1823 MUBUFAddr64Table <1>;
1826 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1829 // There is no VI version. If the pseudo is selected, it should be lowered
1830 // for VI appropriately.
1833 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1834 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1838 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
1839 string asm, list<dag> pattern, bit is_return> {
1841 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1842 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
1843 AtomicNoRet<NAME#"_OFFSET", is_return>;
1845 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
1847 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1850 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
1854 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
1855 string asm, list<dag> pattern, bit is_return> {
1857 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
1858 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
1859 AtomicNoRet<NAME#"_ADDR64", is_return>;
1861 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
1862 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
1865 // There is no VI version. If the pseudo is selected, it should be lowered
1866 // for VI appropriately.
1869 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
1870 ValueType vt, SDPatternOperator atomic> {
1872 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1874 // No return variants
1877 defm _ADDR64 : MUBUFAtomicAddr64_m <
1878 op, name#"_addr64", (outs),
1879 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1880 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
1881 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
1884 defm _OFFSET : MUBUFAtomicOffset_m <
1885 op, name#"_offset", (outs),
1886 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
1888 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
1892 // Variant that return values
1893 let glc = 1, Constraints = "$vdata = $vdata_in",
1894 DisableEncoding = "$vdata_in" in {
1896 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
1897 op, name#"_rtn_addr64", (outs rc:$vdata),
1898 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1899 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
1900 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
1902 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
1903 i16:$offset, i1:$slc), vt:$vdata_in))], 1
1906 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
1907 op, name#"_rtn_offset", (outs rc:$vdata),
1908 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
1909 mbuf_offset:$offset, slc:$slc),
1910 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1912 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1913 i1:$slc), vt:$vdata_in))], 1
1918 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1921 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
1922 ValueType load_vt = i32,
1923 SDPatternOperator ld = null_frag> {
1925 let mayLoad = 1, mayStore = 0 in {
1926 let offen = 0, idxen = 0, vaddr = 0 in {
1927 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
1928 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
1929 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1930 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1931 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1932 i32:$soffset, i16:$offset,
1933 i1:$glc, i1:$slc, i1:$tfe)))]>;
1936 let offen = 1, idxen = 0 in {
1937 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
1938 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
1939 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1941 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1944 let offen = 0, idxen = 1 in {
1945 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
1946 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
1947 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
1948 slc:$slc, tfe:$tfe),
1949 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1952 let offen = 1, idxen = 1 in {
1953 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
1954 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
1955 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1956 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1959 let offen = 0, idxen = 0 in {
1960 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
1961 (ins VReg_64:$vaddr, SReg_128:$srsrc,
1962 SCSrc_32:$soffset, mbuf_offset:$offset,
1963 glc:$glc, slc:$slc, tfe:$tfe),
1964 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
1965 "$glc"#"$slc"#"$tfe",
1966 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1967 i64:$vaddr, i32:$soffset,
1968 i16:$offset, i1:$glc, i1:$slc,
1974 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
1975 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
1976 let mayLoad = 0, mayStore = 1 in {
1977 defm : MUBUF_m <op, name, (outs),
1978 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
1979 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1981 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1982 "$glc"#"$slc"#"$tfe", []>;
1984 let offen = 0, idxen = 0, vaddr = 0 in {
1985 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
1986 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
1987 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1988 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1989 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1990 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
1991 } // offen = 0, idxen = 0, vaddr = 0
1993 let offen = 1, idxen = 0 in {
1994 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
1995 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
1996 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
1997 slc:$slc, tfe:$tfe),
1998 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1999 "$glc"#"$slc"#"$tfe", []>;
2000 } // end offen = 1, idxen = 0
2002 let offen = 0, idxen = 1 in {
2003 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs),
2004 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2005 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2006 slc:$slc, tfe:$tfe),
2007 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2010 let offen = 1, idxen = 1 in {
2011 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs),
2012 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2013 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2014 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2017 let offen = 0, idxen = 0 in {
2018 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
2019 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2021 mbuf_offset:$offset, glc:$glc, slc:$slc,
2023 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
2024 "$offset"#"$glc"#"$slc"#"$tfe",
2025 [(st store_vt:$vdata,
2026 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
2027 i32:$soffset, i16:$offset,
2028 i1:$glc, i1:$slc, i1:$tfe))]>;
2030 } // End mayLoad = 0, mayStore = 1
2033 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
2034 FLAT <op, (outs regClass:$vdst),
2035 (ins VReg_64:$addr),
2036 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
2044 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
2045 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
2046 name#" $data, $addr, [M0, FLAT_SCRATCH]",
2059 class MIMG_Mask <string op, int channels> {
2061 int Channels = channels;
2064 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2065 RegisterClass dst_rc,
2066 RegisterClass src_rc> : MIMG <
2068 (outs dst_rc:$vdata),
2069 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2070 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2072 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2073 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2078 let hasPostISelHook = 1;
2081 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2082 RegisterClass dst_rc,
2084 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2085 MIMG_Mask<asm#"_V1", channels>;
2086 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2087 MIMG_Mask<asm#"_V2", channels>;
2088 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2089 MIMG_Mask<asm#"_V4", channels>;
2092 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2093 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2094 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2095 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2096 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2099 class MIMG_Sampler_Helper <bits<7> op, string asm,
2100 RegisterClass dst_rc,
2101 RegisterClass src_rc, int wqm> : MIMG <
2103 (outs dst_rc:$vdata),
2104 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2105 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2106 SReg_256:$srsrc, SReg_128:$ssamp),
2107 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2108 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2112 let hasPostISelHook = 1;
2116 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2117 RegisterClass dst_rc,
2118 int channels, int wqm> {
2119 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2120 MIMG_Mask<asm#"_V1", channels>;
2121 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2122 MIMG_Mask<asm#"_V2", channels>;
2123 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2124 MIMG_Mask<asm#"_V4", channels>;
2125 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2126 MIMG_Mask<asm#"_V8", channels>;
2127 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2128 MIMG_Mask<asm#"_V16", channels>;
2131 multiclass MIMG_Sampler <bits<7> op, string asm> {
2132 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2133 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2134 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2135 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2138 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2139 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2140 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2141 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2142 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2145 class MIMG_Gather_Helper <bits<7> op, string asm,
2146 RegisterClass dst_rc,
2147 RegisterClass src_rc, int wqm> : MIMG <
2149 (outs dst_rc:$vdata),
2150 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2151 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2152 SReg_256:$srsrc, SReg_128:$ssamp),
2153 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2154 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2159 // DMASK was repurposed for GATHER4. 4 components are always
2160 // returned and DMASK works like a swizzle - it selects
2161 // the component to fetch. The only useful DMASK values are
2162 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2163 // (red,red,red,red) etc.) The ISA document doesn't mention
2165 // Therefore, disable all code which updates DMASK by setting these two:
2167 let hasPostISelHook = 0;
2171 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2172 RegisterClass dst_rc,
2173 int channels, int wqm> {
2174 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2175 MIMG_Mask<asm#"_V1", channels>;
2176 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2177 MIMG_Mask<asm#"_V2", channels>;
2178 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2179 MIMG_Mask<asm#"_V4", channels>;
2180 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2181 MIMG_Mask<asm#"_V8", channels>;
2182 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2183 MIMG_Mask<asm#"_V16", channels>;
2186 multiclass MIMG_Gather <bits<7> op, string asm> {
2187 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2188 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2189 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2190 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2193 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2194 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2195 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2196 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2197 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2200 //===----------------------------------------------------------------------===//
2201 // Vector instruction mappings
2202 //===----------------------------------------------------------------------===//
2204 // Maps an opcode in e32 form to its e64 equivalent
2205 def getVOPe64 : InstrMapping {
2206 let FilterClass = "VOP";
2207 let RowFields = ["OpName"];
2208 let ColFields = ["Size"];
2210 let ValueCols = [["8"]];
2213 // Maps an opcode in e64 form to its e32 equivalent
2214 def getVOPe32 : InstrMapping {
2215 let FilterClass = "VOP";
2216 let RowFields = ["OpName"];
2217 let ColFields = ["Size"];
2219 let ValueCols = [["4"]];
2222 def getMaskedMIMGOp : InstrMapping {
2223 let FilterClass = "MIMG_Mask";
2224 let RowFields = ["Op"];
2225 let ColFields = ["Channels"];
2227 let ValueCols = [["1"], ["2"], ["3"] ];
2230 // Maps an commuted opcode to its original version
2231 def getCommuteOrig : InstrMapping {
2232 let FilterClass = "VOP2_REV";
2233 let RowFields = ["RevOp"];
2234 let ColFields = ["IsOrig"];
2236 let ValueCols = [["1"]];
2239 // Maps an original opcode to its commuted version
2240 def getCommuteRev : InstrMapping {
2241 let FilterClass = "VOP2_REV";
2242 let RowFields = ["RevOp"];
2243 let ColFields = ["IsOrig"];
2245 let ValueCols = [["0"]];
2248 def getCommuteCmpOrig : InstrMapping {
2249 let FilterClass = "VOPC_REV";
2250 let RowFields = ["RevOp"];
2251 let ColFields = ["IsOrig"];
2253 let ValueCols = [["1"]];
2256 // Maps an original opcode to its commuted version
2257 def getCommuteCmpRev : InstrMapping {
2258 let FilterClass = "VOPC_REV";
2259 let RowFields = ["RevOp"];
2260 let ColFields = ["IsOrig"];
2262 let ValueCols = [["0"]];
2266 def getMCOpcodeGen : InstrMapping {
2267 let FilterClass = "SIMCInstr";
2268 let RowFields = ["PseudoInstr"];
2269 let ColFields = ["Subtarget"];
2270 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2271 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2274 def getAddr64Inst : InstrMapping {
2275 let FilterClass = "MUBUFAddr64Table";
2276 let RowFields = ["OpName"];
2277 let ColFields = ["IsAddr64"];
2279 let ValueCols = [["1"]];
2282 // Maps an atomic opcode to its version with a return value.
2283 def getAtomicRetOp : InstrMapping {
2284 let FilterClass = "AtomicNoRet";
2285 let RowFields = ["NoRetOp"];
2286 let ColFields = ["IsRet"];
2288 let ValueCols = [["1"]];
2291 // Maps an atomic opcode to its returnless version.
2292 def getAtomicNoRetOp : InstrMapping {
2293 let FilterClass = "AtomicNoRet";
2294 let RowFields = ["NoRetOp"];
2295 let ColFields = ["IsRet"];
2297 let ValueCols = [["0"]];
2300 include "SIInstructions.td"
2301 include "CIInstructions.td"
2302 include "VIInstructions.td"