1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
19 #include "AMDGPUInstrInfo.h"
20 #include "SIRegisterInfo.h"
24 class SIInstrInfo : public AMDGPUInstrInfo {
26 const SIRegisterInfo RI;
28 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
29 MachineRegisterInfo &MRI,
30 MachineOperand &SuperReg,
31 const TargetRegisterClass *SuperRC,
33 const TargetRegisterClass *SubRC) const;
34 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
35 MachineRegisterInfo &MRI,
36 MachineOperand &SuperReg,
37 const TargetRegisterClass *SuperRC,
39 const TargetRegisterClass *SubRC) const;
41 unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
42 MachineBasicBlock::iterator MI,
43 MachineRegisterInfo &MRI,
44 const TargetRegisterClass *RC,
45 const MachineOperand &Op) const;
47 void splitScalar64BitOp(SmallVectorImpl<MachineInstr *> & Worklist,
48 MachineInstr *Inst, unsigned Opcode) const;
52 explicit SIInstrInfo(AMDGPUTargetMachine &tm);
54 const SIRegisterInfo &getRegisterInfo() const {
58 virtual void copyPhysReg(MachineBasicBlock &MBB,
59 MachineBasicBlock::iterator MI, DebugLoc DL,
60 unsigned DestReg, unsigned SrcReg,
63 void storeRegToStackSlot(MachineBasicBlock &MBB,
64 MachineBasicBlock::iterator MI,
65 unsigned SrcReg, bool isKill, int FrameIndex,
66 const TargetRegisterClass *RC,
67 const TargetRegisterInfo *TRI) const;
69 void loadRegFromStackSlot(MachineBasicBlock &MBB,
70 MachineBasicBlock::iterator MI,
71 unsigned DestReg, int FrameIndex,
72 const TargetRegisterClass *RC,
73 const TargetRegisterInfo *TRI) const;
75 unsigned commuteOpcode(unsigned Opcode) const;
77 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
78 bool NewMI=false) const;
80 virtual unsigned getIEQOpcode() const {
81 llvm_unreachable("Unimplemented");
84 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
85 MachineBasicBlock::iterator I,
86 unsigned DstReg, unsigned SrcReg) const;
87 virtual bool isMov(unsigned Opcode) const;
89 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
90 bool isDS(uint16_t Opcode) const;
91 int isMIMG(uint16_t Opcode) const;
92 int isSMRD(uint16_t Opcode) const;
93 bool isVOP1(uint16_t Opcode) const;
94 bool isVOP2(uint16_t Opcode) const;
95 bool isVOP3(uint16_t Opcode) const;
96 bool isVOPC(uint16_t Opcode) const;
97 bool isInlineConstant(const MachineOperand &MO) const;
98 bool isLiteralConstant(const MachineOperand &MO) const;
100 virtual bool verifyInstruction(const MachineInstr *MI,
101 StringRef &ErrInfo) const;
103 bool isSALUInstr(const MachineInstr &MI) const;
104 static unsigned getVALUOp(const MachineInstr &MI);
106 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
108 /// \brief Return the correct register class for \p OpNo. For target-specific
109 /// instructions, this will return the register class that has been defined
110 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
111 /// the register class of its machine operand.
112 /// to infer the correct register class base on the other operands.
113 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
114 unsigned OpNo) const;\
116 /// \returns true if it is legal for the operand at index \p OpNo
118 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
120 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
121 /// a MOV. For example:
122 /// ADD_I32_e32 VGPR0, 15
125 /// ADD_I32_e32 VGPR0, VGPR1
127 /// If the operand being legalized is a register, then a COPY will be used
129 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
131 /// \brief Legalize all operands in this instruction. This function may
132 /// create new instruction and insert them before \p MI.
133 void legalizeOperands(MachineInstr *MI) const;
135 /// \brief Replace this instruction's opcode with the equivalent VALU
136 /// opcode. This function will also move the users of \p MI to the
137 /// VALU if necessary.
138 void moveToVALU(MachineInstr &MI) const;
140 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
141 unsigned Channel) const;
143 virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
145 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
146 MachineBasicBlock::iterator I,
149 unsigned OffsetReg) const;
151 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
152 MachineBasicBlock::iterator I,
155 unsigned OffsetReg) const;
156 void reserveIndirectRegisters(BitVector &Reserved,
157 const MachineFunction &MF) const;
159 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
160 unsigned SavReg, unsigned IndexReg) const;
165 int getVOPe64(uint16_t Opcode);
166 int getCommuteRev(uint16_t Opcode);
167 int getCommuteOrig(uint16_t Opcode);
169 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
172 } // End namespace AMDGPU
174 } // End namespace llvm
176 namespace SIInstrFlags {
178 // First 4 bits are the instruction encoding
185 #endif //SIINSTRINFO_H