1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
29 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
30 : AMDGPUInstrInfo(st),
33 //===----------------------------------------------------------------------===//
34 // TargetInstrInfo callbacks
35 //===----------------------------------------------------------------------===//
37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
38 unsigned N = Node->getNumOperands();
39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
44 static SDValue findChainOperand(SDNode *Load) {
45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
50 /// \brief Returns true if both nodes have the same value for the given
51 /// operand \p Op, or if both nodes do not have this operand.
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
53 unsigned Opc0 = N0->getMachineOpcode();
54 unsigned Opc1 = N1->getMachineOpcode();
56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59 if (Op0Idx == -1 && Op1Idx == -1)
63 if ((Op0Idx == -1 && Op1Idx != -1) ||
64 (Op1Idx == -1 && Op0Idx != -1))
67 // getNamedOperandIdx returns the index for the MachineInstr's operands,
68 // which includes the result as the first operand. We are indexing into the
69 // MachineSDNode's operands, so we need to skip the result operand to get
74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
77 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
79 int64_t &Offset1) const {
80 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
83 unsigned Opc0 = Load0->getMachineOpcode();
84 unsigned Opc1 = Load1->getMachineOpcode();
86 // Make sure both are actually loads.
87 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
90 if (isDS(Opc0) && isDS(Opc1)) {
91 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
94 if (Load0->getOperand(1) != Load1->getOperand(1))
98 if (findChainOperand(Load0) != findChainOperand(Load1))
101 // Skip read2 / write2 variants for simplicity.
102 // TODO: We should report true if the used offsets are adjacent (excluded
104 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
105 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
108 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
109 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
113 if (isSMRD(Opc0) && isSMRD(Opc1)) {
114 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
117 if (Load0->getOperand(0) != Load1->getOperand(0))
121 if (findChainOperand(Load0) != findChainOperand(Load1))
124 Offset0 = cast<ConstantSDNode>(Load0->getOperand(1))->getZExtValue();
125 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue();
129 // MUBUF and MTBUF can access the same addresses.
130 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
132 // MUBUF and MTBUF have vaddr at different indices.
133 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
134 findChainOperand(Load0) != findChainOperand(Load1) ||
135 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
136 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
139 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
140 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
142 if (OffIdx0 == -1 || OffIdx1 == -1)
145 // getNamedOperandIdx returns the index for MachineInstrs. Since they
146 // inlcude the output in the operand list, but SDNodes don't, we need to
147 // subtract the index by one.
151 SDValue Off0 = Load0->getOperand(OffIdx0);
152 SDValue Off1 = Load1->getOperand(OffIdx1);
154 // The offset might be a FrameIndexSDNode.
155 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
158 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
159 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
166 static bool isStride64(unsigned Opc) {
168 case AMDGPU::DS_READ2ST64_B32:
169 case AMDGPU::DS_READ2ST64_B64:
170 case AMDGPU::DS_WRITE2ST64_B32:
171 case AMDGPU::DS_WRITE2ST64_B64:
178 bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
179 unsigned &BaseReg, unsigned &Offset,
180 const TargetRegisterInfo *TRI) const {
181 unsigned Opc = LdSt->getOpcode();
183 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
184 AMDGPU::OpName::offset);
186 // Normal, single offset LDS instruction.
187 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
188 AMDGPU::OpName::addr);
190 BaseReg = AddrReg->getReg();
191 Offset = OffsetImm->getImm();
195 // The 2 offset instructions use offset0 and offset1 instead. We can treat
196 // these as a load with a single offset if the 2 offsets are consecutive. We
197 // will use this for some partially aligned loads.
198 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
199 AMDGPU::OpName::offset0);
200 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
201 AMDGPU::OpName::offset1);
203 uint8_t Offset0 = Offset0Imm->getImm();
204 uint8_t Offset1 = Offset1Imm->getImm();
205 assert(Offset1 > Offset0);
207 if (Offset1 - Offset0 == 1) {
208 // Each of these offsets is in element sized units, so we need to convert
209 // to bytes of the individual reads.
213 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
215 assert(LdSt->mayStore());
216 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
217 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
223 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
224 AMDGPU::OpName::addr);
225 BaseReg = AddrReg->getReg();
226 Offset = EltSize * Offset0;
233 if (isMUBUF(Opc) || isMTBUF(Opc)) {
234 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
237 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
238 AMDGPU::OpName::vaddr);
242 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
243 AMDGPU::OpName::offset);
244 BaseReg = AddrReg->getReg();
245 Offset = OffsetImm->getImm();
250 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
251 AMDGPU::OpName::offset);
255 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
256 AMDGPU::OpName::sbase);
257 BaseReg = SBaseReg->getReg();
258 Offset = OffsetImm->getImm();
265 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
266 MachineInstr *SecondLdSt,
267 unsigned NumLoads) const {
268 unsigned Opc0 = FirstLdSt->getOpcode();
269 unsigned Opc1 = SecondLdSt->getOpcode();
271 // TODO: This needs finer tuning
275 if (isDS(Opc0) && isDS(Opc1))
278 if (isSMRD(Opc0) && isSMRD(Opc1))
281 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1)))
288 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
289 MachineBasicBlock::iterator MI, DebugLoc DL,
290 unsigned DestReg, unsigned SrcReg,
291 bool KillSrc) const {
293 // If we are trying to copy to or from SCC, there is a bug somewhere else in
294 // the backend. While it may be theoretically possible to do this, it should
295 // never be necessary.
296 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
298 static const int16_t Sub0_15[] = {
299 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
300 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
301 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
302 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
305 static const int16_t Sub0_7[] = {
306 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
307 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
310 static const int16_t Sub0_3[] = {
311 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
314 static const int16_t Sub0_2[] = {
315 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
318 static const int16_t Sub0_1[] = {
319 AMDGPU::sub0, AMDGPU::sub1, 0
323 const int16_t *SubIndices;
325 if (AMDGPU::M0 == DestReg) {
326 // Check if M0 isn't already set to this value
327 for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
328 I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
330 if (!I->definesRegister(AMDGPU::M0))
333 unsigned Opc = I->getOpcode();
334 if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
337 if (!I->readsRegister(SrcReg))
340 // The copy isn't necessary
345 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
346 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
347 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
348 .addReg(SrcReg, getKillRegState(KillSrc));
351 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
352 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
353 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
354 .addReg(SrcReg, getKillRegState(KillSrc));
357 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
358 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
359 Opcode = AMDGPU::S_MOV_B32;
362 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
363 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
364 Opcode = AMDGPU::S_MOV_B32;
367 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
368 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
369 Opcode = AMDGPU::S_MOV_B32;
370 SubIndices = Sub0_15;
372 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
373 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
374 AMDGPU::SReg_32RegClass.contains(SrcReg));
375 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
376 .addReg(SrcReg, getKillRegState(KillSrc));
379 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
380 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
381 AMDGPU::SReg_64RegClass.contains(SrcReg));
382 Opcode = AMDGPU::V_MOV_B32_e32;
385 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
386 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
387 Opcode = AMDGPU::V_MOV_B32_e32;
390 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
391 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
392 AMDGPU::SReg_128RegClass.contains(SrcReg));
393 Opcode = AMDGPU::V_MOV_B32_e32;
396 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
397 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
398 AMDGPU::SReg_256RegClass.contains(SrcReg));
399 Opcode = AMDGPU::V_MOV_B32_e32;
402 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
403 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
404 AMDGPU::SReg_512RegClass.contains(SrcReg));
405 Opcode = AMDGPU::V_MOV_B32_e32;
406 SubIndices = Sub0_15;
409 llvm_unreachable("Can't copy register!");
412 while (unsigned SubIdx = *SubIndices++) {
413 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
414 get(Opcode), RI.getSubReg(DestReg, SubIdx));
416 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
419 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
423 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
426 // Try to map original to commuted opcode
427 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
430 // Try to map commuted to original opcode
431 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
437 static bool shouldTryToSpillVGPRs(MachineFunction *MF) {
439 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
440 const TargetMachine &TM = MF->getTarget();
442 // FIXME: Even though it can cause problems, we need to enable
443 // spilling at -O0, since the fast register allocator always
444 // spills registers that are live at the end of blocks.
445 return MFI->getShaderType() == ShaderType::COMPUTE &&
446 TM.getOptLevel() == CodeGenOpt::None;
450 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
451 MachineBasicBlock::iterator MI,
452 unsigned SrcReg, bool isKill,
454 const TargetRegisterClass *RC,
455 const TargetRegisterInfo *TRI) const {
456 MachineFunction *MF = MBB.getParent();
457 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
458 DebugLoc DL = MBB.findDebugLoc(MI);
461 if (RI.isSGPRClass(RC)) {
462 // We are only allowed to create one new instruction when spilling
463 // registers, so we need to use pseudo instruction for spilling
465 switch (RC->getSize() * 8) {
466 case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break;
467 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
468 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
469 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
470 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
472 } else if(shouldTryToSpillVGPRs(MF) && RI.hasVGPRs(RC)) {
473 switch(RC->getSize() * 8) {
474 case 32: Opcode = AMDGPU::SI_SPILL_V32_SAVE; break;
475 case 64: Opcode = AMDGPU::SI_SPILL_V64_SAVE; break;
476 case 96: Opcode = AMDGPU::SI_SPILL_V96_SAVE; break;
477 case 128: Opcode = AMDGPU::SI_SPILL_V128_SAVE; break;
478 case 256: Opcode = AMDGPU::SI_SPILL_V256_SAVE; break;
479 case 512: Opcode = AMDGPU::SI_SPILL_V512_SAVE; break;
484 FrameInfo->setObjectAlignment(FrameIndex, 4);
485 BuildMI(MBB, MI, DL, get(Opcode))
487 .addFrameIndex(FrameIndex);
489 LLVMContext &Ctx = MF->getFunction()->getContext();
490 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
492 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), AMDGPU::VGPR0)
497 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
498 MachineBasicBlock::iterator MI,
499 unsigned DestReg, int FrameIndex,
500 const TargetRegisterClass *RC,
501 const TargetRegisterInfo *TRI) const {
502 MachineFunction *MF = MBB.getParent();
503 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
504 DebugLoc DL = MBB.findDebugLoc(MI);
507 if (RI.isSGPRClass(RC)){
508 switch(RC->getSize() * 8) {
509 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
510 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
511 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
512 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
513 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
515 } else if(shouldTryToSpillVGPRs(MF) && RI.hasVGPRs(RC)) {
516 switch(RC->getSize() * 8) {
517 case 32: Opcode = AMDGPU::SI_SPILL_V32_RESTORE; break;
518 case 64: Opcode = AMDGPU::SI_SPILL_V64_RESTORE; break;
519 case 96: Opcode = AMDGPU::SI_SPILL_V96_RESTORE; break;
520 case 128: Opcode = AMDGPU::SI_SPILL_V128_RESTORE; break;
521 case 256: Opcode = AMDGPU::SI_SPILL_V256_RESTORE; break;
522 case 512: Opcode = AMDGPU::SI_SPILL_V512_RESTORE; break;
527 FrameInfo->setObjectAlignment(FrameIndex, 4);
528 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
529 .addFrameIndex(FrameIndex);
531 LLVMContext &Ctx = MF->getFunction()->getContext();
532 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
533 " restore register");
534 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
535 .addReg(AMDGPU::VGPR0);
539 /// \param @Offset Offset in bytes of the FrameIndex being spilled
540 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
541 MachineBasicBlock::iterator MI,
542 RegScavenger *RS, unsigned TmpReg,
543 unsigned FrameOffset,
544 unsigned Size) const {
545 MachineFunction *MF = MBB.getParent();
546 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
547 const AMDGPUSubtarget &ST = MF->getTarget().getSubtarget<AMDGPUSubtarget>();
548 const SIRegisterInfo *TRI =
549 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
550 DebugLoc DL = MBB.findDebugLoc(MI);
551 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
552 unsigned WavefrontSize = ST.getWavefrontSize();
554 unsigned TIDReg = MFI->getTIDReg();
555 if (!MFI->hasCalculatedTID()) {
556 MachineBasicBlock &Entry = MBB.getParent()->front();
557 MachineBasicBlock::iterator Insert = Entry.front();
558 DebugLoc DL = Insert->getDebugLoc();
560 TIDReg = RI.findUnusedVGPR(MF->getRegInfo());
561 if (TIDReg == AMDGPU::NoRegister)
565 if (MFI->getShaderType() == ShaderType::COMPUTE &&
566 WorkGroupSize > WavefrontSize) {
568 unsigned TIDIGXReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_X);
569 unsigned TIDIGYReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Y);
570 unsigned TIDIGZReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Z);
571 unsigned InputPtrReg =
572 TRI->getPreloadedValue(*MF, SIRegisterInfo::INPUT_PTR);
573 static const unsigned TIDIGRegs[3] = {
574 TIDIGXReg, TIDIGYReg, TIDIGZReg
576 for (unsigned Reg : TIDIGRegs) {
577 if (!Entry.isLiveIn(Reg))
578 Entry.addLiveIn(Reg);
581 RS->enterBasicBlock(&Entry);
582 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
583 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
584 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
586 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
587 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
589 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
591 // NGROUPS.X * NGROUPS.Y
592 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
595 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
596 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
599 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
600 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
604 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
605 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
610 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
615 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e32),
621 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
625 MFI->setTIDReg(TIDReg);
628 // Add FrameIndex to LDS offset
629 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
630 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
637 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
646 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
651 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
652 MachineBasicBlock &MBB = *MI->getParent();
653 DebugLoc DL = MBB.findDebugLoc(MI);
654 switch (MI->getOpcode()) {
655 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
657 case AMDGPU::SI_CONSTDATA_PTR: {
658 unsigned Reg = MI->getOperand(0).getReg();
659 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
660 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
662 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
664 // Add 32-bit offset from this instruction to the start of the constant data.
665 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo)
667 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
668 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
669 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
672 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
673 .addReg(AMDGPU::SCC, RegState::Implicit);
674 MI->eraseFromParent();
677 case AMDGPU::SGPR_USE:
678 // This is just a placeholder for register allocation.
679 MI->eraseFromParent();
685 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
688 if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg())
691 // Make sure it s legal to commute operands for VOP2.
692 if (isVOP2(MI->getOpcode()) &&
693 (!isOperandLegal(MI, 1, &MI->getOperand(2)) ||
694 !isOperandLegal(MI, 2, &MI->getOperand(1))))
697 if (!MI->getOperand(2).isReg()) {
698 // XXX: Commute instructions with FPImm operands
699 if (NewMI || MI->getOperand(2).isFPImm() ||
700 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
704 // XXX: Commute VOP3 instructions with abs and neg set .
705 const MachineOperand *Abs = getNamedOperand(*MI, AMDGPU::OpName::abs);
706 const MachineOperand *Neg = getNamedOperand(*MI, AMDGPU::OpName::neg);
707 const MachineOperand *Src0Mods = getNamedOperand(*MI,
708 AMDGPU::OpName::src0_modifiers);
709 const MachineOperand *Src1Mods = getNamedOperand(*MI,
710 AMDGPU::OpName::src1_modifiers);
711 const MachineOperand *Src2Mods = getNamedOperand(*MI,
712 AMDGPU::OpName::src2_modifiers);
714 if ((Abs && Abs->getImm()) || (Neg && Neg->getImm()) ||
715 (Src0Mods && Src0Mods->getImm()) || (Src1Mods && Src1Mods->getImm()) ||
716 (Src2Mods && Src2Mods->getImm()))
719 unsigned Reg = MI->getOperand(1).getReg();
720 unsigned SubReg = MI->getOperand(1).getSubReg();
721 MI->getOperand(1).ChangeToImmediate(MI->getOperand(2).getImm());
722 MI->getOperand(2).ChangeToRegister(Reg, false);
723 MI->getOperand(2).setSubReg(SubReg);
725 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
729 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
734 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
735 MachineBasicBlock::iterator I,
737 unsigned SrcReg) const {
738 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
739 DstReg) .addReg(SrcReg);
742 bool SIInstrInfo::isMov(unsigned Opcode) const {
744 default: return false;
745 case AMDGPU::S_MOV_B32:
746 case AMDGPU::S_MOV_B64:
747 case AMDGPU::V_MOV_B32_e32:
748 case AMDGPU::V_MOV_B32_e64:
754 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
755 return RC != &AMDGPU::EXECRegRegClass;
759 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
760 AliasAnalysis *AA) const {
761 switch(MI->getOpcode()) {
762 default: return AMDGPUInstrInfo::isTriviallyReMaterializable(MI, AA);
763 case AMDGPU::S_MOV_B32:
764 case AMDGPU::S_MOV_B64:
765 case AMDGPU::V_MOV_B32_e32:
766 return MI->getOperand(1).isImm();
772 // Helper function generated by tablegen. We are wrapping this with
773 // an SIInstrInfo function that returns bool rather than int.
774 int isDS(uint16_t Opcode);
778 bool SIInstrInfo::isDS(uint16_t Opcode) const {
779 return ::AMDGPU::isDS(Opcode) != -1;
782 bool SIInstrInfo::isMIMG(uint16_t Opcode) const {
783 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
786 bool SIInstrInfo::isSMRD(uint16_t Opcode) const {
787 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
790 bool SIInstrInfo::isMUBUF(uint16_t Opcode) const {
791 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
794 bool SIInstrInfo::isMTBUF(uint16_t Opcode) const {
795 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
798 bool SIInstrInfo::isFLAT(uint16_t Opcode) const {
799 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
802 bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
803 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
806 bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
807 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
810 bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
811 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
814 bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
815 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
818 bool SIInstrInfo::isSALUInstr(const MachineInstr &MI) const {
819 return get(MI.getOpcode()).TSFlags & SIInstrFlags::SALU;
822 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
823 int32_t Val = Imm.getSExtValue();
824 if (Val >= -16 && Val <= 64)
827 // The actual type of the operand does not seem to matter as long
828 // as the bits match one of the inline immediate values. For example:
830 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
831 // so it is a legal inline immediate.
833 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
834 // floating-point, so it is a legal inline immediate.
836 return (APInt::floatToBits(0.0f) == Imm) ||
837 (APInt::floatToBits(1.0f) == Imm) ||
838 (APInt::floatToBits(-1.0f) == Imm) ||
839 (APInt::floatToBits(0.5f) == Imm) ||
840 (APInt::floatToBits(-0.5f) == Imm) ||
841 (APInt::floatToBits(2.0f) == Imm) ||
842 (APInt::floatToBits(-2.0f) == Imm) ||
843 (APInt::floatToBits(4.0f) == Imm) ||
844 (APInt::floatToBits(-4.0f) == Imm);
847 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
849 return isInlineConstant(APInt(32, MO.getImm(), true));
852 APFloat FpImm = MO.getFPImm()->getValueAPF();
853 return isInlineConstant(FpImm.bitcastToAPInt());
859 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
860 return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO);
863 static bool compareMachineOp(const MachineOperand &Op0,
864 const MachineOperand &Op1) {
865 if (Op0.getType() != Op1.getType())
868 switch (Op0.getType()) {
869 case MachineOperand::MO_Register:
870 return Op0.getReg() == Op1.getReg();
871 case MachineOperand::MO_Immediate:
872 return Op0.getImm() == Op1.getImm();
873 case MachineOperand::MO_FPImmediate:
874 return Op0.getFPImm() == Op1.getFPImm();
876 llvm_unreachable("Didn't expect to be comparing these operand types");
880 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
881 const MachineOperand &MO) const {
882 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
884 assert(MO.isImm() || MO.isFPImm() || MO.isTargetIndex() || MO.isFI());
886 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
889 if (OpInfo.RegClass < 0)
892 if (isLiteralConstant(MO))
893 return RI.regClassCanUseLiteralConstant(OpInfo.RegClass);
895 return RI.regClassCanUseInlineConstant(OpInfo.RegClass);
898 bool SIInstrInfo::canFoldOffset(unsigned OffsetSize, unsigned AS) {
900 case AMDGPUAS::GLOBAL_ADDRESS: {
901 // MUBUF instructions a 12-bit offset in bytes.
902 return isUInt<12>(OffsetSize);
904 case AMDGPUAS::CONSTANT_ADDRESS: {
905 // SMRD instructions have an 8-bit offset in dwords.
906 return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4);
908 case AMDGPUAS::LOCAL_ADDRESS:
909 case AMDGPUAS::REGION_ADDRESS: {
910 // The single offset versions have a 16-bit offset in bytes.
911 return isUInt<16>(OffsetSize);
913 case AMDGPUAS::PRIVATE_ADDRESS:
914 // Indirect register addressing does not use any offsets.
920 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
921 return AMDGPU::getVOPe32(Opcode) != -1;
924 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
925 // The src0_modifier operand is present on all instructions
926 // that have modifiers.
928 return AMDGPU::getNamedOperandIdx(Opcode,
929 AMDGPU::OpName::src0_modifiers) != -1;
932 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
933 const MachineOperand &MO) const {
934 // Literal constants use the constant bus.
935 if (isLiteralConstant(MO))
938 if (!MO.isReg() || !MO.isUse())
941 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
942 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
944 // FLAT_SCR is just an SGPR pair.
945 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
948 // EXEC register uses the constant bus.
949 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
952 // SGPRs use the constant bus
953 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
955 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
956 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
963 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
964 StringRef &ErrInfo) const {
965 uint16_t Opcode = MI->getOpcode();
966 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
967 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
968 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
969 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
971 // Make sure the number of operands is correct.
972 const MCInstrDesc &Desc = get(Opcode);
973 if (!Desc.isVariadic() &&
974 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
975 ErrInfo = "Instruction has wrong number of operands.";
979 // Make sure the register classes are correct
980 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
981 switch (Desc.OpInfo[i].OperandType) {
982 case MCOI::OPERAND_REGISTER: {
983 if ((MI->getOperand(i).isImm() || MI->getOperand(i).isFPImm()) &&
984 !isImmOperandLegal(MI, i, MI->getOperand(i))) {
985 ErrInfo = "Illegal immediate value for operand.";
990 case MCOI::OPERAND_IMMEDIATE:
991 // Check if this operand is an immediate.
992 // FrameIndex operands will be replaced by immediates, so they are
994 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm() &&
995 !MI->getOperand(i).isFI()) {
996 ErrInfo = "Expected immediate, but got non-immediate";
1004 if (!MI->getOperand(i).isReg())
1007 int RegClass = Desc.OpInfo[i].RegClass;
1008 if (RegClass != -1) {
1009 unsigned Reg = MI->getOperand(i).getReg();
1010 if (TargetRegisterInfo::isVirtualRegister(Reg))
1013 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1014 if (!RC->contains(Reg)) {
1015 ErrInfo = "Operand has incorrect register class.";
1023 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
1024 unsigned ConstantBusCount = 0;
1025 unsigned SGPRUsed = AMDGPU::NoRegister;
1026 for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
1027 const MachineOperand &MO = MI->getOperand(i);
1028 if (usesConstantBus(MRI, MO)) {
1030 if (MO.getReg() != SGPRUsed)
1032 SGPRUsed = MO.getReg();
1038 if (ConstantBusCount > 1) {
1039 ErrInfo = "VOP* instruction uses the constant bus more than once";
1044 // Verify SRC1 for VOP2 and VOPC
1045 if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
1046 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1047 if (Src1.isImm() || Src1.isFPImm()) {
1048 ErrInfo = "VOP[2C] src1 cannot be an immediate.";
1054 if (isVOP3(Opcode)) {
1055 if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
1056 ErrInfo = "VOP3 src0 cannot be a literal constant.";
1059 if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
1060 ErrInfo = "VOP3 src1 cannot be a literal constant.";
1063 if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
1064 ErrInfo = "VOP3 src2 cannot be a literal constant.";
1069 // Verify misc. restrictions on specific instructions.
1070 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1071 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1074 const MachineOperand &Src0 = MI->getOperand(2);
1075 const MachineOperand &Src1 = MI->getOperand(3);
1076 const MachineOperand &Src2 = MI->getOperand(4);
1077 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1078 if (!compareMachineOp(Src0, Src1) &&
1079 !compareMachineOp(Src0, Src2)) {
1080 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1089 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1090 switch (MI.getOpcode()) {
1091 default: return AMDGPU::INSTRUCTION_LIST_END;
1092 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1093 case AMDGPU::COPY: return AMDGPU::COPY;
1094 case AMDGPU::PHI: return AMDGPU::PHI;
1095 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1096 case AMDGPU::S_MOV_B32:
1097 return MI.getOperand(1).isReg() ?
1098 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1099 case AMDGPU::S_ADD_I32:
1100 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1101 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1102 case AMDGPU::S_SUB_I32:
1103 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1104 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1105 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1106 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1107 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1108 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1109 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1110 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1111 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1112 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1113 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1114 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1115 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1116 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1117 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1118 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1119 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1120 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1121 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1122 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1123 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1124 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1125 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1126 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1127 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1128 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1129 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1130 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1131 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1132 case AMDGPU::S_LOAD_DWORD_IMM:
1133 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1134 case AMDGPU::S_LOAD_DWORDX2_IMM:
1135 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1136 case AMDGPU::S_LOAD_DWORDX4_IMM:
1137 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1138 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e32;
1139 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1140 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1144 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1145 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1148 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1149 unsigned OpNo) const {
1150 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1151 const MCInstrDesc &Desc = get(MI.getOpcode());
1152 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1153 Desc.OpInfo[OpNo].RegClass == -1)
1154 return MRI.getRegClass(MI.getOperand(OpNo).getReg());
1156 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1157 return RI.getRegClass(RCID);
1160 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1161 switch (MI.getOpcode()) {
1163 case AMDGPU::REG_SEQUENCE:
1165 case AMDGPU::INSERT_SUBREG:
1166 return RI.hasVGPRs(getOpRegClass(MI, 0));
1168 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1172 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1173 MachineBasicBlock::iterator I = MI;
1174 MachineOperand &MO = MI->getOperand(OpIdx);
1175 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1176 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1177 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1178 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1180 Opcode = AMDGPU::COPY;
1181 } else if (RI.isSGPRClass(RC)) {
1182 Opcode = AMDGPU::S_MOV_B32;
1185 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1186 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC)) {
1187 VRC = &AMDGPU::VReg_64RegClass;
1189 VRC = &AMDGPU::VReg_32RegClass;
1191 unsigned Reg = MRI.createVirtualRegister(VRC);
1192 BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
1193 Reg).addOperand(MO);
1194 MO.ChangeToRegister(Reg, false);
1197 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1198 MachineRegisterInfo &MRI,
1199 MachineOperand &SuperReg,
1200 const TargetRegisterClass *SuperRC,
1202 const TargetRegisterClass *SubRC)
1204 assert(SuperReg.isReg());
1206 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1207 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1209 // Just in case the super register is itself a sub-register, copy it to a new
1210 // value so we don't need to worry about merging its subreg index with the
1211 // SubIdx passed to this function. The register coalescer should be able to
1212 // eliminate this extra copy.
1213 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
1215 .addOperand(SuperReg);
1217 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
1219 .addReg(NewSuperReg, 0, SubIdx);
1223 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1224 MachineBasicBlock::iterator MII,
1225 MachineRegisterInfo &MRI,
1227 const TargetRegisterClass *SuperRC,
1229 const TargetRegisterClass *SubRC) const {
1231 // XXX - Is there a better way to do this?
1232 if (SubIdx == AMDGPU::sub0)
1233 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1234 if (SubIdx == AMDGPU::sub1)
1235 return MachineOperand::CreateImm(Op.getImm() >> 32);
1237 llvm_unreachable("Unhandled register index for immediate");
1240 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1242 return MachineOperand::CreateReg(SubReg, false);
1245 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
1246 MachineBasicBlock::iterator MI,
1247 MachineRegisterInfo &MRI,
1248 const TargetRegisterClass *RC,
1249 const MachineOperand &Op) const {
1250 MachineBasicBlock *MBB = MI->getParent();
1251 DebugLoc DL = MI->getDebugLoc();
1252 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1253 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1254 unsigned Dst = MRI.createVirtualRegister(RC);
1256 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1258 .addImm(Op.getImm() & 0xFFFFFFFF);
1259 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1261 .addImm(Op.getImm() >> 32);
1263 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
1265 .addImm(AMDGPU::sub0)
1267 .addImm(AMDGPU::sub1);
1269 Worklist.push_back(Lo);
1270 Worklist.push_back(Hi);
1275 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1276 const MachineOperand *MO) const {
1277 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1278 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1279 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1280 const TargetRegisterClass *DefinedRC =
1281 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1283 MO = &MI->getOperand(OpIdx);
1285 if (usesConstantBus(MRI, *MO)) {
1286 unsigned SGPRUsed = MO->isReg() ? MO->getReg() : AMDGPU::NoRegister;
1287 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1290 if (usesConstantBus(MRI, MI->getOperand(i)) &&
1291 MI->getOperand(i).isReg() && MI->getOperand(i).getReg() != SGPRUsed) {
1299 const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg());
1300 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass));
1304 // Handle non-register types that are treated like immediates.
1305 assert(MO->isImm() || MO->isFPImm() || MO->isTargetIndex() || MO->isFI());
1308 // This operand expects an immediate.
1312 return isImmOperandLegal(MI, OpIdx, *MO);
1315 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1316 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1318 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1319 AMDGPU::OpName::src0);
1320 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1321 AMDGPU::OpName::src1);
1322 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1323 AMDGPU::OpName::src2);
1326 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1328 if (!isOperandLegal(MI, Src0Idx))
1329 legalizeOpWithMove(MI, Src0Idx);
1332 if (isOperandLegal(MI, Src1Idx))
1335 // Usually src0 of VOP2 instructions allow more types of inputs
1336 // than src1, so try to commute the instruction to decrease our
1337 // chances of having to insert a MOV instruction to legalize src1.
1338 if (MI->isCommutable()) {
1339 if (commuteInstruction(MI))
1340 // If we are successful in commuting, then we know MI is legal, so
1345 legalizeOpWithMove(MI, Src1Idx);
1349 // XXX - Do any VOP3 instructions read VCC?
1351 if (isVOP3(MI->getOpcode())) {
1352 int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx};
1353 unsigned SGPRReg = AMDGPU::NoRegister;
1354 for (unsigned i = 0; i < 3; ++i) {
1355 int Idx = VOP3Idx[i];
1358 MachineOperand &MO = MI->getOperand(Idx);
1361 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1362 continue; // VGPRs are legal
1364 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1366 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1367 SGPRReg = MO.getReg();
1368 // We can use one SGPR in each VOP3 instruction.
1371 } else if (!isLiteralConstant(MO)) {
1372 // If it is not a register and not a literal constant, then it must be
1373 // an inline constant which is always legal.
1376 // If we make it this far, then the operand is not legal and we must
1378 legalizeOpWithMove(MI, Idx);
1382 // Legalize REG_SEQUENCE and PHI
1383 // The register class of the operands much be the same type as the register
1384 // class of the output.
1385 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
1386 MI->getOpcode() == AMDGPU::PHI) {
1387 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1388 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1389 if (!MI->getOperand(i).isReg() ||
1390 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1392 const TargetRegisterClass *OpRC =
1393 MRI.getRegClass(MI->getOperand(i).getReg());
1394 if (RI.hasVGPRs(OpRC)) {
1401 // If any of the operands are VGPR registers, then they all most be
1402 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1404 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1407 VRC = RI.getEquivalentVGPRClass(SRC);
1414 // Update all the operands so they have the same type.
1415 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1416 if (!MI->getOperand(i).isReg() ||
1417 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1419 unsigned DstReg = MRI.createVirtualRegister(RC);
1420 MachineBasicBlock *InsertBB;
1421 MachineBasicBlock::iterator Insert;
1422 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1423 InsertBB = MI->getParent();
1426 // MI is a PHI instruction.
1427 InsertBB = MI->getOperand(i + 1).getMBB();
1428 Insert = InsertBB->getFirstTerminator();
1430 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1431 get(AMDGPU::COPY), DstReg)
1432 .addOperand(MI->getOperand(i));
1433 MI->getOperand(i).setReg(DstReg);
1437 // Legalize INSERT_SUBREG
1438 // src0 must have the same register class as dst
1439 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1440 unsigned Dst = MI->getOperand(0).getReg();
1441 unsigned Src0 = MI->getOperand(1).getReg();
1442 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1443 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1444 if (DstRC != Src0RC) {
1445 MachineBasicBlock &MBB = *MI->getParent();
1446 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1447 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1449 MI->getOperand(1).setReg(NewSrc0);
1454 // Legalize MUBUF* instructions
1455 // FIXME: If we start using the non-addr64 instructions for compute, we
1456 // may need to legalize them here.
1458 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1459 if (SRsrcIdx != -1) {
1460 // We have an MUBUF instruction
1461 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1462 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1463 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1464 RI.getRegClass(SRsrcRC))) {
1465 // The operands are legal.
1466 // FIXME: We may need to legalize operands besided srsrc.
1470 MachineBasicBlock &MBB = *MI->getParent();
1471 // Extract the the ptr from the resource descriptor.
1473 // SRsrcPtrLo = srsrc:sub0
1474 unsigned SRsrcPtrLo = buildExtractSubReg(MI, MRI, *SRsrc,
1475 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
1477 // SRsrcPtrHi = srsrc:sub1
1478 unsigned SRsrcPtrHi = buildExtractSubReg(MI, MRI, *SRsrc,
1479 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
1481 // Create an empty resource descriptor
1482 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1483 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1484 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1485 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1488 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1492 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1493 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1495 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1497 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1498 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1500 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1502 // NewSRsrc = {Zero64, SRsrcFormat}
1503 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1506 .addImm(AMDGPU::sub0_sub1)
1507 .addReg(SRsrcFormatLo)
1508 .addImm(AMDGPU::sub2)
1509 .addReg(SRsrcFormatHi)
1510 .addImm(AMDGPU::sub3);
1512 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1513 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1514 unsigned NewVAddrLo;
1515 unsigned NewVAddrHi;
1517 // This is already an ADDR64 instruction so we need to add the pointer
1518 // extracted from the resource descriptor to the current value of VAddr.
1519 NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1520 NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1522 // NewVaddrLo = SRsrcPtrLo + VAddr:sub0
1523 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
1526 .addReg(VAddr->getReg(), 0, AMDGPU::sub0)
1527 .addReg(AMDGPU::VCC, RegState::ImplicitDefine);
1529 // NewVaddrHi = SRsrcPtrHi + VAddr:sub1
1530 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
1533 .addReg(VAddr->getReg(), 0, AMDGPU::sub1)
1534 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
1535 .addReg(AMDGPU::VCC, RegState::Implicit);
1538 // This instructions is the _OFFSET variant, so we need to convert it to
1540 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
1541 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
1542 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
1543 assert(SOffset->isImm() && SOffset->getImm() == 0 && "Legalizing MUBUF "
1544 "with non-zero soffset is not implemented");
1547 // Create the new instruction.
1548 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
1549 MachineInstr *Addr64 =
1550 BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
1553 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
1554 // This will be replaced later
1555 // with the new value of vaddr.
1556 .addOperand(*Offset);
1558 MI->removeFromParent();
1561 NewVAddrLo = SRsrcPtrLo;
1562 NewVAddrHi = SRsrcPtrHi;
1563 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1564 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
1567 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1568 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1571 .addImm(AMDGPU::sub0)
1573 .addImm(AMDGPU::sub1);
1576 // Update the instruction to use NewVaddr
1577 VAddr->setReg(NewVAddr);
1578 // Update the instruction to use NewSRsrc
1579 SRsrc->setReg(NewSRsrc);
1583 void SIInstrInfo::splitSMRD(MachineInstr *MI,
1584 const TargetRegisterClass *HalfRC,
1585 unsigned HalfImmOp, unsigned HalfSGPROp,
1586 MachineInstr *&Lo, MachineInstr *&Hi) const {
1588 DebugLoc DL = MI->getDebugLoc();
1589 MachineBasicBlock *MBB = MI->getParent();
1590 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1591 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
1592 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
1593 unsigned HalfSize = HalfRC->getSize();
1594 const MachineOperand *OffOp =
1595 getNamedOperand(*MI, AMDGPU::OpName::offset);
1596 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
1599 // Handle the _IMM variant
1600 unsigned LoOffset = OffOp->getImm();
1601 unsigned HiOffset = LoOffset + (HalfSize / 4);
1602 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
1606 if (!isUInt<8>(HiOffset)) {
1607 unsigned OffsetSGPR =
1608 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1609 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
1610 .addImm(HiOffset << 2); // The immediate offset is in dwords,
1611 // but offset in register is in bytes.
1612 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
1614 .addReg(OffsetSGPR);
1616 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
1621 // Handle the _SGPR variant
1622 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
1623 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
1626 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1627 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
1630 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp))
1632 .addReg(OffsetSGPR);
1635 unsigned SubLo, SubHi;
1638 SubLo = AMDGPU::sub0;
1639 SubHi = AMDGPU::sub1;
1642 SubLo = AMDGPU::sub0_sub1;
1643 SubHi = AMDGPU::sub2_sub3;
1646 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
1647 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
1650 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
1651 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
1654 llvm_unreachable("Unhandled HalfSize");
1657 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE))
1658 .addOperand(MI->getOperand(0))
1665 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
1666 MachineBasicBlock *MBB = MI->getParent();
1667 switch (MI->getOpcode()) {
1668 case AMDGPU::S_LOAD_DWORD_IMM:
1669 case AMDGPU::S_LOAD_DWORD_SGPR:
1670 case AMDGPU::S_LOAD_DWORDX2_IMM:
1671 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1672 case AMDGPU::S_LOAD_DWORDX4_IMM:
1673 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1674 unsigned NewOpcode = getVALUOp(*MI);
1678 if (MI->getOperand(2).isReg()) {
1679 RegOffset = MI->getOperand(2).getReg();
1682 assert(MI->getOperand(2).isImm());
1683 // SMRD instructions take a dword offsets and MUBUF instructions
1684 // take a byte offset.
1685 ImmOffset = MI->getOperand(2).getImm() << 2;
1686 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1687 if (isUInt<12>(ImmOffset)) {
1688 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1692 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1699 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1700 unsigned DWord0 = RegOffset;
1701 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1702 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1703 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1705 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
1707 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
1708 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1709 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
1710 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1711 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
1713 .addImm(AMDGPU::sub0)
1715 .addImm(AMDGPU::sub1)
1717 .addImm(AMDGPU::sub2)
1719 .addImm(AMDGPU::sub3);
1720 MI->setDesc(get(NewOpcode));
1721 if (MI->getOperand(2).isReg()) {
1722 MI->getOperand(2).setReg(MI->getOperand(1).getReg());
1724 MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
1726 MI->getOperand(1).setReg(SRsrc);
1727 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
1729 const TargetRegisterClass *NewDstRC =
1730 RI.getRegClass(get(NewOpcode).OpInfo[0].RegClass);
1732 unsigned DstReg = MI->getOperand(0).getReg();
1733 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1734 MRI.replaceRegWith(DstReg, NewDstReg);
1737 case AMDGPU::S_LOAD_DWORDX8_IMM:
1738 case AMDGPU::S_LOAD_DWORDX8_SGPR: {
1739 MachineInstr *Lo, *Hi;
1740 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
1741 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
1742 MI->eraseFromParent();
1743 moveSMRDToVALU(Lo, MRI);
1744 moveSMRDToVALU(Hi, MRI);
1748 case AMDGPU::S_LOAD_DWORDX16_IMM:
1749 case AMDGPU::S_LOAD_DWORDX16_SGPR: {
1750 MachineInstr *Lo, *Hi;
1751 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
1752 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
1753 MI->eraseFromParent();
1754 moveSMRDToVALU(Lo, MRI);
1755 moveSMRDToVALU(Hi, MRI);
1761 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
1762 SmallVector<MachineInstr *, 128> Worklist;
1763 Worklist.push_back(&TopInst);
1765 while (!Worklist.empty()) {
1766 MachineInstr *Inst = Worklist.pop_back_val();
1767 MachineBasicBlock *MBB = Inst->getParent();
1768 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1770 unsigned Opcode = Inst->getOpcode();
1771 unsigned NewOpcode = getVALUOp(*Inst);
1773 // Handle some special cases
1776 if (isSMRD(Inst->getOpcode())) {
1777 moveSMRDToVALU(Inst, MRI);
1780 case AMDGPU::S_MOV_B64: {
1781 DebugLoc DL = Inst->getDebugLoc();
1783 // If the source operand is a register we can replace this with a
1785 if (Inst->getOperand(1).isReg()) {
1786 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
1787 .addOperand(Inst->getOperand(0))
1788 .addOperand(Inst->getOperand(1));
1789 Worklist.push_back(Copy);
1791 // Otherwise, we need to split this into two movs, because there is
1792 // no 64-bit VALU move instruction.
1793 unsigned Reg = Inst->getOperand(0).getReg();
1794 unsigned Dst = split64BitImm(Worklist,
1797 MRI.getRegClass(Reg),
1798 Inst->getOperand(1));
1799 MRI.replaceRegWith(Reg, Dst);
1801 Inst->eraseFromParent();
1804 case AMDGPU::S_AND_B64:
1805 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32);
1806 Inst->eraseFromParent();
1809 case AMDGPU::S_OR_B64:
1810 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32);
1811 Inst->eraseFromParent();
1814 case AMDGPU::S_XOR_B64:
1815 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32);
1816 Inst->eraseFromParent();
1819 case AMDGPU::S_NOT_B64:
1820 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
1821 Inst->eraseFromParent();
1824 case AMDGPU::S_BCNT1_I32_B64:
1825 splitScalar64BitBCNT(Worklist, Inst);
1826 Inst->eraseFromParent();
1829 case AMDGPU::S_BFE_U64:
1830 case AMDGPU::S_BFE_I64:
1831 case AMDGPU::S_BFM_B64:
1832 llvm_unreachable("Moving this op to VALU not implemented");
1835 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
1836 // We cannot move this instruction to the VALU, so we should try to
1837 // legalize its operands instead.
1838 legalizeOperands(Inst);
1842 // Use the new VALU Opcode.
1843 const MCInstrDesc &NewDesc = get(NewOpcode);
1844 Inst->setDesc(NewDesc);
1846 // Remove any references to SCC. Vector instructions can't read from it, and
1847 // We're just about to add the implicit use / defs of VCC, and we don't want
1849 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
1850 MachineOperand &Op = Inst->getOperand(i);
1851 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
1852 Inst->RemoveOperand(i);
1855 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
1856 // We are converting these to a BFE, so we need to add the missing
1857 // operands for the size and offset.
1858 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
1859 Inst->addOperand(MachineOperand::CreateImm(0));
1860 Inst->addOperand(MachineOperand::CreateImm(Size));
1862 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
1863 // The VALU version adds the second operand to the result, so insert an
1865 Inst->addOperand(MachineOperand::CreateImm(0));
1868 addDescImplicitUseDef(NewDesc, Inst);
1870 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
1871 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
1872 // If we need to move this to VGPRs, we need to unpack the second operand
1873 // back into the 2 separate ones for bit offset and width.
1874 assert(OffsetWidthOp.isImm() &&
1875 "Scalar BFE is only implemented for constant width and offset");
1876 uint32_t Imm = OffsetWidthOp.getImm();
1878 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
1879 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
1880 Inst->RemoveOperand(2); // Remove old immediate.
1881 Inst->addOperand(MachineOperand::CreateImm(Offset));
1882 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
1885 // Update the destination register class.
1887 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
1890 // For target instructions, getOpRegClass just returns the virtual
1891 // register class associated with the operand, so we need to find an
1892 // equivalent VGPR register class in order to move the instruction to the
1896 case AMDGPU::REG_SEQUENCE:
1897 case AMDGPU::INSERT_SUBREG:
1898 if (RI.hasVGPRs(NewDstRC))
1900 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
1908 unsigned DstReg = Inst->getOperand(0).getReg();
1909 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1910 MRI.replaceRegWith(DstReg, NewDstReg);
1912 // Legalize the operands
1913 legalizeOperands(Inst);
1915 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
1916 E = MRI.use_end(); I != E; ++I) {
1917 MachineInstr &UseMI = *I->getParent();
1918 if (!canReadVGPR(UseMI, I.getOperandNo())) {
1919 Worklist.push_back(&UseMI);
1925 //===----------------------------------------------------------------------===//
1926 // Indirect addressing callbacks
1927 //===----------------------------------------------------------------------===//
1929 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
1930 unsigned Channel) const {
1931 assert(Channel == 0);
1935 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
1936 return &AMDGPU::VReg_32RegClass;
1939 void SIInstrInfo::splitScalar64BitUnaryOp(
1940 SmallVectorImpl<MachineInstr *> &Worklist,
1942 unsigned Opcode) const {
1943 MachineBasicBlock &MBB = *Inst->getParent();
1944 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1946 MachineOperand &Dest = Inst->getOperand(0);
1947 MachineOperand &Src0 = Inst->getOperand(1);
1948 DebugLoc DL = Inst->getDebugLoc();
1950 MachineBasicBlock::iterator MII = Inst;
1952 const MCInstrDesc &InstDesc = get(Opcode);
1953 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1954 MRI.getRegClass(Src0.getReg()) :
1955 &AMDGPU::SGPR_32RegClass;
1957 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
1959 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1960 AMDGPU::sub0, Src0SubRC);
1962 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
1963 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
1965 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
1966 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
1967 .addOperand(SrcReg0Sub0);
1969 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1970 AMDGPU::sub1, Src0SubRC);
1972 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
1973 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
1974 .addOperand(SrcReg0Sub1);
1976 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
1977 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
1979 .addImm(AMDGPU::sub0)
1981 .addImm(AMDGPU::sub1);
1983 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
1985 // Try to legalize the operands in case we need to swap the order to keep it
1987 Worklist.push_back(LoHalf);
1988 Worklist.push_back(HiHalf);
1991 void SIInstrInfo::splitScalar64BitBinaryOp(
1992 SmallVectorImpl<MachineInstr *> &Worklist,
1994 unsigned Opcode) const {
1995 MachineBasicBlock &MBB = *Inst->getParent();
1996 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1998 MachineOperand &Dest = Inst->getOperand(0);
1999 MachineOperand &Src0 = Inst->getOperand(1);
2000 MachineOperand &Src1 = Inst->getOperand(2);
2001 DebugLoc DL = Inst->getDebugLoc();
2003 MachineBasicBlock::iterator MII = Inst;
2005 const MCInstrDesc &InstDesc = get(Opcode);
2006 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2007 MRI.getRegClass(Src0.getReg()) :
2008 &AMDGPU::SGPR_32RegClass;
2010 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2011 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2012 MRI.getRegClass(Src1.getReg()) :
2013 &AMDGPU::SGPR_32RegClass;
2015 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2017 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2018 AMDGPU::sub0, Src0SubRC);
2019 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2020 AMDGPU::sub0, Src1SubRC);
2022 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2023 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2025 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2026 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2027 .addOperand(SrcReg0Sub0)
2028 .addOperand(SrcReg1Sub0);
2030 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2031 AMDGPU::sub1, Src0SubRC);
2032 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2033 AMDGPU::sub1, Src1SubRC);
2035 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2036 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2037 .addOperand(SrcReg0Sub1)
2038 .addOperand(SrcReg1Sub1);
2040 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2041 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2043 .addImm(AMDGPU::sub0)
2045 .addImm(AMDGPU::sub1);
2047 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2049 // Try to legalize the operands in case we need to swap the order to keep it
2051 Worklist.push_back(LoHalf);
2052 Worklist.push_back(HiHalf);
2055 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2056 MachineInstr *Inst) const {
2057 MachineBasicBlock &MBB = *Inst->getParent();
2058 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2060 MachineBasicBlock::iterator MII = Inst;
2061 DebugLoc DL = Inst->getDebugLoc();
2063 MachineOperand &Dest = Inst->getOperand(0);
2064 MachineOperand &Src = Inst->getOperand(1);
2066 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e32);
2067 const TargetRegisterClass *SrcRC = Src.isReg() ?
2068 MRI.getRegClass(Src.getReg()) :
2069 &AMDGPU::SGPR_32RegClass;
2071 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2072 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2074 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2076 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2077 AMDGPU::sub0, SrcSubRC);
2078 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2079 AMDGPU::sub1, SrcSubRC);
2081 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg)
2082 .addOperand(SrcRegSub0)
2085 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2086 .addOperand(SrcRegSub1)
2089 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2091 Worklist.push_back(First);
2092 Worklist.push_back(Second);
2095 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
2096 MachineInstr *Inst) const {
2097 // Add the implict and explicit register definitions.
2098 if (NewDesc.ImplicitUses) {
2099 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
2100 unsigned Reg = NewDesc.ImplicitUses[i];
2101 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
2105 if (NewDesc.ImplicitDefs) {
2106 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
2107 unsigned Reg = NewDesc.ImplicitDefs[i];
2108 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
2113 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2114 MachineBasicBlock *MBB,
2115 MachineBasicBlock::iterator I,
2117 unsigned Address, unsigned OffsetReg) const {
2118 const DebugLoc &DL = MBB->findDebugLoc(I);
2119 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
2120 getIndirectIndexBegin(*MBB->getParent()));
2122 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2123 .addReg(IndirectBaseReg, RegState::Define)
2124 .addOperand(I->getOperand(0))
2125 .addReg(IndirectBaseReg)
2131 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2132 MachineBasicBlock *MBB,
2133 MachineBasicBlock::iterator I,
2135 unsigned Address, unsigned OffsetReg) const {
2136 const DebugLoc &DL = MBB->findDebugLoc(I);
2137 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
2138 getIndirectIndexBegin(*MBB->getParent()));
2140 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
2141 .addOperand(I->getOperand(0))
2142 .addOperand(I->getOperand(1))
2143 .addReg(IndirectBaseReg)
2149 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2150 const MachineFunction &MF) const {
2151 int End = getIndirectIndexEnd(MF);
2152 int Begin = getIndirectIndexBegin(MF);
2158 for (int Index = Begin; Index <= End; ++Index)
2159 Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
2161 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2162 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
2164 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
2165 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
2167 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
2168 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
2170 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
2171 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
2173 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
2174 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
2177 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
2178 unsigned OperandName) const {
2179 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
2183 return &MI.getOperand(Idx);