1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/MC/MCInstrDesc.h"
26 SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
27 : AMDGPUInstrInfo(tm),
30 //===----------------------------------------------------------------------===//
31 // TargetInstrInfo callbacks
32 //===----------------------------------------------------------------------===//
35 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
36 MachineBasicBlock::iterator MI, DebugLoc DL,
37 unsigned DestReg, unsigned SrcReg,
40 // If we are trying to copy to or from SCC, there is a bug somewhere else in
41 // the backend. While it may be theoretically possible to do this, it should
42 // never be necessary.
43 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
45 static const int16_t Sub0_15[] = {
46 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
47 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
48 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
49 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
52 static const int16_t Sub0_7[] = {
53 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
54 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
57 static const int16_t Sub0_3[] = {
58 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
61 static const int16_t Sub0_2[] = {
62 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
65 static const int16_t Sub0_1[] = {
66 AMDGPU::sub0, AMDGPU::sub1, 0
70 const int16_t *SubIndices;
72 if (AMDGPU::M0 == DestReg) {
73 // Check if M0 isn't already set to this value
74 for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
75 I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
77 if (!I->definesRegister(AMDGPU::M0))
80 unsigned Opc = I->getOpcode();
81 if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
84 if (!I->readsRegister(SrcReg))
87 // The copy isn't necessary
92 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
93 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
94 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
95 .addReg(SrcReg, getKillRegState(KillSrc));
98 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
99 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
100 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
101 .addReg(SrcReg, getKillRegState(KillSrc));
104 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
105 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
106 Opcode = AMDGPU::S_MOV_B32;
109 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
110 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
111 Opcode = AMDGPU::S_MOV_B32;
114 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
115 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
116 Opcode = AMDGPU::S_MOV_B32;
117 SubIndices = Sub0_15;
119 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
120 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
121 AMDGPU::SReg_32RegClass.contains(SrcReg));
122 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
123 .addReg(SrcReg, getKillRegState(KillSrc));
126 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
127 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
128 AMDGPU::SReg_64RegClass.contains(SrcReg));
129 Opcode = AMDGPU::V_MOV_B32_e32;
132 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
133 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
134 Opcode = AMDGPU::V_MOV_B32_e32;
137 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
138 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
139 AMDGPU::SReg_128RegClass.contains(SrcReg));
140 Opcode = AMDGPU::V_MOV_B32_e32;
143 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
144 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
145 AMDGPU::SReg_256RegClass.contains(SrcReg));
146 Opcode = AMDGPU::V_MOV_B32_e32;
149 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
150 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
151 AMDGPU::SReg_512RegClass.contains(SrcReg));
152 Opcode = AMDGPU::V_MOV_B32_e32;
153 SubIndices = Sub0_15;
156 llvm_unreachable("Can't copy register!");
159 while (unsigned SubIdx = *SubIndices++) {
160 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
161 get(Opcode), RI.getSubReg(DestReg, SubIdx));
163 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
166 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
170 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
173 // Try to map original to commuted opcode
174 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
177 // Try to map commuted to original opcode
178 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
184 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
185 MachineBasicBlock::iterator MI,
186 unsigned SrcReg, bool isKill,
188 const TargetRegisterClass *RC,
189 const TargetRegisterInfo *TRI) const {
190 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
191 SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
192 DebugLoc DL = MBB.findDebugLoc(MI);
193 unsigned KillFlag = isKill ? RegState::Kill : 0;
195 if (TRI->getCommonSubClass(RC, &AMDGPU::SGPR_32RegClass)) {
196 unsigned Lane = MFI->SpillTracker.getNextLane(MRI);
197 BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32),
198 MFI->SpillTracker.LaneVGPR)
199 .addReg(SrcReg, KillFlag)
201 MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR,
204 for (unsigned i = 0, e = RC->getSize() / 4; i != e; ++i) {
205 unsigned SubReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
206 BuildMI(MBB, MI, MBB.findDebugLoc(MI), get(AMDGPU::COPY), SubReg)
207 .addReg(SrcReg, 0, RI.getSubRegFromChannel(i));
208 storeRegToStackSlot(MBB, MI, SubReg, isKill, FrameIndex + i,
209 &AMDGPU::SReg_32RegClass, TRI);
214 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
215 MachineBasicBlock::iterator MI,
216 unsigned DestReg, int FrameIndex,
217 const TargetRegisterClass *RC,
218 const TargetRegisterInfo *TRI) const {
219 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
220 SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
221 DebugLoc DL = MBB.findDebugLoc(MI);
222 if (TRI->getCommonSubClass(RC, &AMDGPU::SReg_32RegClass)) {
223 SIMachineFunctionInfo::SpilledReg Spill =
224 MFI->SpillTracker.getSpilledReg(FrameIndex);
226 BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), DestReg)
230 for (unsigned i = 0, e = RC->getSize() / 4; i != e; ++i) {
231 unsigned Flags = RegState::Define;
233 Flags |= RegState::Undef;
235 unsigned SubReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
236 loadRegFromStackSlot(MBB, MI, SubReg, FrameIndex + i,
237 &AMDGPU::SReg_32RegClass, TRI);
238 BuildMI(MBB, MI, DL, get(AMDGPU::COPY))
239 .addReg(DestReg, Flags, RI.getSubRegFromChannel(i))
245 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
248 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
249 if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg())
252 // Cannot commute VOP2 if src0 is SGPR.
253 if (isVOP2(MI->getOpcode()) && MI->getOperand(1).isReg() &&
254 RI.isSGPRClass(MRI.getRegClass(MI->getOperand(1).getReg())))
257 if (!MI->getOperand(2).isReg()) {
258 // XXX: Commute instructions with FPImm operands
259 if (NewMI || MI->getOperand(2).isFPImm() ||
260 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
264 // XXX: Commute VOP3 instructions with abs and neg set.
265 if (isVOP3(MI->getOpcode()) &&
266 (MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
267 AMDGPU::OpName::abs)).getImm() ||
268 MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
269 AMDGPU::OpName::neg)).getImm()))
272 unsigned Reg = MI->getOperand(1).getReg();
273 unsigned SubReg = MI->getOperand(1).getSubReg();
274 MI->getOperand(1).ChangeToImmediate(MI->getOperand(2).getImm());
275 MI->getOperand(2).ChangeToRegister(Reg, false);
276 MI->getOperand(2).setSubReg(SubReg);
278 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
282 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
287 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
288 MachineBasicBlock::iterator I,
290 unsigned SrcReg) const {
291 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
292 DstReg) .addReg(SrcReg);
295 bool SIInstrInfo::isMov(unsigned Opcode) const {
297 default: return false;
298 case AMDGPU::S_MOV_B32:
299 case AMDGPU::S_MOV_B64:
300 case AMDGPU::V_MOV_B32_e32:
301 case AMDGPU::V_MOV_B32_e64:
307 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
308 return RC != &AMDGPU::EXECRegRegClass;
312 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
313 AliasAnalysis *AA) const {
314 switch(MI->getOpcode()) {
315 default: return AMDGPUInstrInfo::isTriviallyReMaterializable(MI, AA);
316 case AMDGPU::S_MOV_B32:
317 case AMDGPU::S_MOV_B64:
318 case AMDGPU::V_MOV_B32_e32:
319 return MI->getOperand(1).isImm();
325 // Helper function generated by tablegen. We are wrapping this with
326 // an SIInstrInfo function that reutrns bool rather than int.
327 int isDS(uint16_t Opcode);
331 bool SIInstrInfo::isDS(uint16_t Opcode) const {
332 return ::AMDGPU::isDS(Opcode) != -1;
335 int SIInstrInfo::isMIMG(uint16_t Opcode) const {
336 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
339 int SIInstrInfo::isSMRD(uint16_t Opcode) const {
340 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
343 bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
344 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
347 bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
348 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
351 bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
352 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
355 bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
356 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
359 bool SIInstrInfo::isSALUInstr(const MachineInstr &MI) const {
360 return get(MI.getOpcode()).TSFlags & SIInstrFlags::SALU;
363 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
364 int32_t Val = Imm.getSExtValue();
365 if (Val >= -16 && Val <= 64)
368 // The actual type of the operand does not seem to matter as long
369 // as the bits match one of the inline immediate values. For example:
371 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
372 // so it is a legal inline immediate.
374 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
375 // floating-point, so it is a legal inline immediate.
377 return (APInt::floatToBits(0.0f) == Imm) ||
378 (APInt::floatToBits(1.0f) == Imm) ||
379 (APInt::floatToBits(-1.0f) == Imm) ||
380 (APInt::floatToBits(0.5f) == Imm) ||
381 (APInt::floatToBits(-0.5f) == Imm) ||
382 (APInt::floatToBits(2.0f) == Imm) ||
383 (APInt::floatToBits(-2.0f) == Imm) ||
384 (APInt::floatToBits(4.0f) == Imm) ||
385 (APInt::floatToBits(-4.0f) == Imm);
388 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
390 return isInlineConstant(APInt(32, MO.getImm(), true));
393 APFloat FpImm = MO.getFPImm()->getValueAPF();
394 return isInlineConstant(FpImm.bitcastToAPInt());
400 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
401 return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO);
404 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
405 StringRef &ErrInfo) const {
406 uint16_t Opcode = MI->getOpcode();
407 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
408 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
409 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
411 // Make sure the number of operands is correct.
412 const MCInstrDesc &Desc = get(Opcode);
413 if (!Desc.isVariadic() &&
414 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
415 ErrInfo = "Instruction has wrong number of operands.";
419 // Make sure the register classes are correct
420 for (unsigned i = 0, e = Desc.getNumOperands(); i != e; ++i) {
421 switch (Desc.OpInfo[i].OperandType) {
422 case MCOI::OPERAND_REGISTER:
424 case MCOI::OPERAND_IMMEDIATE:
425 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm()) {
426 ErrInfo = "Expected immediate, but got non-immediate";
434 if (!MI->getOperand(i).isReg())
437 int RegClass = Desc.OpInfo[i].RegClass;
438 if (RegClass != -1) {
439 unsigned Reg = MI->getOperand(i).getReg();
440 if (TargetRegisterInfo::isVirtualRegister(Reg))
443 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
444 if (!RC->contains(Reg)) {
445 ErrInfo = "Operand has incorrect register class.";
453 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
454 unsigned ConstantBusCount = 0;
455 unsigned SGPRUsed = AMDGPU::NoRegister;
456 for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
457 const MachineOperand &MO = MI->getOperand(i);
458 if (MO.isReg() && MO.isUse() &&
459 !TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
461 // EXEC register uses the constant bus.
462 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
465 // SGPRs use the constant bus
466 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
468 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
469 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
470 if (SGPRUsed != MO.getReg()) {
472 SGPRUsed = MO.getReg();
476 // Literal constants use the constant bus.
477 if (isLiteralConstant(MO))
480 if (ConstantBusCount > 1) {
481 ErrInfo = "VOP* instruction uses the constant bus more than once";
486 // Verify SRC1 for VOP2 and VOPC
487 if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
488 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
489 if (Src1.isImm() || Src1.isFPImm()) {
490 ErrInfo = "VOP[2C] src1 cannot be an immediate.";
496 if (isVOP3(Opcode)) {
497 if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
498 ErrInfo = "VOP3 src0 cannot be a literal constant.";
501 if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
502 ErrInfo = "VOP3 src1 cannot be a literal constant.";
505 if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
506 ErrInfo = "VOP3 src2 cannot be a literal constant.";
513 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
514 switch (MI.getOpcode()) {
515 default: return AMDGPU::INSTRUCTION_LIST_END;
516 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
517 case AMDGPU::COPY: return AMDGPU::COPY;
518 case AMDGPU::PHI: return AMDGPU::PHI;
519 case AMDGPU::S_MOV_B32:
520 return MI.getOperand(1).isReg() ?
521 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
522 case AMDGPU::S_ADD_I32: return AMDGPU::V_ADD_I32_e32;
523 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
524 case AMDGPU::S_SUB_I32: return AMDGPU::V_SUB_I32_e32;
525 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
526 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
527 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
528 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
529 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
530 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
531 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
532 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
533 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
534 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
535 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
536 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
537 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
538 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
542 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
543 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
546 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
547 unsigned OpNo) const {
548 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
549 const MCInstrDesc &Desc = get(MI.getOpcode());
550 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
551 Desc.OpInfo[OpNo].RegClass == -1)
552 return MRI.getRegClass(MI.getOperand(OpNo).getReg());
554 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
555 return RI.getRegClass(RCID);
558 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
559 switch (MI.getOpcode()) {
561 case AMDGPU::REG_SEQUENCE:
562 return RI.hasVGPRs(getOpRegClass(MI, 0));
564 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
568 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
569 MachineBasicBlock::iterator I = MI;
570 MachineOperand &MO = MI->getOperand(OpIdx);
571 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
572 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
573 const TargetRegisterClass *RC = RI.getRegClass(RCID);
574 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
576 Opcode = AMDGPU::COPY;
577 } else if (RI.isSGPRClass(RC)) {
578 Opcode = AMDGPU::S_MOV_B32;
581 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
582 unsigned Reg = MRI.createVirtualRegister(VRC);
583 BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
585 MO.ChangeToRegister(Reg, false);
588 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
589 MachineRegisterInfo &MRI,
590 MachineOperand &SuperReg,
591 const TargetRegisterClass *SuperRC,
593 const TargetRegisterClass *SubRC)
595 assert(SuperReg.isReg());
597 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
598 unsigned SubReg = MRI.createVirtualRegister(SubRC);
600 // Just in case the super register is itself a sub-register, copy it to a new
601 // value so we don't need to wory about merging its subreg index with the
602 // SubIdx passed to this function. The register coalescer should be able to
603 // eliminate this extra copy.
604 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
606 .addOperand(SuperReg);
608 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
610 .addReg(NewSuperReg, 0, SubIdx);
614 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
615 MachineBasicBlock::iterator MII,
616 MachineRegisterInfo &MRI,
618 const TargetRegisterClass *SuperRC,
620 const TargetRegisterClass *SubRC) const {
622 // XXX - Is there a better way to do this?
623 if (SubIdx == AMDGPU::sub0)
624 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
625 if (SubIdx == AMDGPU::sub1)
626 return MachineOperand::CreateImm(Op.getImm() >> 32);
628 llvm_unreachable("Unhandled register index for immediate");
631 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
633 return MachineOperand::CreateReg(SubReg, false);
636 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
637 MachineBasicBlock::iterator MI,
638 MachineRegisterInfo &MRI,
639 const TargetRegisterClass *RC,
640 const MachineOperand &Op) const {
641 MachineBasicBlock *MBB = MI->getParent();
642 DebugLoc DL = MI->getDebugLoc();
643 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
644 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
645 unsigned Dst = MRI.createVirtualRegister(RC);
647 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
649 .addImm(Op.getImm() & 0xFFFFFFFF);
650 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
652 .addImm(Op.getImm() >> 32);
654 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
656 .addImm(AMDGPU::sub0)
658 .addImm(AMDGPU::sub1);
660 Worklist.push_back(Lo);
661 Worklist.push_back(Hi);
666 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
667 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
668 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
669 AMDGPU::OpName::src0);
670 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
671 AMDGPU::OpName::src1);
672 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
673 AMDGPU::OpName::src2);
676 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
677 MachineOperand &Src0 = MI->getOperand(Src0Idx);
678 MachineOperand &Src1 = MI->getOperand(Src1Idx);
680 // If the instruction implicitly reads VCC, we can't have any SGPR operands,
682 bool ReadsVCC = MI->readsRegister(AMDGPU::VCC, &RI);
683 if (ReadsVCC && Src0.isReg() &&
684 RI.isSGPRClass(MRI.getRegClass(Src0.getReg()))) {
685 legalizeOpWithMove(MI, Src0Idx);
689 if (ReadsVCC && Src1.isReg() &&
690 RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {
691 legalizeOpWithMove(MI, Src1Idx);
695 // Legalize VOP2 instructions where src1 is not a VGPR. An SGPR input must
696 // be the first operand, and there can only be one.
697 if (Src1.isImm() || Src1.isFPImm() ||
698 (Src1.isReg() && RI.isSGPRClass(MRI.getRegClass(Src1.getReg())))) {
699 if (MI->isCommutable()) {
700 if (commuteInstruction(MI))
703 legalizeOpWithMove(MI, Src1Idx);
707 // XXX - Do any VOP3 instructions read VCC?
709 if (isVOP3(MI->getOpcode())) {
710 int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx};
711 unsigned SGPRReg = AMDGPU::NoRegister;
712 for (unsigned i = 0; i < 3; ++i) {
713 int Idx = VOP3Idx[i];
716 MachineOperand &MO = MI->getOperand(Idx);
719 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
720 continue; // VGPRs are legal
722 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
724 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
725 SGPRReg = MO.getReg();
726 // We can use one SGPR in each VOP3 instruction.
729 } else if (!isLiteralConstant(MO)) {
730 // If it is not a register and not a literal constant, then it must be
731 // an inline constant which is always legal.
734 // If we make it this far, then the operand is not legal and we must
736 legalizeOpWithMove(MI, Idx);
740 // Legalize REG_SEQUENCE
741 // The register class of the operands much be the same type as the register
742 // class of the output.
743 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
744 const TargetRegisterClass *RC = NULL, *SRC = NULL, *VRC = NULL;
745 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
746 if (!MI->getOperand(i).isReg() ||
747 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
749 const TargetRegisterClass *OpRC =
750 MRI.getRegClass(MI->getOperand(i).getReg());
751 if (RI.hasVGPRs(OpRC)) {
758 // If any of the operands are VGPR registers, then they all most be
759 // otherwise we will create illegal VGPR->SGPR copies when legalizing
761 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
764 VRC = RI.getEquivalentVGPRClass(SRC);
771 // Update all the operands so they have the same type.
772 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
773 if (!MI->getOperand(i).isReg() ||
774 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
776 unsigned DstReg = MRI.createVirtualRegister(RC);
777 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
778 get(AMDGPU::COPY), DstReg)
779 .addOperand(MI->getOperand(i));
780 MI->getOperand(i).setReg(DstReg);
784 // Legalize MUBUF* instructions
785 // FIXME: If we start using the non-addr64 instructions for compute, we
786 // may need to legalize them here.
788 int SRsrcIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
789 AMDGPU::OpName::srsrc);
790 int VAddrIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
791 AMDGPU::OpName::vaddr);
792 if (SRsrcIdx != -1 && VAddrIdx != -1) {
793 const TargetRegisterClass *VAddrRC =
794 RI.getRegClass(get(MI->getOpcode()).OpInfo[VAddrIdx].RegClass);
796 if(VAddrRC->getSize() == 8 &&
797 MRI.getRegClass(MI->getOperand(SRsrcIdx).getReg()) != VAddrRC) {
798 // We have a MUBUF instruction that uses a 64-bit vaddr register and
799 // srsrc has the incorrect register class. In order to fix this, we
800 // need to extract the pointer from the resource descriptor (srsrc),
801 // add it to the value of vadd, then store the result in the vaddr
802 // operand. Then, we need to set the pointer field of the resource
803 // descriptor to zero.
805 MachineBasicBlock &MBB = *MI->getParent();
806 MachineOperand &SRsrcOp = MI->getOperand(SRsrcIdx);
807 MachineOperand &VAddrOp = MI->getOperand(VAddrIdx);
808 unsigned SRsrcPtrLo, SRsrcPtrHi, VAddrLo, VAddrHi;
809 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
810 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
811 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
812 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
813 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
814 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
815 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
817 // SRsrcPtrLo = srsrc:sub0
818 SRsrcPtrLo = buildExtractSubReg(MI, MRI, SRsrcOp,
819 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
821 // SRsrcPtrHi = srsrc:sub1
822 SRsrcPtrHi = buildExtractSubReg(MI, MRI, SRsrcOp,
823 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
825 // VAddrLo = vaddr:sub0
826 VAddrLo = buildExtractSubReg(MI, MRI, VAddrOp,
827 &AMDGPU::VReg_64RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
829 // VAddrHi = vaddr:sub1
830 VAddrHi = buildExtractSubReg(MI, MRI, VAddrOp,
831 &AMDGPU::VReg_64RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
833 // NewVaddrLo = SRsrcPtrLo + VAddrLo
834 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
838 .addReg(AMDGPU::VCC, RegState::Define | RegState::Implicit);
840 // NewVaddrHi = SRsrcPtrHi + VAddrHi
841 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
845 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
846 .addReg(AMDGPU::VCC, RegState::Implicit);
848 // NewVaddr = {NewVaddrHi, NewVaddrLo}
849 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
852 .addImm(AMDGPU::sub0)
854 .addImm(AMDGPU::sub1);
857 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
861 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
862 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
864 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
866 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
867 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
869 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
871 // NewSRsrc = {Zero64, SRsrcFormat}
872 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
875 .addImm(AMDGPU::sub0_sub1)
876 .addReg(SRsrcFormatLo)
877 .addImm(AMDGPU::sub2)
878 .addReg(SRsrcFormatHi)
879 .addImm(AMDGPU::sub3);
881 // Update the instruction to use NewVaddr
882 MI->getOperand(VAddrIdx).setReg(NewVAddr);
883 // Update the instruction to use NewSRsrc
884 MI->getOperand(SRsrcIdx).setReg(NewSRsrc);
889 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
890 SmallVector<MachineInstr *, 128> Worklist;
891 Worklist.push_back(&TopInst);
893 while (!Worklist.empty()) {
894 MachineInstr *Inst = Worklist.pop_back_val();
895 MachineBasicBlock *MBB = Inst->getParent();
896 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
898 // Handle some special cases
899 switch(Inst->getOpcode()) {
900 case AMDGPU::S_MOV_B64: {
901 DebugLoc DL = Inst->getDebugLoc();
903 // If the source operand is a register we can replace this with a
905 if (Inst->getOperand(1).isReg()) {
906 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
907 .addOperand(Inst->getOperand(0))
908 .addOperand(Inst->getOperand(1));
909 Worklist.push_back(Copy);
911 // Otherwise, we need to split this into two movs, because there is
912 // no 64-bit VALU move instruction.
913 unsigned Reg = Inst->getOperand(0).getReg();
914 unsigned Dst = split64BitImm(Worklist,
917 MRI.getRegClass(Reg),
918 Inst->getOperand(1));
919 MRI.replaceRegWith(Reg, Dst);
921 Inst->eraseFromParent();
924 case AMDGPU::S_AND_B64:
925 splitScalar64BitOp(Worklist, Inst, AMDGPU::S_AND_B32);
926 Inst->eraseFromParent();
929 case AMDGPU::S_OR_B64:
930 splitScalar64BitOp(Worklist, Inst, AMDGPU::S_OR_B32);
931 Inst->eraseFromParent();
934 case AMDGPU::S_XOR_B64:
935 splitScalar64BitOp(Worklist, Inst, AMDGPU::S_XOR_B32);
936 Inst->eraseFromParent();
939 case AMDGPU::S_NOT_B64:
940 splitScalar64BitOp(Worklist, Inst, AMDGPU::S_NOT_B32);
941 Inst->eraseFromParent();
944 case AMDGPU::S_BFE_U64:
945 case AMDGPU::S_BFE_I64:
946 case AMDGPU::S_BFM_B64:
947 llvm_unreachable("Moving this op to VALU not implemented");
950 unsigned NewOpcode = getVALUOp(*Inst);
951 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
952 // We cannot move this instruction to the VALU, so we should try to
953 // legalize its operands instead.
954 legalizeOperands(Inst);
958 // Use the new VALU Opcode.
959 const MCInstrDesc &NewDesc = get(NewOpcode);
960 Inst->setDesc(NewDesc);
962 // Remove any references to SCC. Vector instructions can't read from it, and
963 // We're just about to add the implicit use / defs of VCC, and we don't want
965 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
966 MachineOperand &Op = Inst->getOperand(i);
967 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
968 Inst->RemoveOperand(i);
971 // Add the implict and explicit register definitions.
972 if (NewDesc.ImplicitUses) {
973 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
974 unsigned Reg = NewDesc.ImplicitUses[i];
975 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
979 if (NewDesc.ImplicitDefs) {
980 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
981 unsigned Reg = NewDesc.ImplicitDefs[i];
982 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
986 legalizeOperands(Inst);
988 // Update the destination register class.
989 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
991 switch (Inst->getOpcode()) {
992 // For target instructions, getOpRegClass just returns the virtual
993 // register class associated with the operand, so we need to find an
994 // equivalent VGPR register class in order to move the instruction to the
998 case AMDGPU::REG_SEQUENCE:
999 if (RI.hasVGPRs(NewDstRC))
1001 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
1009 unsigned DstReg = Inst->getOperand(0).getReg();
1010 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1011 MRI.replaceRegWith(DstReg, NewDstReg);
1013 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
1014 E = MRI.use_end(); I != E; ++I) {
1015 MachineInstr &UseMI = *I->getParent();
1016 if (!canReadVGPR(UseMI, I.getOperandNo())) {
1017 Worklist.push_back(&UseMI);
1023 //===----------------------------------------------------------------------===//
1024 // Indirect addressing callbacks
1025 //===----------------------------------------------------------------------===//
1027 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
1028 unsigned Channel) const {
1029 assert(Channel == 0);
1033 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
1034 return &AMDGPU::VReg_32RegClass;
1037 void SIInstrInfo::splitScalar64BitOp(SmallVectorImpl<MachineInstr *> &Worklist,
1039 unsigned Opcode) const {
1040 MachineBasicBlock &MBB = *Inst->getParent();
1041 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1043 MachineOperand &Dest = Inst->getOperand(0);
1044 MachineOperand &Src0 = Inst->getOperand(1);
1045 MachineOperand &Src1 = Inst->getOperand(2);
1046 DebugLoc DL = Inst->getDebugLoc();
1048 MachineBasicBlock::iterator MII = Inst;
1050 const MCInstrDesc &InstDesc = get(Opcode);
1051 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1052 MRI.getRegClass(Src0.getReg()) :
1053 &AMDGPU::SGPR_32RegClass;
1055 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
1056 const TargetRegisterClass *Src1RC = Src1.isReg() ?
1057 MRI.getRegClass(Src1.getReg()) :
1058 &AMDGPU::SGPR_32RegClass;
1060 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
1062 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1063 AMDGPU::sub0, Src0SubRC);
1064 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
1065 AMDGPU::sub0, Src1SubRC);
1067 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
1068 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
1070 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
1071 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
1072 .addOperand(SrcReg0Sub0)
1073 .addOperand(SrcReg1Sub0);
1075 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1076 AMDGPU::sub1, Src0SubRC);
1077 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
1078 AMDGPU::sub1, Src1SubRC);
1080 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
1081 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
1082 .addOperand(SrcReg0Sub1)
1083 .addOperand(SrcReg1Sub1);
1085 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
1086 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
1088 .addImm(AMDGPU::sub0)
1090 .addImm(AMDGPU::sub1);
1092 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
1094 // Try to legalize the operands in case we need to swap the order to keep it
1096 Worklist.push_back(LoHalf);
1097 Worklist.push_back(HiHalf);
1100 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
1101 MachineBasicBlock *MBB,
1102 MachineBasicBlock::iterator I,
1104 unsigned Address, unsigned OffsetReg) const {
1105 const DebugLoc &DL = MBB->findDebugLoc(I);
1106 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1107 getIndirectIndexBegin(*MBB->getParent()));
1109 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
1110 .addReg(IndirectBaseReg, RegState::Define)
1111 .addOperand(I->getOperand(0))
1112 .addReg(IndirectBaseReg)
1118 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
1119 MachineBasicBlock *MBB,
1120 MachineBasicBlock::iterator I,
1122 unsigned Address, unsigned OffsetReg) const {
1123 const DebugLoc &DL = MBB->findDebugLoc(I);
1124 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1125 getIndirectIndexBegin(*MBB->getParent()));
1127 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
1128 .addOperand(I->getOperand(0))
1129 .addOperand(I->getOperand(1))
1130 .addReg(IndirectBaseReg)
1136 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
1137 const MachineFunction &MF) const {
1138 int End = getIndirectIndexEnd(MF);
1139 int Begin = getIndirectIndexBegin(MF);
1145 for (int Index = Begin; Index <= End; ++Index)
1146 Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
1148 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
1149 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
1151 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
1152 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
1154 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
1155 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
1157 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
1158 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
1160 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
1161 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));