1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/Support/Debug.h"
30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
31 : AMDGPUInstrInfo(st), RI(st) {}
33 //===----------------------------------------------------------------------===//
34 // TargetInstrInfo callbacks
35 //===----------------------------------------------------------------------===//
37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
38 unsigned N = Node->getNumOperands();
39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
44 static SDValue findChainOperand(SDNode *Load) {
45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
50 /// \brief Returns true if both nodes have the same value for the given
51 /// operand \p Op, or if both nodes do not have this operand.
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
53 unsigned Opc0 = N0->getMachineOpcode();
54 unsigned Opc1 = N1->getMachineOpcode();
56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59 if (Op0Idx == -1 && Op1Idx == -1)
63 if ((Op0Idx == -1 && Op1Idx != -1) ||
64 (Op1Idx == -1 && Op0Idx != -1))
67 // getNamedOperandIdx returns the index for the MachineInstr's operands,
68 // which includes the result as the first operand. We are indexing into the
69 // MachineSDNode's operands, so we need to skip the result operand to get
74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
77 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
79 int64_t &Offset1) const {
80 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
83 unsigned Opc0 = Load0->getMachineOpcode();
84 unsigned Opc1 = Load1->getMachineOpcode();
86 // Make sure both are actually loads.
87 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
90 if (isDS(Opc0) && isDS(Opc1)) {
92 // FIXME: Handle this case:
93 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
97 if (Load0->getOperand(1) != Load1->getOperand(1))
101 if (findChainOperand(Load0) != findChainOperand(Load1))
104 // Skip read2 / write2 variants for simplicity.
105 // TODO: We should report true if the used offsets are adjacent (excluded
107 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
108 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
111 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
112 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
116 if (isSMRD(Opc0) && isSMRD(Opc1)) {
117 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
120 if (Load0->getOperand(0) != Load1->getOperand(0))
124 if (findChainOperand(Load0) != findChainOperand(Load1))
127 Offset0 = cast<ConstantSDNode>(Load0->getOperand(1))->getZExtValue();
128 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue();
132 // MUBUF and MTBUF can access the same addresses.
133 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
135 // MUBUF and MTBUF have vaddr at different indices.
136 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
137 findChainOperand(Load0) != findChainOperand(Load1) ||
138 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
139 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
142 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
143 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
145 if (OffIdx0 == -1 || OffIdx1 == -1)
148 // getNamedOperandIdx returns the index for MachineInstrs. Since they
149 // inlcude the output in the operand list, but SDNodes don't, we need to
150 // subtract the index by one.
154 SDValue Off0 = Load0->getOperand(OffIdx0);
155 SDValue Off1 = Load1->getOperand(OffIdx1);
157 // The offset might be a FrameIndexSDNode.
158 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
161 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
162 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
169 static bool isStride64(unsigned Opc) {
171 case AMDGPU::DS_READ2ST64_B32:
172 case AMDGPU::DS_READ2ST64_B64:
173 case AMDGPU::DS_WRITE2ST64_B32:
174 case AMDGPU::DS_WRITE2ST64_B64:
181 bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
182 unsigned &BaseReg, unsigned &Offset,
183 const TargetRegisterInfo *TRI) const {
184 unsigned Opc = LdSt->getOpcode();
186 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
187 AMDGPU::OpName::offset);
189 // Normal, single offset LDS instruction.
190 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
191 AMDGPU::OpName::addr);
193 BaseReg = AddrReg->getReg();
194 Offset = OffsetImm->getImm();
198 // The 2 offset instructions use offset0 and offset1 instead. We can treat
199 // these as a load with a single offset if the 2 offsets are consecutive. We
200 // will use this for some partially aligned loads.
201 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
202 AMDGPU::OpName::offset0);
203 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
204 AMDGPU::OpName::offset1);
206 uint8_t Offset0 = Offset0Imm->getImm();
207 uint8_t Offset1 = Offset1Imm->getImm();
208 assert(Offset1 > Offset0);
210 if (Offset1 - Offset0 == 1) {
211 // Each of these offsets is in element sized units, so we need to convert
212 // to bytes of the individual reads.
216 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
218 assert(LdSt->mayStore());
219 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
220 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
226 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
227 AMDGPU::OpName::addr);
228 BaseReg = AddrReg->getReg();
229 Offset = EltSize * Offset0;
236 if (isMUBUF(Opc) || isMTBUF(Opc)) {
237 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
240 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
241 AMDGPU::OpName::vaddr);
245 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
246 AMDGPU::OpName::offset);
247 BaseReg = AddrReg->getReg();
248 Offset = OffsetImm->getImm();
253 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
254 AMDGPU::OpName::offset);
258 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
259 AMDGPU::OpName::sbase);
260 BaseReg = SBaseReg->getReg();
261 Offset = OffsetImm->getImm();
268 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
269 MachineInstr *SecondLdSt,
270 unsigned NumLoads) const {
271 unsigned Opc0 = FirstLdSt->getOpcode();
272 unsigned Opc1 = SecondLdSt->getOpcode();
274 // TODO: This needs finer tuning
278 if (isDS(Opc0) && isDS(Opc1))
281 if (isSMRD(Opc0) && isSMRD(Opc1))
284 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1)))
291 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
292 MachineBasicBlock::iterator MI, DebugLoc DL,
293 unsigned DestReg, unsigned SrcReg,
294 bool KillSrc) const {
296 // If we are trying to copy to or from SCC, there is a bug somewhere else in
297 // the backend. While it may be theoretically possible to do this, it should
298 // never be necessary.
299 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
301 static const int16_t Sub0_15[] = {
302 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
303 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
304 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
305 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
308 static const int16_t Sub0_7[] = {
309 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
310 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
313 static const int16_t Sub0_3[] = {
314 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
317 static const int16_t Sub0_2[] = {
318 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
321 static const int16_t Sub0_1[] = {
322 AMDGPU::sub0, AMDGPU::sub1, 0
326 const int16_t *SubIndices;
328 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
329 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
330 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
331 .addReg(SrcReg, getKillRegState(KillSrc));
334 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
335 if (DestReg == AMDGPU::VCC) {
336 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
337 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
338 .addReg(SrcReg, getKillRegState(KillSrc));
340 // FIXME: Hack until VReg_1 removed.
341 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
342 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32), AMDGPU::VCC)
344 .addReg(SrcReg, getKillRegState(KillSrc));
350 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
351 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
352 .addReg(SrcReg, getKillRegState(KillSrc));
355 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
356 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
357 Opcode = AMDGPU::S_MOV_B32;
360 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
361 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
362 Opcode = AMDGPU::S_MOV_B32;
365 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
366 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
367 Opcode = AMDGPU::S_MOV_B32;
368 SubIndices = Sub0_15;
370 } else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) {
371 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
372 AMDGPU::SReg_32RegClass.contains(SrcReg));
373 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
374 .addReg(SrcReg, getKillRegState(KillSrc));
377 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
378 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
379 AMDGPU::SReg_64RegClass.contains(SrcReg));
380 Opcode = AMDGPU::V_MOV_B32_e32;
383 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
384 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
385 Opcode = AMDGPU::V_MOV_B32_e32;
388 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
389 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
390 AMDGPU::SReg_128RegClass.contains(SrcReg));
391 Opcode = AMDGPU::V_MOV_B32_e32;
394 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
395 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
396 AMDGPU::SReg_256RegClass.contains(SrcReg));
397 Opcode = AMDGPU::V_MOV_B32_e32;
400 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
401 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
402 AMDGPU::SReg_512RegClass.contains(SrcReg));
403 Opcode = AMDGPU::V_MOV_B32_e32;
404 SubIndices = Sub0_15;
407 llvm_unreachable("Can't copy register!");
410 while (unsigned SubIdx = *SubIndices++) {
411 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
412 get(Opcode), RI.getSubReg(DestReg, SubIdx));
414 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
417 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
421 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
424 // Try to map original to commuted opcode
425 NewOpc = AMDGPU::getCommuteRev(Opcode);
426 // Check if the commuted (REV) opcode exists on the target.
427 if (NewOpc != -1 && pseudoToMCOpcode(NewOpc) != -1)
430 // Try to map commuted to original opcode
431 NewOpc = AMDGPU::getCommuteOrig(Opcode);
432 // Check if the original (non-REV) opcode exists on the target.
433 if (NewOpc != -1 && pseudoToMCOpcode(NewOpc) != -1)
439 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
441 if (DstRC->getSize() == 4) {
442 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
443 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
444 return AMDGPU::S_MOV_B64;
445 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
446 return AMDGPU::V_MOV_B64_PSEUDO;
451 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
452 MachineBasicBlock::iterator MI,
453 unsigned SrcReg, bool isKill,
455 const TargetRegisterClass *RC,
456 const TargetRegisterInfo *TRI) const {
457 MachineFunction *MF = MBB.getParent();
458 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
459 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
460 DebugLoc DL = MBB.findDebugLoc(MI);
463 if (RI.isSGPRClass(RC)) {
464 // We are only allowed to create one new instruction when spilling
465 // registers, so we need to use pseudo instruction for spilling
467 switch (RC->getSize() * 8) {
468 case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break;
469 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
470 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
471 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
472 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
474 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
475 MFI->setHasSpilledVGPRs();
477 switch(RC->getSize() * 8) {
478 case 32: Opcode = AMDGPU::SI_SPILL_V32_SAVE; break;
479 case 64: Opcode = AMDGPU::SI_SPILL_V64_SAVE; break;
480 case 96: Opcode = AMDGPU::SI_SPILL_V96_SAVE; break;
481 case 128: Opcode = AMDGPU::SI_SPILL_V128_SAVE; break;
482 case 256: Opcode = AMDGPU::SI_SPILL_V256_SAVE; break;
483 case 512: Opcode = AMDGPU::SI_SPILL_V512_SAVE; break;
488 FrameInfo->setObjectAlignment(FrameIndex, 4);
489 BuildMI(MBB, MI, DL, get(Opcode))
491 .addFrameIndex(FrameIndex)
492 // Place-holder registers, these will be filled in by
493 // SIPrepareScratchRegs.
494 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
495 .addReg(AMDGPU::SGPR0, RegState::Undef);
497 LLVMContext &Ctx = MF->getFunction()->getContext();
498 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
500 BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
505 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
506 MachineBasicBlock::iterator MI,
507 unsigned DestReg, int FrameIndex,
508 const TargetRegisterClass *RC,
509 const TargetRegisterInfo *TRI) const {
510 MachineFunction *MF = MBB.getParent();
511 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
512 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
513 DebugLoc DL = MBB.findDebugLoc(MI);
516 if (RI.isSGPRClass(RC)){
517 switch(RC->getSize() * 8) {
518 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
519 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
520 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
521 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
522 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
524 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
525 switch(RC->getSize() * 8) {
526 case 32: Opcode = AMDGPU::SI_SPILL_V32_RESTORE; break;
527 case 64: Opcode = AMDGPU::SI_SPILL_V64_RESTORE; break;
528 case 96: Opcode = AMDGPU::SI_SPILL_V96_RESTORE; break;
529 case 128: Opcode = AMDGPU::SI_SPILL_V128_RESTORE; break;
530 case 256: Opcode = AMDGPU::SI_SPILL_V256_RESTORE; break;
531 case 512: Opcode = AMDGPU::SI_SPILL_V512_RESTORE; break;
536 FrameInfo->setObjectAlignment(FrameIndex, 4);
537 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
538 .addFrameIndex(FrameIndex)
539 // Place-holder registers, these will be filled in by
540 // SIPrepareScratchRegs.
541 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
542 .addReg(AMDGPU::SGPR0, RegState::Undef);
545 LLVMContext &Ctx = MF->getFunction()->getContext();
546 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
547 " restore register");
548 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
552 /// \param @Offset Offset in bytes of the FrameIndex being spilled
553 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
554 MachineBasicBlock::iterator MI,
555 RegScavenger *RS, unsigned TmpReg,
556 unsigned FrameOffset,
557 unsigned Size) const {
558 MachineFunction *MF = MBB.getParent();
559 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
560 const AMDGPUSubtarget &ST = MF->getSubtarget<AMDGPUSubtarget>();
561 const SIRegisterInfo *TRI =
562 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
563 DebugLoc DL = MBB.findDebugLoc(MI);
564 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
565 unsigned WavefrontSize = ST.getWavefrontSize();
567 unsigned TIDReg = MFI->getTIDReg();
568 if (!MFI->hasCalculatedTID()) {
569 MachineBasicBlock &Entry = MBB.getParent()->front();
570 MachineBasicBlock::iterator Insert = Entry.front();
571 DebugLoc DL = Insert->getDebugLoc();
573 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
574 if (TIDReg == AMDGPU::NoRegister)
578 if (MFI->getShaderType() == ShaderType::COMPUTE &&
579 WorkGroupSize > WavefrontSize) {
581 unsigned TIDIGXReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_X);
582 unsigned TIDIGYReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Y);
583 unsigned TIDIGZReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Z);
584 unsigned InputPtrReg =
585 TRI->getPreloadedValue(*MF, SIRegisterInfo::INPUT_PTR);
586 static const unsigned TIDIGRegs[3] = {
587 TIDIGXReg, TIDIGYReg, TIDIGZReg
589 for (unsigned Reg : TIDIGRegs) {
590 if (!Entry.isLiveIn(Reg))
591 Entry.addLiveIn(Reg);
594 RS->enterBasicBlock(&Entry);
595 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
596 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
597 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
599 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
600 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
602 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
604 // NGROUPS.X * NGROUPS.Y
605 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
608 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
609 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
612 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
613 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
617 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
618 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
623 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
628 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
634 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
638 MFI->setTIDReg(TIDReg);
641 // Add FrameIndex to LDS offset
642 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
643 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
650 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
659 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
664 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
665 MachineBasicBlock &MBB = *MI->getParent();
666 DebugLoc DL = MBB.findDebugLoc(MI);
667 switch (MI->getOpcode()) {
668 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
670 case AMDGPU::SI_CONSTDATA_PTR: {
671 unsigned Reg = MI->getOperand(0).getReg();
672 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
673 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
675 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
677 // Add 32-bit offset from this instruction to the start of the constant data.
678 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo)
680 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
681 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
682 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
685 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
686 .addReg(AMDGPU::SCC, RegState::Implicit);
687 MI->eraseFromParent();
690 case AMDGPU::SGPR_USE:
691 // This is just a placeholder for register allocation.
692 MI->eraseFromParent();
695 case AMDGPU::V_MOV_B64_PSEUDO: {
696 unsigned Dst = MI->getOperand(0).getReg();
697 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
698 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
700 const MachineOperand &SrcOp = MI->getOperand(1);
701 // FIXME: Will this work for 64-bit floating point immediates?
702 assert(!SrcOp.isFPImm());
704 APInt Imm(64, SrcOp.getImm());
705 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
706 .addImm(Imm.getLoBits(32).getZExtValue())
707 .addReg(Dst, RegState::Implicit);
708 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
709 .addImm(Imm.getHiBits(32).getZExtValue())
710 .addReg(Dst, RegState::Implicit);
712 assert(SrcOp.isReg());
713 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
714 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
715 .addReg(Dst, RegState::Implicit);
716 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
717 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
718 .addReg(Dst, RegState::Implicit);
720 MI->eraseFromParent();
727 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
730 if (MI->getNumOperands() < 3)
733 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
734 AMDGPU::OpName::src0);
735 assert(Src0Idx != -1 && "Should always have src0 operand");
737 MachineOperand &Src0 = MI->getOperand(Src0Idx);
741 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
742 AMDGPU::OpName::src1);
746 MachineOperand &Src1 = MI->getOperand(Src1Idx);
748 // Make sure it's legal to commute operands for VOP2.
749 if (isVOP2(MI->getOpcode()) &&
750 (!isOperandLegal(MI, Src0Idx, &Src1) ||
751 !isOperandLegal(MI, Src1Idx, &Src0))) {
756 // Allow commuting instructions with Imm operands.
757 if (NewMI || !Src1.isImm() ||
758 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
762 // Be sure to copy the source modifiers to the right place.
763 if (MachineOperand *Src0Mods
764 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
765 MachineOperand *Src1Mods
766 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers);
768 int Src0ModsVal = Src0Mods->getImm();
769 if (!Src1Mods && Src0ModsVal != 0)
772 // XXX - This assert might be a lie. It might be useful to have a neg
773 // modifier with 0.0.
774 int Src1ModsVal = Src1Mods->getImm();
775 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates");
777 Src1Mods->setImm(Src0ModsVal);
778 Src0Mods->setImm(Src1ModsVal);
781 unsigned Reg = Src0.getReg();
782 unsigned SubReg = Src0.getSubReg();
784 Src0.ChangeToImmediate(Src1.getImm());
786 llvm_unreachable("Should only have immediates");
788 Src1.ChangeToRegister(Reg, false);
789 Src1.setSubReg(SubReg);
791 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
795 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
800 // This needs to be implemented because the source modifiers may be inserted
801 // between the true commutable operands, and the base
802 // TargetInstrInfo::commuteInstruction uses it.
803 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
805 unsigned &SrcOpIdx2) const {
806 const MCInstrDesc &MCID = MI->getDesc();
807 if (!MCID.isCommutable())
810 unsigned Opc = MI->getOpcode();
811 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
815 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on
817 if (!MI->getOperand(Src0Idx).isReg())
820 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
824 if (!MI->getOperand(Src1Idx).isReg())
827 // If any source modifiers are set, the generic instruction commuting won't
828 // understand how to copy the source modifiers.
829 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) ||
830 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers))
838 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
839 MachineBasicBlock::iterator I,
841 unsigned SrcReg) const {
842 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
843 DstReg) .addReg(SrcReg);
846 bool SIInstrInfo::isMov(unsigned Opcode) const {
848 default: return false;
849 case AMDGPU::S_MOV_B32:
850 case AMDGPU::S_MOV_B64:
851 case AMDGPU::V_MOV_B32_e32:
852 case AMDGPU::V_MOV_B32_e64:
858 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
859 return RC != &AMDGPU::EXECRegRegClass;
863 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
864 AliasAnalysis *AA) const {
865 switch(MI->getOpcode()) {
866 default: return AMDGPUInstrInfo::isTriviallyReMaterializable(MI, AA);
867 case AMDGPU::S_MOV_B32:
868 case AMDGPU::S_MOV_B64:
869 case AMDGPU::V_MOV_B32_e32:
870 return MI->getOperand(1).isImm();
874 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
875 int WidthB, int OffsetB) {
876 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
877 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
878 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
879 return LowOffset + LowWidth <= HighOffset;
882 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
883 MachineInstr *MIb) const {
884 unsigned BaseReg0, Offset0;
885 unsigned BaseReg1, Offset1;
887 if (getLdStBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) &&
888 getLdStBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) {
889 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() &&
890 "read2 / write2 not expected here yet");
891 unsigned Width0 = (*MIa->memoperands_begin())->getSize();
892 unsigned Width1 = (*MIb->memoperands_begin())->getSize();
893 if (BaseReg0 == BaseReg1 &&
894 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
902 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
904 AliasAnalysis *AA) const {
905 unsigned Opc0 = MIa->getOpcode();
906 unsigned Opc1 = MIb->getOpcode();
908 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
909 "MIa must load from or modify a memory location");
910 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
911 "MIb must load from or modify a memory location");
913 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects())
916 // XXX - Can we relax this between address spaces?
917 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
920 // TODO: Should we check the address space from the MachineMemOperand? That
921 // would allow us to distinguish objects we know don't alias based on the
922 // underlying addres space, even if it was lowered to a different one,
923 // e.g. private accesses lowered to use MUBUF instructions on a scratch
927 return checkInstOffsetsDoNotOverlap(MIa, MIb);
929 return !isFLAT(Opc1);
932 if (isMUBUF(Opc0) || isMTBUF(Opc0)) {
933 if (isMUBUF(Opc1) || isMTBUF(Opc1))
934 return checkInstOffsetsDoNotOverlap(MIa, MIb);
936 return !isFLAT(Opc1) && !isSMRD(Opc1);
941 return checkInstOffsetsDoNotOverlap(MIa, MIb);
943 return !isFLAT(Opc1) && !isMUBUF(Opc0) && !isMTBUF(Opc0);
948 return checkInstOffsetsDoNotOverlap(MIa, MIb);
956 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
957 int64_t SVal = Imm.getSExtValue();
958 if (SVal >= -16 && SVal <= 64)
961 if (Imm.getBitWidth() == 64) {
962 uint64_t Val = Imm.getZExtValue();
963 return (DoubleToBits(0.0) == Val) ||
964 (DoubleToBits(1.0) == Val) ||
965 (DoubleToBits(-1.0) == Val) ||
966 (DoubleToBits(0.5) == Val) ||
967 (DoubleToBits(-0.5) == Val) ||
968 (DoubleToBits(2.0) == Val) ||
969 (DoubleToBits(-2.0) == Val) ||
970 (DoubleToBits(4.0) == Val) ||
971 (DoubleToBits(-4.0) == Val);
974 // The actual type of the operand does not seem to matter as long
975 // as the bits match one of the inline immediate values. For example:
977 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
978 // so it is a legal inline immediate.
980 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
981 // floating-point, so it is a legal inline immediate.
982 uint32_t Val = Imm.getZExtValue();
984 return (FloatToBits(0.0f) == Val) ||
985 (FloatToBits(1.0f) == Val) ||
986 (FloatToBits(-1.0f) == Val) ||
987 (FloatToBits(0.5f) == Val) ||
988 (FloatToBits(-0.5f) == Val) ||
989 (FloatToBits(2.0f) == Val) ||
990 (FloatToBits(-2.0f) == Val) ||
991 (FloatToBits(4.0f) == Val) ||
992 (FloatToBits(-4.0f) == Val);
995 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
996 unsigned OpSize) const {
998 // MachineOperand provides no way to tell the true operand size, since it
999 // only records a 64-bit value. We need to know the size to determine if a
1000 // 32-bit floating point immediate bit pattern is legal for an integer
1001 // immediate. It would be for any 32-bit integer operand, but would not be
1002 // for a 64-bit one.
1004 unsigned BitSize = 8 * OpSize;
1005 return isInlineConstant(APInt(BitSize, MO.getImm(), true));
1011 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO,
1012 unsigned OpSize) const {
1013 return MO.isImm() && !isInlineConstant(MO, OpSize);
1016 static bool compareMachineOp(const MachineOperand &Op0,
1017 const MachineOperand &Op1) {
1018 if (Op0.getType() != Op1.getType())
1021 switch (Op0.getType()) {
1022 case MachineOperand::MO_Register:
1023 return Op0.getReg() == Op1.getReg();
1024 case MachineOperand::MO_Immediate:
1025 return Op0.getImm() == Op1.getImm();
1027 llvm_unreachable("Didn't expect to be comparing these operand types");
1031 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
1032 const MachineOperand &MO) const {
1033 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1035 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
1037 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
1040 if (OpInfo.RegClass < 0)
1043 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize();
1044 if (isLiteralConstant(MO, OpSize))
1045 return RI.opCanUseLiteralConstant(OpInfo.OperandType);
1047 return RI.opCanUseInlineConstant(OpInfo.OperandType);
1050 bool SIInstrInfo::canFoldOffset(unsigned OffsetSize, unsigned AS) const {
1052 case AMDGPUAS::GLOBAL_ADDRESS: {
1053 // MUBUF instructions a 12-bit offset in bytes.
1054 return isUInt<12>(OffsetSize);
1056 case AMDGPUAS::CONSTANT_ADDRESS: {
1057 // SMRD instructions have an 8-bit offset in dwords on SI and
1058 // a 20-bit offset in bytes on VI.
1059 if (RI.ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1060 return isUInt<20>(OffsetSize);
1062 return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4);
1064 case AMDGPUAS::LOCAL_ADDRESS:
1065 case AMDGPUAS::REGION_ADDRESS: {
1066 // The single offset versions have a 16-bit offset in bytes.
1067 return isUInt<16>(OffsetSize);
1069 case AMDGPUAS::PRIVATE_ADDRESS:
1070 // Indirect register addressing does not use any offsets.
1076 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1077 int Op32 = AMDGPU::getVOPe32(Opcode);
1081 return pseudoToMCOpcode(Op32) != -1;
1084 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
1085 // The src0_modifier operand is present on all instructions
1086 // that have modifiers.
1088 return AMDGPU::getNamedOperandIdx(Opcode,
1089 AMDGPU::OpName::src0_modifiers) != -1;
1092 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
1093 unsigned OpName) const {
1094 const MachineOperand *Mods = getNamedOperand(MI, OpName);
1095 return Mods && Mods->getImm();
1098 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
1099 const MachineOperand &MO,
1100 unsigned OpSize) const {
1101 // Literal constants use the constant bus.
1102 if (isLiteralConstant(MO, OpSize))
1105 if (!MO.isReg() || !MO.isUse())
1108 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1109 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
1111 // FLAT_SCR is just an SGPR pair.
1112 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
1115 // EXEC register uses the constant bus.
1116 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
1119 // SGPRs use the constant bus
1120 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
1121 (!MO.isImplicit() &&
1122 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
1123 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
1130 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1131 StringRef &ErrInfo) const {
1132 uint16_t Opcode = MI->getOpcode();
1133 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1134 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1135 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
1136 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
1138 // Make sure the number of operands is correct.
1139 const MCInstrDesc &Desc = get(Opcode);
1140 if (!Desc.isVariadic() &&
1141 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
1142 ErrInfo = "Instruction has wrong number of operands.";
1146 // Make sure the register classes are correct
1147 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
1148 if (MI->getOperand(i).isFPImm()) {
1149 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
1150 "all fp values to integers.";
1154 switch (Desc.OpInfo[i].OperandType) {
1155 case MCOI::OPERAND_REGISTER:
1156 if (MI->getOperand(i).isImm()) {
1157 ErrInfo = "Illegal immediate value for operand.";
1161 case AMDGPU::OPERAND_REG_IMM32:
1163 case AMDGPU::OPERAND_REG_INLINE_C:
1164 if (MI->getOperand(i).isImm()) {
1165 int RegClass = Desc.OpInfo[i].RegClass;
1166 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1167 if (!isInlineConstant(MI->getOperand(i), RC->getSize())) {
1168 ErrInfo = "Illegal immediate value for operand.";
1173 case MCOI::OPERAND_IMMEDIATE:
1174 // Check if this operand is an immediate.
1175 // FrameIndex operands will be replaced by immediates, so they are
1177 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFI()) {
1178 ErrInfo = "Expected immediate, but got non-immediate";
1186 if (!MI->getOperand(i).isReg())
1189 int RegClass = Desc.OpInfo[i].RegClass;
1190 if (RegClass != -1) {
1191 unsigned Reg = MI->getOperand(i).getReg();
1192 if (TargetRegisterInfo::isVirtualRegister(Reg))
1195 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1196 if (!RC->contains(Reg)) {
1197 ErrInfo = "Operand has incorrect register class.";
1205 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
1206 // Only look at the true operands. Only a real operand can use the constant
1207 // bus, and we don't want to check pseudo-operands like the source modifier
1209 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
1211 unsigned ConstantBusCount = 0;
1212 unsigned SGPRUsed = AMDGPU::NoRegister;
1213 for (int OpIdx : OpIndices) {
1216 const MachineOperand &MO = MI->getOperand(OpIdx);
1217 if (usesConstantBus(MRI, MO, getOpSize(Opcode, OpIdx))) {
1219 if (MO.getReg() != SGPRUsed)
1221 SGPRUsed = MO.getReg();
1227 if (ConstantBusCount > 1) {
1228 ErrInfo = "VOP* instruction uses the constant bus more than once";
1233 // Verify SRC1 for VOP2 and VOPC
1234 if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
1235 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1237 ErrInfo = "VOP[2C] src1 cannot be an immediate.";
1243 if (isVOP3(Opcode)) {
1244 if (Src0Idx != -1 &&
1245 isLiteralConstant(MI->getOperand(Src0Idx), getOpSize(Opcode, Src0Idx))) {
1246 ErrInfo = "VOP3 src0 cannot be a literal constant.";
1249 if (Src1Idx != -1 &&
1250 isLiteralConstant(MI->getOperand(Src1Idx), getOpSize(Opcode, Src1Idx))) {
1251 ErrInfo = "VOP3 src1 cannot be a literal constant.";
1254 if (Src2Idx != -1 &&
1255 isLiteralConstant(MI->getOperand(Src2Idx), getOpSize(Opcode, Src2Idx))) {
1256 ErrInfo = "VOP3 src2 cannot be a literal constant.";
1261 // Verify misc. restrictions on specific instructions.
1262 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1263 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1264 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1265 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1266 const MachineOperand &Src2 = MI->getOperand(Src2Idx);
1267 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1268 if (!compareMachineOp(Src0, Src1) &&
1269 !compareMachineOp(Src0, Src2)) {
1270 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1279 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1280 switch (MI.getOpcode()) {
1281 default: return AMDGPU::INSTRUCTION_LIST_END;
1282 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1283 case AMDGPU::COPY: return AMDGPU::COPY;
1284 case AMDGPU::PHI: return AMDGPU::PHI;
1285 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1286 case AMDGPU::S_MOV_B32:
1287 return MI.getOperand(1).isReg() ?
1288 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1289 case AMDGPU::S_ADD_I32:
1290 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1291 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1292 case AMDGPU::S_SUB_I32:
1293 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1294 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1295 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1296 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1297 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1298 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1299 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1300 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1301 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1302 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1303 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1304 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1305 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1306 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1307 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1308 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1309 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1310 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1311 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1312 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1313 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1314 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1315 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1316 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1317 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1318 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1319 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1320 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1321 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1322 case AMDGPU::S_LOAD_DWORD_IMM:
1323 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1324 case AMDGPU::S_LOAD_DWORDX2_IMM:
1325 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1326 case AMDGPU::S_LOAD_DWORDX4_IMM:
1327 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1328 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
1329 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1330 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1334 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1335 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1338 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1339 unsigned OpNo) const {
1340 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1341 const MCInstrDesc &Desc = get(MI.getOpcode());
1342 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1343 Desc.OpInfo[OpNo].RegClass == -1) {
1344 unsigned Reg = MI.getOperand(OpNo).getReg();
1346 if (TargetRegisterInfo::isVirtualRegister(Reg))
1347 return MRI.getRegClass(Reg);
1348 return RI.getPhysRegClass(Reg);
1351 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1352 return RI.getRegClass(RCID);
1355 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1356 switch (MI.getOpcode()) {
1358 case AMDGPU::REG_SEQUENCE:
1360 case AMDGPU::INSERT_SUBREG:
1361 return RI.hasVGPRs(getOpRegClass(MI, 0));
1363 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1367 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1368 MachineBasicBlock::iterator I = MI;
1369 MachineBasicBlock *MBB = MI->getParent();
1370 MachineOperand &MO = MI->getOperand(OpIdx);
1371 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1372 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1373 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1374 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1376 Opcode = AMDGPU::COPY;
1377 else if (RI.isSGPRClass(RC))
1378 Opcode = AMDGPU::S_MOV_B32;
1381 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1382 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
1383 VRC = &AMDGPU::VReg_64RegClass;
1385 VRC = &AMDGPU::VGPR_32RegClass;
1387 unsigned Reg = MRI.createVirtualRegister(VRC);
1388 DebugLoc DL = MBB->findDebugLoc(I);
1389 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
1391 MO.ChangeToRegister(Reg, false);
1394 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1395 MachineRegisterInfo &MRI,
1396 MachineOperand &SuperReg,
1397 const TargetRegisterClass *SuperRC,
1399 const TargetRegisterClass *SubRC)
1401 assert(SuperReg.isReg());
1403 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1404 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1406 // Just in case the super register is itself a sub-register, copy it to a new
1407 // value so we don't need to worry about merging its subreg index with the
1408 // SubIdx passed to this function. The register coalescer should be able to
1409 // eliminate this extra copy.
1410 MachineBasicBlock *MBB = MI->getParent();
1411 DebugLoc DL = MI->getDebugLoc();
1413 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
1414 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
1416 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1417 .addReg(NewSuperReg, 0, SubIdx);
1422 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1423 MachineBasicBlock::iterator MII,
1424 MachineRegisterInfo &MRI,
1426 const TargetRegisterClass *SuperRC,
1428 const TargetRegisterClass *SubRC) const {
1430 // XXX - Is there a better way to do this?
1431 if (SubIdx == AMDGPU::sub0)
1432 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1433 if (SubIdx == AMDGPU::sub1)
1434 return MachineOperand::CreateImm(Op.getImm() >> 32);
1436 llvm_unreachable("Unhandled register index for immediate");
1439 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1441 return MachineOperand::CreateReg(SubReg, false);
1444 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
1445 MachineBasicBlock::iterator MI,
1446 MachineRegisterInfo &MRI,
1447 const TargetRegisterClass *RC,
1448 const MachineOperand &Op) const {
1449 MachineBasicBlock *MBB = MI->getParent();
1450 DebugLoc DL = MI->getDebugLoc();
1451 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1452 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1453 unsigned Dst = MRI.createVirtualRegister(RC);
1455 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1457 .addImm(Op.getImm() & 0xFFFFFFFF);
1458 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1460 .addImm(Op.getImm() >> 32);
1462 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
1464 .addImm(AMDGPU::sub0)
1466 .addImm(AMDGPU::sub1);
1468 Worklist.push_back(Lo);
1469 Worklist.push_back(Hi);
1474 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
1475 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {
1476 assert(Inst->getNumExplicitOperands() == 3);
1477 MachineOperand Op1 = Inst->getOperand(1);
1478 Inst->RemoveOperand(1);
1479 Inst->addOperand(Op1);
1482 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1483 const MachineOperand *MO) const {
1484 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1485 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1486 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1487 const TargetRegisterClass *DefinedRC =
1488 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1490 MO = &MI->getOperand(OpIdx);
1492 if (isVALU(InstDesc.Opcode) &&
1493 usesConstantBus(MRI, *MO, DefinedRC->getSize())) {
1495 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1496 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1499 const MachineOperand &Op = MI->getOperand(i);
1500 if (Op.isReg() && Op.getReg() != SGPRUsed &&
1501 usesConstantBus(MRI, Op, getOpSize(*MI, i))) {
1509 const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg());
1511 // In order to be legal, the common sub-class must be equal to the
1512 // class of the current operand. For example:
1514 // v_mov_b32 s0 ; Operand defined as vsrc_32
1515 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL
1517 // s_sendmsg 0, s0 ; Operand defined as m0reg
1518 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
1520 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
1524 // Handle non-register types that are treated like immediates.
1525 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
1528 // This operand expects an immediate.
1532 return isImmOperandLegal(MI, OpIdx, *MO);
1535 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1536 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1538 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1539 AMDGPU::OpName::src0);
1540 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1541 AMDGPU::OpName::src1);
1542 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1543 AMDGPU::OpName::src2);
1546 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1548 if (!isOperandLegal(MI, Src0Idx))
1549 legalizeOpWithMove(MI, Src0Idx);
1552 if (isOperandLegal(MI, Src1Idx))
1555 // Usually src0 of VOP2 instructions allow more types of inputs
1556 // than src1, so try to commute the instruction to decrease our
1557 // chances of having to insert a MOV instruction to legalize src1.
1558 if (MI->isCommutable()) {
1559 if (commuteInstruction(MI))
1560 // If we are successful in commuting, then we know MI is legal, so
1565 legalizeOpWithMove(MI, Src1Idx);
1569 // XXX - Do any VOP3 instructions read VCC?
1571 if (isVOP3(MI->getOpcode())) {
1572 int VOP3Idx[3] = { Src0Idx, Src1Idx, Src2Idx };
1574 // Find the one SGPR operand we are allowed to use.
1575 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
1577 for (unsigned i = 0; i < 3; ++i) {
1578 int Idx = VOP3Idx[i];
1581 MachineOperand &MO = MI->getOperand(Idx);
1584 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1585 continue; // VGPRs are legal
1587 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1589 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1590 SGPRReg = MO.getReg();
1591 // We can use one SGPR in each VOP3 instruction.
1594 } else if (!isLiteralConstant(MO, getOpSize(MI->getOpcode(), Idx))) {
1595 // If it is not a register and not a literal constant, then it must be
1596 // an inline constant which is always legal.
1599 // If we make it this far, then the operand is not legal and we must
1601 legalizeOpWithMove(MI, Idx);
1605 // Legalize REG_SEQUENCE and PHI
1606 // The register class of the operands much be the same type as the register
1607 // class of the output.
1608 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
1609 MI->getOpcode() == AMDGPU::PHI) {
1610 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1611 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1612 if (!MI->getOperand(i).isReg() ||
1613 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1615 const TargetRegisterClass *OpRC =
1616 MRI.getRegClass(MI->getOperand(i).getReg());
1617 if (RI.hasVGPRs(OpRC)) {
1624 // If any of the operands are VGPR registers, then they all most be
1625 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1627 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1630 VRC = RI.getEquivalentVGPRClass(SRC);
1637 // Update all the operands so they have the same type.
1638 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1639 if (!MI->getOperand(i).isReg() ||
1640 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1642 unsigned DstReg = MRI.createVirtualRegister(RC);
1643 MachineBasicBlock *InsertBB;
1644 MachineBasicBlock::iterator Insert;
1645 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1646 InsertBB = MI->getParent();
1649 // MI is a PHI instruction.
1650 InsertBB = MI->getOperand(i + 1).getMBB();
1651 Insert = InsertBB->getFirstTerminator();
1653 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1654 get(AMDGPU::COPY), DstReg)
1655 .addOperand(MI->getOperand(i));
1656 MI->getOperand(i).setReg(DstReg);
1660 // Legalize INSERT_SUBREG
1661 // src0 must have the same register class as dst
1662 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1663 unsigned Dst = MI->getOperand(0).getReg();
1664 unsigned Src0 = MI->getOperand(1).getReg();
1665 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1666 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1667 if (DstRC != Src0RC) {
1668 MachineBasicBlock &MBB = *MI->getParent();
1669 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1670 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1672 MI->getOperand(1).setReg(NewSrc0);
1677 // Legalize MUBUF* instructions
1678 // FIXME: If we start using the non-addr64 instructions for compute, we
1679 // may need to legalize them here.
1681 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1682 if (SRsrcIdx != -1) {
1683 // We have an MUBUF instruction
1684 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1685 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1686 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1687 RI.getRegClass(SRsrcRC))) {
1688 // The operands are legal.
1689 // FIXME: We may need to legalize operands besided srsrc.
1693 MachineBasicBlock &MBB = *MI->getParent();
1694 // Extract the the ptr from the resource descriptor.
1696 // SRsrcPtrLo = srsrc:sub0
1697 unsigned SRsrcPtrLo = buildExtractSubReg(MI, MRI, *SRsrc,
1698 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VGPR_32RegClass);
1700 // SRsrcPtrHi = srsrc:sub1
1701 unsigned SRsrcPtrHi = buildExtractSubReg(MI, MRI, *SRsrc,
1702 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VGPR_32RegClass);
1704 // Create an empty resource descriptor
1705 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1706 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1707 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1708 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1709 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1712 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1716 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1717 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1719 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1721 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1722 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1724 .addImm(RsrcDataFormat >> 32);
1726 // NewSRsrc = {Zero64, SRsrcFormat}
1727 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1730 .addImm(AMDGPU::sub0_sub1)
1731 .addReg(SRsrcFormatLo)
1732 .addImm(AMDGPU::sub2)
1733 .addReg(SRsrcFormatHi)
1734 .addImm(AMDGPU::sub3);
1736 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1737 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1738 unsigned NewVAddrLo;
1739 unsigned NewVAddrHi;
1741 // This is already an ADDR64 instruction so we need to add the pointer
1742 // extracted from the resource descriptor to the current value of VAddr.
1743 NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1744 NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1746 // NewVaddrLo = SRsrcPtrLo + VAddr:sub0
1747 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
1750 .addReg(VAddr->getReg(), 0, AMDGPU::sub0)
1751 .addReg(AMDGPU::VCC, RegState::ImplicitDefine);
1753 // NewVaddrHi = SRsrcPtrHi + VAddr:sub1
1754 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
1757 .addReg(VAddr->getReg(), 0, AMDGPU::sub1)
1758 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
1759 .addReg(AMDGPU::VCC, RegState::Implicit);
1762 // This instructions is the _OFFSET variant, so we need to convert it to
1764 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
1765 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
1766 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
1768 // Create the new instruction.
1769 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
1770 MachineInstr *Addr64 =
1771 BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
1774 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
1775 // This will be replaced later
1776 // with the new value of vaddr.
1777 .addOperand(*SOffset)
1778 .addOperand(*Offset);
1780 MI->removeFromParent();
1783 NewVAddrLo = SRsrcPtrLo;
1784 NewVAddrHi = SRsrcPtrHi;
1785 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1786 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
1789 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1790 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1793 .addImm(AMDGPU::sub0)
1795 .addImm(AMDGPU::sub1);
1798 // Update the instruction to use NewVaddr
1799 VAddr->setReg(NewVAddr);
1800 // Update the instruction to use NewSRsrc
1801 SRsrc->setReg(NewSRsrc);
1805 void SIInstrInfo::splitSMRD(MachineInstr *MI,
1806 const TargetRegisterClass *HalfRC,
1807 unsigned HalfImmOp, unsigned HalfSGPROp,
1808 MachineInstr *&Lo, MachineInstr *&Hi) const {
1810 DebugLoc DL = MI->getDebugLoc();
1811 MachineBasicBlock *MBB = MI->getParent();
1812 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1813 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
1814 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
1815 unsigned HalfSize = HalfRC->getSize();
1816 const MachineOperand *OffOp =
1817 getNamedOperand(*MI, AMDGPU::OpName::offset);
1818 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
1820 // The SMRD has an 8-bit offset in dwords on SI and a 20-bit offset in bytes
1823 bool isVI = RI.ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS;
1824 unsigned OffScale = isVI ? 1 : 4;
1825 // Handle the _IMM variant
1826 unsigned LoOffset = OffOp->getImm() * OffScale;
1827 unsigned HiOffset = LoOffset + HalfSize;
1828 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
1830 .addImm(LoOffset / OffScale);
1832 if (!isUInt<20>(HiOffset) || (!isVI && !isUInt<8>(HiOffset / OffScale))) {
1833 unsigned OffsetSGPR =
1834 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1835 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
1836 .addImm(HiOffset); // The offset in register is in bytes.
1837 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
1839 .addReg(OffsetSGPR);
1841 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
1843 .addImm(HiOffset / OffScale);
1846 // Handle the _SGPR variant
1847 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
1848 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
1851 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1852 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
1855 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp))
1857 .addReg(OffsetSGPR);
1860 unsigned SubLo, SubHi;
1863 SubLo = AMDGPU::sub0;
1864 SubHi = AMDGPU::sub1;
1867 SubLo = AMDGPU::sub0_sub1;
1868 SubHi = AMDGPU::sub2_sub3;
1871 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
1872 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
1875 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
1876 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
1879 llvm_unreachable("Unhandled HalfSize");
1882 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE))
1883 .addOperand(MI->getOperand(0))
1890 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
1891 MachineBasicBlock *MBB = MI->getParent();
1892 switch (MI->getOpcode()) {
1893 case AMDGPU::S_LOAD_DWORD_IMM:
1894 case AMDGPU::S_LOAD_DWORD_SGPR:
1895 case AMDGPU::S_LOAD_DWORDX2_IMM:
1896 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1897 case AMDGPU::S_LOAD_DWORDX4_IMM:
1898 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1899 unsigned NewOpcode = getVALUOp(*MI);
1903 if (MI->getOperand(2).isReg()) {
1904 RegOffset = MI->getOperand(2).getReg();
1907 assert(MI->getOperand(2).isImm());
1908 // SMRD instructions take a dword offsets on SI and byte offset on VI
1909 // and MUBUF instructions always take a byte offset.
1910 ImmOffset = MI->getOperand(2).getImm();
1911 if (RI.ST.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS)
1913 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1915 if (isUInt<12>(ImmOffset)) {
1916 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1920 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1927 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1928 unsigned DWord0 = RegOffset;
1929 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1930 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1931 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1932 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1934 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
1936 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
1937 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1938 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
1939 .addImm(RsrcDataFormat >> 32);
1940 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
1942 .addImm(AMDGPU::sub0)
1944 .addImm(AMDGPU::sub1)
1946 .addImm(AMDGPU::sub2)
1948 .addImm(AMDGPU::sub3);
1949 MI->setDesc(get(NewOpcode));
1950 if (MI->getOperand(2).isReg()) {
1951 MI->getOperand(2).setReg(MI->getOperand(1).getReg());
1953 MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
1955 MI->getOperand(1).setReg(SRsrc);
1956 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0));
1957 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
1959 const TargetRegisterClass *NewDstRC =
1960 RI.getRegClass(get(NewOpcode).OpInfo[0].RegClass);
1962 unsigned DstReg = MI->getOperand(0).getReg();
1963 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1964 MRI.replaceRegWith(DstReg, NewDstReg);
1967 case AMDGPU::S_LOAD_DWORDX8_IMM:
1968 case AMDGPU::S_LOAD_DWORDX8_SGPR: {
1969 MachineInstr *Lo, *Hi;
1970 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
1971 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
1972 MI->eraseFromParent();
1973 moveSMRDToVALU(Lo, MRI);
1974 moveSMRDToVALU(Hi, MRI);
1978 case AMDGPU::S_LOAD_DWORDX16_IMM:
1979 case AMDGPU::S_LOAD_DWORDX16_SGPR: {
1980 MachineInstr *Lo, *Hi;
1981 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
1982 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
1983 MI->eraseFromParent();
1984 moveSMRDToVALU(Lo, MRI);
1985 moveSMRDToVALU(Hi, MRI);
1991 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
1992 SmallVector<MachineInstr *, 128> Worklist;
1993 Worklist.push_back(&TopInst);
1995 while (!Worklist.empty()) {
1996 MachineInstr *Inst = Worklist.pop_back_val();
1997 MachineBasicBlock *MBB = Inst->getParent();
1998 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2000 unsigned Opcode = Inst->getOpcode();
2001 unsigned NewOpcode = getVALUOp(*Inst);
2003 // Handle some special cases
2006 if (isSMRD(Inst->getOpcode())) {
2007 moveSMRDToVALU(Inst, MRI);
2010 case AMDGPU::S_MOV_B64: {
2011 DebugLoc DL = Inst->getDebugLoc();
2013 // If the source operand is a register we can replace this with a
2015 if (Inst->getOperand(1).isReg()) {
2016 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
2017 .addOperand(Inst->getOperand(0))
2018 .addOperand(Inst->getOperand(1));
2019 Worklist.push_back(Copy);
2021 // Otherwise, we need to split this into two movs, because there is
2022 // no 64-bit VALU move instruction.
2023 unsigned Reg = Inst->getOperand(0).getReg();
2024 unsigned Dst = split64BitImm(Worklist,
2027 MRI.getRegClass(Reg),
2028 Inst->getOperand(1));
2029 MRI.replaceRegWith(Reg, Dst);
2031 Inst->eraseFromParent();
2034 case AMDGPU::S_AND_B64:
2035 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32);
2036 Inst->eraseFromParent();
2039 case AMDGPU::S_OR_B64:
2040 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32);
2041 Inst->eraseFromParent();
2044 case AMDGPU::S_XOR_B64:
2045 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32);
2046 Inst->eraseFromParent();
2049 case AMDGPU::S_NOT_B64:
2050 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
2051 Inst->eraseFromParent();
2054 case AMDGPU::S_BCNT1_I32_B64:
2055 splitScalar64BitBCNT(Worklist, Inst);
2056 Inst->eraseFromParent();
2059 case AMDGPU::S_BFE_I64: {
2060 splitScalar64BitBFE(Worklist, Inst);
2061 Inst->eraseFromParent();
2065 case AMDGPU::S_LSHL_B32:
2066 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2067 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
2071 case AMDGPU::S_ASHR_I32:
2072 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2073 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
2077 case AMDGPU::S_LSHR_B32:
2078 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2079 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
2083 case AMDGPU::S_LSHL_B64:
2084 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2085 NewOpcode = AMDGPU::V_LSHLREV_B64;
2089 case AMDGPU::S_ASHR_I64:
2090 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2091 NewOpcode = AMDGPU::V_ASHRREV_I64;
2095 case AMDGPU::S_LSHR_B64:
2096 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2097 NewOpcode = AMDGPU::V_LSHRREV_B64;
2102 case AMDGPU::S_BFE_U64:
2103 case AMDGPU::S_BFM_B64:
2104 llvm_unreachable("Moving this op to VALU not implemented");
2107 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
2108 // We cannot move this instruction to the VALU, so we should try to
2109 // legalize its operands instead.
2110 legalizeOperands(Inst);
2114 // Use the new VALU Opcode.
2115 const MCInstrDesc &NewDesc = get(NewOpcode);
2116 Inst->setDesc(NewDesc);
2118 // Remove any references to SCC. Vector instructions can't read from it, and
2119 // We're just about to add the implicit use / defs of VCC, and we don't want
2121 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
2122 MachineOperand &Op = Inst->getOperand(i);
2123 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
2124 Inst->RemoveOperand(i);
2127 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
2128 // We are converting these to a BFE, so we need to add the missing
2129 // operands for the size and offset.
2130 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
2131 Inst->addOperand(MachineOperand::CreateImm(0));
2132 Inst->addOperand(MachineOperand::CreateImm(Size));
2134 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
2135 // The VALU version adds the second operand to the result, so insert an
2137 Inst->addOperand(MachineOperand::CreateImm(0));
2140 addDescImplicitUseDef(NewDesc, Inst);
2142 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
2143 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
2144 // If we need to move this to VGPRs, we need to unpack the second operand
2145 // back into the 2 separate ones for bit offset and width.
2146 assert(OffsetWidthOp.isImm() &&
2147 "Scalar BFE is only implemented for constant width and offset");
2148 uint32_t Imm = OffsetWidthOp.getImm();
2150 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2151 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2152 Inst->RemoveOperand(2); // Remove old immediate.
2153 Inst->addOperand(MachineOperand::CreateImm(Offset));
2154 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
2157 // Update the destination register class.
2159 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
2162 // For target instructions, getOpRegClass just returns the virtual
2163 // register class associated with the operand, so we need to find an
2164 // equivalent VGPR register class in order to move the instruction to the
2168 case AMDGPU::REG_SEQUENCE:
2169 case AMDGPU::INSERT_SUBREG:
2170 if (RI.hasVGPRs(NewDstRC))
2172 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
2180 unsigned DstReg = Inst->getOperand(0).getReg();
2181 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2182 MRI.replaceRegWith(DstReg, NewDstReg);
2184 // Legalize the operands
2185 legalizeOperands(Inst);
2187 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
2188 E = MRI.use_end(); I != E; ++I) {
2189 MachineInstr &UseMI = *I->getParent();
2190 if (!canReadVGPR(UseMI, I.getOperandNo())) {
2191 Worklist.push_back(&UseMI);
2197 //===----------------------------------------------------------------------===//
2198 // Indirect addressing callbacks
2199 //===----------------------------------------------------------------------===//
2201 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2202 unsigned Channel) const {
2203 assert(Channel == 0);
2207 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2208 return &AMDGPU::VGPR_32RegClass;
2211 void SIInstrInfo::splitScalar64BitUnaryOp(
2212 SmallVectorImpl<MachineInstr *> &Worklist,
2214 unsigned Opcode) const {
2215 MachineBasicBlock &MBB = *Inst->getParent();
2216 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2218 MachineOperand &Dest = Inst->getOperand(0);
2219 MachineOperand &Src0 = Inst->getOperand(1);
2220 DebugLoc DL = Inst->getDebugLoc();
2222 MachineBasicBlock::iterator MII = Inst;
2224 const MCInstrDesc &InstDesc = get(Opcode);
2225 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2226 MRI.getRegClass(Src0.getReg()) :
2227 &AMDGPU::SGPR_32RegClass;
2229 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2231 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2232 AMDGPU::sub0, Src0SubRC);
2234 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2235 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2237 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2238 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2239 .addOperand(SrcReg0Sub0);
2241 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2242 AMDGPU::sub1, Src0SubRC);
2244 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2245 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2246 .addOperand(SrcReg0Sub1);
2248 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2249 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2251 .addImm(AMDGPU::sub0)
2253 .addImm(AMDGPU::sub1);
2255 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2257 // Try to legalize the operands in case we need to swap the order to keep it
2259 Worklist.push_back(LoHalf);
2260 Worklist.push_back(HiHalf);
2263 void SIInstrInfo::splitScalar64BitBinaryOp(
2264 SmallVectorImpl<MachineInstr *> &Worklist,
2266 unsigned Opcode) const {
2267 MachineBasicBlock &MBB = *Inst->getParent();
2268 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2270 MachineOperand &Dest = Inst->getOperand(0);
2271 MachineOperand &Src0 = Inst->getOperand(1);
2272 MachineOperand &Src1 = Inst->getOperand(2);
2273 DebugLoc DL = Inst->getDebugLoc();
2275 MachineBasicBlock::iterator MII = Inst;
2277 const MCInstrDesc &InstDesc = get(Opcode);
2278 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2279 MRI.getRegClass(Src0.getReg()) :
2280 &AMDGPU::SGPR_32RegClass;
2282 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2283 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2284 MRI.getRegClass(Src1.getReg()) :
2285 &AMDGPU::SGPR_32RegClass;
2287 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2289 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2290 AMDGPU::sub0, Src0SubRC);
2291 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2292 AMDGPU::sub0, Src1SubRC);
2294 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2295 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2297 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2298 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2299 .addOperand(SrcReg0Sub0)
2300 .addOperand(SrcReg1Sub0);
2302 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2303 AMDGPU::sub1, Src0SubRC);
2304 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2305 AMDGPU::sub1, Src1SubRC);
2307 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2308 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2309 .addOperand(SrcReg0Sub1)
2310 .addOperand(SrcReg1Sub1);
2312 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2313 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2315 .addImm(AMDGPU::sub0)
2317 .addImm(AMDGPU::sub1);
2319 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2321 // Try to legalize the operands in case we need to swap the order to keep it
2323 Worklist.push_back(LoHalf);
2324 Worklist.push_back(HiHalf);
2327 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2328 MachineInstr *Inst) const {
2329 MachineBasicBlock &MBB = *Inst->getParent();
2330 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2332 MachineBasicBlock::iterator MII = Inst;
2333 DebugLoc DL = Inst->getDebugLoc();
2335 MachineOperand &Dest = Inst->getOperand(0);
2336 MachineOperand &Src = Inst->getOperand(1);
2338 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
2339 const TargetRegisterClass *SrcRC = Src.isReg() ?
2340 MRI.getRegClass(Src.getReg()) :
2341 &AMDGPU::SGPR_32RegClass;
2343 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2344 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2346 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2348 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2349 AMDGPU::sub0, SrcSubRC);
2350 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2351 AMDGPU::sub1, SrcSubRC);
2353 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg)
2354 .addOperand(SrcRegSub0)
2357 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2358 .addOperand(SrcRegSub1)
2361 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2363 Worklist.push_back(First);
2364 Worklist.push_back(Second);
2367 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
2368 MachineInstr *Inst) const {
2369 MachineBasicBlock &MBB = *Inst->getParent();
2370 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2371 MachineBasicBlock::iterator MII = Inst;
2372 DebugLoc DL = Inst->getDebugLoc();
2374 MachineOperand &Dest = Inst->getOperand(0);
2375 uint32_t Imm = Inst->getOperand(2).getImm();
2376 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2377 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2381 // Only sext_inreg cases handled.
2382 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 &&
2387 if (BitWidth < 32) {
2388 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2389 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2390 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2392 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
2393 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0)
2397 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
2401 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2403 .addImm(AMDGPU::sub0)
2405 .addImm(AMDGPU::sub1);
2407 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2411 MachineOperand &Src = Inst->getOperand(1);
2412 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2413 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2415 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
2417 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2419 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2420 .addReg(Src.getReg(), 0, AMDGPU::sub0)
2421 .addImm(AMDGPU::sub0)
2423 .addImm(AMDGPU::sub1);
2425 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2428 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
2429 MachineInstr *Inst) const {
2430 // Add the implict and explicit register definitions.
2431 if (NewDesc.ImplicitUses) {
2432 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
2433 unsigned Reg = NewDesc.ImplicitUses[i];
2434 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
2438 if (NewDesc.ImplicitDefs) {
2439 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
2440 unsigned Reg = NewDesc.ImplicitDefs[i];
2441 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
2446 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2447 int OpIndices[3]) const {
2448 const MCInstrDesc &Desc = get(MI->getOpcode());
2450 // Find the one SGPR operand we are allowed to use.
2451 unsigned SGPRReg = AMDGPU::NoRegister;
2453 // First we need to consider the instruction's operand requirements before
2454 // legalizing. Some operands are required to be SGPRs, such as implicit uses
2455 // of VCC, but we are still bound by the constant bus requirement to only use
2458 // If the operand's class is an SGPR, we can never move it.
2460 for (const MachineOperand &MO : MI->implicit_operands()) {
2461 // We only care about reads.
2465 if (MO.getReg() == AMDGPU::VCC)
2468 if (MO.getReg() == AMDGPU::FLAT_SCR)
2469 return AMDGPU::FLAT_SCR;
2472 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
2473 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2475 for (unsigned i = 0; i < 3; ++i) {
2476 int Idx = OpIndices[i];
2480 const MachineOperand &MO = MI->getOperand(Idx);
2481 if (RI.isSGPRClassID(Desc.OpInfo[Idx].RegClass))
2482 SGPRReg = MO.getReg();
2484 if (MO.isReg() && RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
2485 UsedSGPRs[i] = MO.getReg();
2488 if (SGPRReg != AMDGPU::NoRegister)
2491 // We don't have a required SGPR operand, so we have a bit more freedom in
2492 // selecting operands to move.
2494 // Try to select the most used SGPR. If an SGPR is equal to one of the
2495 // others, we choose that.
2498 // V_FMA_F32 v0, s0, s0, s0 -> No moves
2499 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
2501 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
2502 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
2503 SGPRReg = UsedSGPRs[0];
2506 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
2507 if (UsedSGPRs[1] == UsedSGPRs[2])
2508 SGPRReg = UsedSGPRs[1];
2514 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2515 MachineBasicBlock *MBB,
2516 MachineBasicBlock::iterator I,
2518 unsigned Address, unsigned OffsetReg) const {
2519 const DebugLoc &DL = MBB->findDebugLoc(I);
2520 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2521 getIndirectIndexBegin(*MBB->getParent()));
2523 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2524 .addReg(IndirectBaseReg, RegState::Define)
2525 .addOperand(I->getOperand(0))
2526 .addReg(IndirectBaseReg)
2532 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2533 MachineBasicBlock *MBB,
2534 MachineBasicBlock::iterator I,
2536 unsigned Address, unsigned OffsetReg) const {
2537 const DebugLoc &DL = MBB->findDebugLoc(I);
2538 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2539 getIndirectIndexBegin(*MBB->getParent()));
2541 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
2542 .addOperand(I->getOperand(0))
2543 .addOperand(I->getOperand(1))
2544 .addReg(IndirectBaseReg)
2550 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2551 const MachineFunction &MF) const {
2552 int End = getIndirectIndexEnd(MF);
2553 int Begin = getIndirectIndexBegin(MF);
2559 for (int Index = Begin; Index <= End; ++Index)
2560 Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index));
2562 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2563 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
2565 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
2566 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
2568 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
2569 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
2571 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
2572 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
2574 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
2575 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
2578 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
2579 unsigned OperandName) const {
2580 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
2584 return &MI.getOperand(Idx);
2587 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
2588 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
2589 if (ST.isAmdHsaOS())
2590 RsrcDataFormat |= (1ULL << 56);
2592 return RsrcDataFormat;