1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SI Instruction format definitions.
12 //===----------------------------------------------------------------------===//
14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
17 field bits<1> VM_CNT = 0;
18 field bits<1> EXP_CNT = 0;
19 field bits<1> LGKM_CNT = 0;
21 field bits<1> SALU = 0;
22 field bits<1> VALU = 0;
24 field bits<1> SOP1 = 0;
25 field bits<1> SOP2 = 0;
26 field bits<1> SOPC = 0;
27 field bits<1> SOPK = 0;
28 field bits<1> SOPP = 0;
30 field bits<1> VOP1 = 0;
31 field bits<1> VOP2 = 0;
32 field bits<1> VOP3 = 0;
33 field bits<1> VOPC = 0;
35 field bits<1> MUBUF = 0;
36 field bits<1> MTBUF = 0;
37 field bits<1> SMRD = 0;
39 field bits<1> MIMG = 0;
40 field bits<1> FLAT = 0;
41 field bits<1> WQM = 0;
42 field bits<1> VGPRSpill = 0;
44 // These need to be kept in sync with the enum in SIInstrFlags.
45 let TSFlags{0} = VM_CNT;
46 let TSFlags{1} = EXP_CNT;
47 let TSFlags{2} = LGKM_CNT;
49 let TSFlags{3} = SALU;
50 let TSFlags{4} = VALU;
52 let TSFlags{5} = SOP1;
53 let TSFlags{6} = SOP2;
54 let TSFlags{7} = SOPC;
55 let TSFlags{8} = SOPK;
56 let TSFlags{9} = SOPP;
58 let TSFlags{10} = VOP1;
59 let TSFlags{11} = VOP2;
60 let TSFlags{12} = VOP3;
61 let TSFlags{13} = VOPC;
63 let TSFlags{14} = MUBUF;
64 let TSFlags{15} = MTBUF;
65 let TSFlags{16} = SMRD;
67 let TSFlags{18} = MIMG;
68 let TSFlags{19} = FLAT;
69 let TSFlags{20} = WQM;
70 let TSFlags{21} = VGPRSpill;
72 // Most instructions require adjustments after selection to satisfy
73 // operand requirements.
74 let hasPostISelHook = 1;
75 let SchedRW = [Write32Bit];
88 class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
89 def VOPDstVCC : VOPDstOperand <VCCReg>;
91 let Uses = [EXEC] in {
93 class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
94 InstSI <outs, ins, asm, pattern> {
98 let hasSideEffects = 0;
99 let UseNamedOperandTable = 1;
103 class VOPCCommon <dag ins, string asm, list<dag> pattern> :
104 VOPAnyCommon <(outs VOPDstVCC:$dst), ins, asm, pattern> {
106 let DisableEncoding = "$dst";
111 class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
112 VOPAnyCommon <outs, ins, asm, pattern> {
118 class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> :
119 VOPAnyCommon <outs, ins, asm, pattern> {
125 class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
126 VOPAnyCommon <outs, ins, asm, pattern> {
128 // Using complex patterns gives VOP3 patterns a very high complexity rating,
129 // but standalone patterns are almost always prefered, so we need to adjust the
130 // priority lower. The goal is to use a high number to reduce complexity to
131 // zero (or less than zero).
132 let AddedComplexity = -1000;
137 let AsmMatchConverter = "cvtVOP3";
138 let isCodeGenOnly = 0;
143 } // End Uses = [EXEC]
145 //===----------------------------------------------------------------------===//
147 //===----------------------------------------------------------------------===//
149 class SOP1e <bits<8> op> : Enc32 {
153 let Inst{7-0} = ssrc0;
155 let Inst{22-16} = sdst;
156 let Inst{31-23} = 0x17d; //encoding;
159 class SOP2e <bits<7> op> : Enc32 {
164 let Inst{7-0} = ssrc0;
165 let Inst{15-8} = ssrc1;
166 let Inst{22-16} = sdst;
167 let Inst{29-23} = op;
168 let Inst{31-30} = 0x2; // encoding
171 class SOPCe <bits<7> op> : Enc32 {
175 let Inst{7-0} = ssrc0;
176 let Inst{15-8} = ssrc1;
177 let Inst{22-16} = op;
178 let Inst{31-23} = 0x17e;
181 class SOPKe <bits<5> op> : Enc32 {
185 let Inst{15-0} = simm16;
186 let Inst{22-16} = sdst;
187 let Inst{27-23} = op;
188 let Inst{31-28} = 0xb; //encoding
191 class SOPK64e <bits<5> op> : Enc64 {
196 let Inst{15-0} = simm16;
197 let Inst{22-16} = sdst;
198 let Inst{27-23} = op;
199 let Inst{31-28} = 0xb;
201 let Inst{63-32} = imm;
204 class SOPPe <bits<7> op> : Enc32 {
207 let Inst{15-0} = simm16;
208 let Inst{22-16} = op;
209 let Inst{31-23} = 0x17f; // encoding
212 class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
217 let Inst{7-0} = offset;
219 let Inst{14-9} = sbase{6-1};
220 let Inst{21-15} = sdst;
221 let Inst{26-22} = op;
222 let Inst{31-27} = 0x18; //encoding
225 let SchedRW = [WriteSALU] in {
226 class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
227 InstSI<outs, ins, asm, pattern> {
230 let hasSideEffects = 0;
231 let isCodeGenOnly = 0;
236 class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> :
237 InstSI <outs, ins, asm, pattern> {
241 let hasSideEffects = 0;
242 let isCodeGenOnly = 0;
246 let UseNamedOperandTable = 1;
249 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
250 InstSI<outs, ins, asm, pattern>, SOPCe <op> {
252 let DisableEncoding = "$dst";
255 let hasSideEffects = 0;
258 let isCodeGenOnly = 0;
260 let UseNamedOperandTable = 1;
263 class SOPK <dag outs, dag ins, string asm, list<dag> pattern> :
264 InstSI <outs, ins , asm, pattern> {
268 let hasSideEffects = 0;
272 let UseNamedOperandTable = 1;
275 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
276 InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
280 let hasSideEffects = 0;
284 let UseNamedOperandTable = 1;
287 } // let SchedRW = [WriteSALU]
289 class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
290 InstSI<outs, ins, asm, pattern> {
296 let hasSideEffects = 0;
297 let UseNamedOperandTable = 1;
298 let SchedRW = [WriteSMEM];
301 //===----------------------------------------------------------------------===//
302 // Vector ALU operations
303 //===----------------------------------------------------------------------===//
305 class VOP1e <bits<8> op> : Enc32 {
309 let Inst{8-0} = src0;
311 let Inst{24-17} = vdst;
312 let Inst{31-25} = 0x3f; //encoding
315 class VOP2e <bits<6> op> : Enc32 {
320 let Inst{8-0} = src0;
321 let Inst{16-9} = src1;
322 let Inst{24-17} = vdst;
323 let Inst{30-25} = op;
324 let Inst{31} = 0x0; //encoding
327 class VOP2_MADKe <bits<6> op> : Enc64 {
334 let Inst{8-0} = src0;
335 let Inst{16-9} = vsrc1;
336 let Inst{24-17} = vdst;
337 let Inst{30-25} = op;
338 let Inst{31} = 0x0; // encoding
339 let Inst{63-32} = src2;
342 class VOP3e <bits<9> op> : Enc64 {
344 bits<2> src0_modifiers;
346 bits<2> src1_modifiers;
348 bits<2> src2_modifiers;
353 let Inst{7-0} = vdst;
354 let Inst{8} = src0_modifiers{1};
355 let Inst{9} = src1_modifiers{1};
356 let Inst{10} = src2_modifiers{1};
357 let Inst{11} = clamp;
358 let Inst{25-17} = op;
359 let Inst{31-26} = 0x34; //encoding
360 let Inst{40-32} = src0;
361 let Inst{49-41} = src1;
362 let Inst{58-50} = src2;
363 let Inst{60-59} = omod;
364 let Inst{61} = src0_modifiers{0};
365 let Inst{62} = src1_modifiers{0};
366 let Inst{63} = src2_modifiers{0};
369 class VOP3be <bits<9> op> : Enc64 {
371 bits<2> src0_modifiers;
373 bits<2> src1_modifiers;
375 bits<2> src2_modifiers;
380 let Inst{7-0} = vdst;
381 let Inst{14-8} = sdst;
382 let Inst{25-17} = op;
383 let Inst{31-26} = 0x34; //encoding
384 let Inst{40-32} = src0;
385 let Inst{49-41} = src1;
386 let Inst{58-50} = src2;
387 let Inst{60-59} = omod;
388 let Inst{61} = src0_modifiers{0};
389 let Inst{62} = src1_modifiers{0};
390 let Inst{63} = src2_modifiers{0};
393 class VOPCe <bits<8> op> : Enc32 {
397 let Inst{8-0} = src0;
398 let Inst{16-9} = vsrc1;
399 let Inst{24-17} = op;
400 let Inst{31-25} = 0x3e;
403 class VINTRPe <bits<2> op> : Enc32 {
409 let Inst{7-0} = vsrc;
410 let Inst{9-8} = attrchan;
411 let Inst{15-10} = attr;
412 let Inst{17-16} = op;
413 let Inst{25-18} = vdst;
414 let Inst{31-26} = 0x32; // encoding
417 class DSe <bits<8> op> : Enc64 {
426 let Inst{7-0} = offset0;
427 let Inst{15-8} = offset1;
429 let Inst{25-18} = op;
430 let Inst{31-26} = 0x36; //encoding
431 let Inst{39-32} = addr;
432 let Inst{47-40} = data0;
433 let Inst{55-48} = data1;
434 let Inst{63-56} = vdst;
437 class MUBUFe <bits<7> op> : Enc64 {
451 let Inst{11-0} = offset;
452 let Inst{12} = offen;
453 let Inst{13} = idxen;
455 let Inst{15} = addr64;
457 let Inst{24-18} = op;
458 let Inst{31-26} = 0x38; //encoding
459 let Inst{39-32} = vaddr;
460 let Inst{47-40} = vdata;
461 let Inst{52-48} = srsrc{6-2};
464 let Inst{63-56} = soffset;
467 class MTBUFe <bits<3> op> : Enc64 {
482 let Inst{11-0} = offset;
483 let Inst{12} = offen;
484 let Inst{13} = idxen;
486 let Inst{15} = addr64;
487 let Inst{18-16} = op;
488 let Inst{22-19} = dfmt;
489 let Inst{25-23} = nfmt;
490 let Inst{31-26} = 0x3a; //encoding
491 let Inst{39-32} = vaddr;
492 let Inst{47-40} = vdata;
493 let Inst{52-48} = srsrc{6-2};
496 let Inst{63-56} = soffset;
499 class MIMGe <bits<7> op> : Enc64 {
513 let Inst{11-8} = dmask;
514 let Inst{12} = unorm;
520 let Inst{24-18} = op;
522 let Inst{31-26} = 0x3c;
523 let Inst{39-32} = vaddr;
524 let Inst{47-40} = vdata;
525 let Inst{52-48} = srsrc{6-2};
526 let Inst{57-53} = ssamp{6-2};
529 class FLATe<bits<7> op> : Enc64 {
540 let Inst{24-18} = op;
541 let Inst{31-26} = 0x37; // Encoding.
542 let Inst{39-32} = addr;
543 let Inst{47-40} = data;
544 // 54-48 is reserved.
546 let Inst{63-56} = vdst;
562 let Inst{10} = compr;
565 let Inst{31-26} = 0x3e;
566 let Inst{39-32} = vsrc0;
567 let Inst{47-40} = vsrc1;
568 let Inst{55-48} = vsrc2;
569 let Inst{63-56} = vsrc3;
572 let Uses = [EXEC] in {
574 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
575 VOP1Common <outs, ins, asm, pattern>,
577 let isCodeGenOnly = 0;
580 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
581 VOP2Common <outs, ins, asm, pattern>, VOP2e<op> {
582 let isCodeGenOnly = 0;
585 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
586 VOPCCommon <ins, asm, pattern>, VOPCe <op>;
588 class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
589 InstSI <outs, ins, asm, pattern> {
592 let hasSideEffects = 0;
595 } // End Uses = [EXEC]
597 //===----------------------------------------------------------------------===//
598 // Vector I/O operations
599 //===----------------------------------------------------------------------===//
601 let Uses = [EXEC] in {
603 class DS <dag outs, dag ins, string asm, list<dag> pattern> :
604 InstSI <outs, ins, asm, pattern> {
608 let UseNamedOperandTable = 1;
611 // Most instruction load and store data, so set this as the default.
615 let hasSideEffects = 0;
616 let AsmMatchConverter = "cvtDS";
617 let SchedRW = [WriteLDS];
620 class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
621 InstSI<outs, ins, asm, pattern> {
627 let hasSideEffects = 0;
628 let UseNamedOperandTable = 1;
629 let AsmMatchConverter = "cvtMubuf";
630 let SchedRW = [WriteVMEM];
633 class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
634 InstSI<outs, ins, asm, pattern> {
640 let hasSideEffects = 0;
641 let UseNamedOperandTable = 1;
642 let SchedRW = [WriteVMEM];
645 class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
646 InstSI<outs, ins, asm, pattern>, FLATe <op> {
648 // Internally, FLAT instruction are executed as both an LDS and a
649 // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
650 // and are not considered done until both have been decremented.
654 let Uses = [EXEC, FLAT_SCR]; // M0
656 let UseNamedOperandTable = 1;
657 let hasSideEffects = 0;
660 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
661 InstSI <outs, ins, asm, pattern>, MIMGe <op> {
667 let hasSideEffects = 0; // XXX ????
671 } // End Uses = [EXEC]