1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI DAG Lowering interface definition
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_R600_SIISELLOWERING_H
16 #define LLVM_LIB_TARGET_R600_SIISELLOWERING_H
18 #include "AMDGPUISelLowering.h"
19 #include "SIInstrInfo.h"
23 class SITargetLowering : public AMDGPUTargetLowering {
24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
25 SDValue Chain, unsigned Offset, bool Signed) const;
26 SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
27 SelectionDAG &DAG) const;
28 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
29 SelectionDAG &DAG) const override;
31 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
32 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
33 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
34 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
35 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
36 SDValue LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
39 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
40 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const;
41 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
42 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
43 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
45 bool foldImm(SDValue &Operand, int32_t &Immediate,
46 bool &ScalarSlotUsed) const;
47 const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG,
48 const SDValue &Op) const;
49 bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
50 unsigned RegClass) const;
52 SDNode *legalizeOperands(MachineSDNode *N, SelectionDAG &DAG) const;
53 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
54 MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const;
56 static SDValue performUCharToFloatCombine(SDNode *N,
57 DAGCombinerInfo &DCI);
58 SDValue performSHLPtrCombine(SDNode *N,
60 DAGCombinerInfo &DCI) const;
63 SITargetLowering(TargetMachine &tm);
65 bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
66 EVT /*VT*/) const override;
68 bool isLegalAddressingMode(const AddrMode &AM,
69 Type *Ty) const override;
71 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
73 bool *IsFast) const override;
75 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
76 unsigned SrcAlign, bool IsMemset,
79 MachineFunction &MF) const override;
81 TargetLoweringBase::LegalizeTypeAction
82 getPreferredVectorAction(EVT VT) const override;
84 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
85 Type *Ty) const override;
87 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
89 const SmallVectorImpl<ISD::InputArg> &Ins,
90 SDLoc DL, SelectionDAG &DAG,
91 SmallVectorImpl<SDValue> &InVals) const override;
93 MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
94 MachineBasicBlock * BB) const override;
95 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
96 MVT getScalarShiftAmountTy(EVT VT) const override;
97 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
98 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
99 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
100 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
101 void AdjustInstrPostInstrSelection(MachineInstr *MI,
102 SDNode *Node) const override;
104 int32_t analyzeImmediate(const SDNode *N) const;
105 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
106 unsigned Reg, EVT VT) const override;
107 void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
110 } // End namespace llvm