1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI DAG Lowering interface definition
13 //===----------------------------------------------------------------------===//
15 #ifndef SIISELLOWERING_H
16 #define SIISELLOWERING_H
18 #include "AMDGPUISelLowering.h"
19 #include "SIInstrInfo.h"
23 class SITargetLowering : public AMDGPUTargetLowering {
24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
25 SDValue Chain, unsigned Offset, bool Signed) const;
26 SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
27 SelectionDAG &DAG) const;
28 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
29 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
30 SDValue LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const;
31 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
32 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
33 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
34 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
35 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
36 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
38 bool foldImm(SDValue &Operand, int32_t &Immediate,
39 bool &ScalarSlotUsed) const;
40 const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG,
41 const SDValue &Op) const;
42 bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
43 unsigned RegClass) const;
44 void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
45 unsigned RegClass, bool &ScalarSlotUsed) const;
47 SDNode *foldOperands(MachineSDNode *N, SelectionDAG &DAG) const;
48 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
49 MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const;
51 static SDValue performUCharToFloatCombine(SDNode *N,
52 DAGCombinerInfo &DCI);
55 SITargetLowering(TargetMachine &tm);
56 bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS,
57 bool *IsFast) const override;
59 TargetLoweringBase::LegalizeTypeAction
60 getPreferredVectorAction(EVT VT) const override;
62 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
63 Type *Ty) const override;
65 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
67 const SmallVectorImpl<ISD::InputArg> &Ins,
68 SDLoc DL, SelectionDAG &DAG,
69 SmallVectorImpl<SDValue> &InVals) const override;
71 MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
72 MachineBasicBlock * BB) const override;
73 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
74 MVT getScalarShiftAmountTy(EVT VT) const override;
75 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
76 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
77 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
78 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
79 void AdjustInstrPostInstrSelection(MachineInstr *MI,
80 SDNode *Node) const override;
82 int32_t analyzeImmediate(const SDNode *N) const;
83 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
84 unsigned Reg, EVT VT) const override;
87 } // End namespace llvm
89 #endif //SIISELLOWERING_H