1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for SI
13 //===----------------------------------------------------------------------===//
15 #include "SIISelLowering.h"
17 #include "AMDGPUIntrinsicInfo.h"
18 #include "AMDGPUSubtarget.h"
19 #include "SIInstrInfo.h"
20 #include "SIMachineFunctionInfo.h"
21 #include "SIRegisterInfo.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/ADT/SmallString.h"
31 SITargetLowering::SITargetLowering(TargetMachine &TM) :
32 AMDGPUTargetLowering(TM) {
33 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
34 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
36 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
37 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
39 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
40 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
42 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
43 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
44 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
46 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
47 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
49 addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
50 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
52 addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
53 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
55 computeRegisterProperties();
58 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
59 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
60 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
61 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
62 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
63 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
65 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
66 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
67 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
68 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
69 setCondCodeAction(ISD::SETULE, MVT::f64, Expand);
70 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
72 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
73 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
74 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
75 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
77 setOperationAction(ISD::ADD, MVT::i32, Legal);
78 setOperationAction(ISD::ADDC, MVT::i32, Legal);
79 setOperationAction(ISD::ADDE, MVT::i32, Legal);
80 setOperationAction(ISD::SUBC, MVT::i32, Legal);
81 setOperationAction(ISD::SUBE, MVT::i32, Legal);
83 // We need to custom lower vector stores from local memory
84 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
85 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
86 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
87 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
89 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
90 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
92 // We need to custom lower loads/stores from private memory
93 setOperationAction(ISD::LOAD, MVT::i32, Custom);
94 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
95 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
96 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
98 setOperationAction(ISD::STORE, MVT::i1, Custom);
99 setOperationAction(ISD::STORE, MVT::i32, Custom);
100 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
101 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
103 setOperationAction(ISD::SELECT, MVT::f32, Promote);
104 AddPromotedToType(ISD::SELECT, MVT::f32, MVT::i32);
105 setOperationAction(ISD::SELECT, MVT::i64, Custom);
106 setOperationAction(ISD::SELECT, MVT::f64, Promote);
107 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
109 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
110 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
111 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
112 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
114 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
115 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
125 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
126 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
127 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
129 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Custom);
131 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
133 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
134 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
135 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
136 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
138 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
139 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
141 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
142 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
143 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
144 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Expand);
145 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, Expand);
146 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, Expand);
148 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
149 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
150 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
151 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
153 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
154 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
155 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Custom);
156 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Expand);
157 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
159 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
160 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
161 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
162 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
163 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
164 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
166 setOperationAction(ISD::LOAD, MVT::i1, Custom);
168 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
169 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
170 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
172 // These should use UDIVREM, so set them to expand
173 setOperationAction(ISD::UDIV, MVT::i64, Expand);
174 setOperationAction(ISD::UREM, MVT::i64, Expand);
176 // We only support LOAD/STORE and vector manipulation ops for vectors
177 // with > 4 elements.
179 MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32
182 for (MVT VT : VecTypes) {
183 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
187 case ISD::BUILD_VECTOR:
189 case ISD::EXTRACT_VECTOR_ELT:
190 case ISD::INSERT_VECTOR_ELT:
191 case ISD::CONCAT_VECTORS:
192 case ISD::INSERT_SUBVECTOR:
193 case ISD::EXTRACT_SUBVECTOR:
196 setOperationAction(Op, VT, Expand);
202 for (int I = MVT::v1f64; I <= MVT::v8f64; ++I) {
203 MVT::SimpleValueType VT = static_cast<MVT::SimpleValueType>(I);
204 setOperationAction(ISD::FTRUNC, VT, Expand);
205 setOperationAction(ISD::FCEIL, VT, Expand);
206 setOperationAction(ISD::FFLOOR, VT, Expand);
209 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
210 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
211 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
212 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
213 setOperationAction(ISD::FRINT, MVT::f64, Legal);
216 // FIXME: These should be removed and handled the same was as f32 fneg. Source
217 // modifiers also work for the double instructions.
218 setOperationAction(ISD::FNEG, MVT::f64, Expand);
219 setOperationAction(ISD::FABS, MVT::f64, Expand);
221 setTargetDAGCombine(ISD::SELECT_CC);
222 setTargetDAGCombine(ISD::SETCC);
224 setTargetDAGCombine(ISD::UINT_TO_FP);
226 setSchedulingPreference(Sched::RegPressure);
229 //===----------------------------------------------------------------------===//
230 // TargetLowering queries
231 //===----------------------------------------------------------------------===//
233 bool SITargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
235 bool *IsFast) const {
239 // XXX: This depends on the address space and also we may want to revist
240 // the alignment values we specify in the DataLayout.
242 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
243 // which isn't a simple VT.
244 if (!VT.isSimple() || VT == MVT::Other)
247 // XXX - CI changes say "Support for unaligned memory accesses" but I don't
248 // see what for specifically. The wording everywhere else seems to be the
251 // 3.6.4 - Operations using pairs of VGPRs (for example: double-floats) have
252 // no alignment restrictions.
253 if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS) {
254 // Using any pair of GPRs should be the same as any other pair.
257 return VT.bitsGE(MVT::i64);
260 // XXX - The only mention I see of this in the ISA manual is for LDS direct
261 // reads the "byte address and must be dword aligned". Is it also true for the
262 // normal loads and stores?
263 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS)
266 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
267 // byte-address are ignored, thus forcing Dword alignment.
270 return VT.bitsGT(MVT::i32);
273 bool SITargetLowering::shouldSplitVectorType(EVT VT) const {
274 return VT.getScalarType().bitsLE(MVT::i16);
277 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
279 const SIInstrInfo *TII =
280 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
281 return TII->isInlineConstant(Imm);
284 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
285 SDLoc DL, SDValue Chain,
286 unsigned Offset, bool Signed) const {
287 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
288 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
289 AMDGPUAS::CONSTANT_ADDRESS);
290 SDValue BasePtr = DAG.getCopyFromReg(Chain, DL,
291 MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64);
292 SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
293 DAG.getConstant(Offset, MVT::i64));
294 return DAG.getExtLoad(Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD, DL, VT, Chain, Ptr,
295 MachinePointerInfo(UndefValue::get(PtrTy)), MemVT,
296 false, false, MemVT.getSizeInBits() >> 3);
300 SDValue SITargetLowering::LowerFormalArguments(
302 CallingConv::ID CallConv,
304 const SmallVectorImpl<ISD::InputArg> &Ins,
305 SDLoc DL, SelectionDAG &DAG,
306 SmallVectorImpl<SDValue> &InVals) const {
308 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
310 MachineFunction &MF = DAG.getMachineFunction();
311 FunctionType *FType = MF.getFunction()->getFunctionType();
312 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
314 assert(CallConv == CallingConv::C);
316 SmallVector<ISD::InputArg, 16> Splits;
317 uint32_t Skipped = 0;
319 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
320 const ISD::InputArg &Arg = Ins[i];
322 // First check if it's a PS input addr
323 if (Info->ShaderType == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
324 !Arg.Flags.isByVal()) {
326 assert((PSInputNum <= 15) && "Too many PS inputs!");
329 // We can savely skip PS inputs
335 Info->PSInputAddr |= 1 << PSInputNum++;
338 // Second split vertices into their elements
339 if (Info->ShaderType != ShaderType::COMPUTE && Arg.VT.isVector()) {
340 ISD::InputArg NewArg = Arg;
341 NewArg.Flags.setSplit();
342 NewArg.VT = Arg.VT.getVectorElementType();
344 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
345 // three or five element vertex only needs three or five registers,
346 // NOT four or eigth.
347 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
348 unsigned NumElements = ParamType->getVectorNumElements();
350 for (unsigned j = 0; j != NumElements; ++j) {
351 Splits.push_back(NewArg);
352 NewArg.PartOffset += NewArg.VT.getStoreSize();
355 } else if (Info->ShaderType != ShaderType::COMPUTE) {
356 Splits.push_back(Arg);
360 SmallVector<CCValAssign, 16> ArgLocs;
361 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
362 getTargetMachine(), ArgLocs, *DAG.getContext());
364 // At least one interpolation mode must be enabled or else the GPU will hang.
365 if (Info->ShaderType == ShaderType::PIXEL && (Info->PSInputAddr & 0x7F) == 0) {
366 Info->PSInputAddr |= 1;
367 CCInfo.AllocateReg(AMDGPU::VGPR0);
368 CCInfo.AllocateReg(AMDGPU::VGPR1);
371 // The pointer to the list of arguments is stored in SGPR0, SGPR1
372 if (Info->ShaderType == ShaderType::COMPUTE) {
373 CCInfo.AllocateReg(AMDGPU::SGPR0);
374 CCInfo.AllocateReg(AMDGPU::SGPR1);
375 MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass);
378 if (Info->ShaderType == ShaderType::COMPUTE) {
379 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
383 AnalyzeFormalArguments(CCInfo, Splits);
385 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
387 const ISD::InputArg &Arg = Ins[i];
388 if (Skipped & (1 << i)) {
389 InVals.push_back(DAG.getUNDEF(Arg.VT));
393 CCValAssign &VA = ArgLocs[ArgIdx++];
394 EVT VT = VA.getLocVT();
398 EVT MemVT = Splits[i].VT;
399 // The first 36 bytes of the input buffer contains information about
400 // thread group and global sizes.
401 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, DAG.getRoot(),
402 36 + VA.getLocMemOffset(),
403 Ins[i].Flags.isSExt());
404 InVals.push_back(Arg);
407 assert(VA.isRegLoc() && "Parameter must be in a register!");
409 unsigned Reg = VA.getLocReg();
411 if (VT == MVT::i64) {
412 // For now assume it is a pointer
413 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
414 &AMDGPU::SReg_64RegClass);
415 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
416 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
420 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
422 Reg = MF.addLiveIn(Reg, RC);
423 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
425 if (Arg.VT.isVector()) {
427 // Build a vector from the registers
428 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
429 unsigned NumElements = ParamType->getVectorNumElements();
431 SmallVector<SDValue, 4> Regs;
433 for (unsigned j = 1; j != NumElements; ++j) {
434 Reg = ArgLocs[ArgIdx++].getLocReg();
435 Reg = MF.addLiveIn(Reg, RC);
436 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
439 // Fill up the missing vector elements
440 NumElements = Arg.VT.getVectorNumElements() - NumElements;
441 for (unsigned j = 0; j != NumElements; ++j)
442 Regs.push_back(DAG.getUNDEF(VT));
444 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
448 InVals.push_back(Val);
453 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
454 MachineInstr * MI, MachineBasicBlock * BB) const {
456 MachineBasicBlock::iterator I = *MI;
457 const SIInstrInfo *TII =
458 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
459 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
461 switch (MI->getOpcode()) {
463 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
464 case AMDGPU::BRANCH: return BB;
465 case AMDGPU::SI_ADDR64_RSRC: {
466 unsigned SuperReg = MI->getOperand(0).getReg();
467 unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
468 unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
469 unsigned SubRegHiHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
470 unsigned SubRegHiLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
471 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo)
472 .addOperand(MI->getOperand(1));
473 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
475 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
476 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
477 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
479 .addImm(AMDGPU::sub0)
481 .addImm(AMDGPU::sub1);
482 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
484 .addImm(AMDGPU::sub0_sub1)
486 .addImm(AMDGPU::sub2_sub3);
487 MI->eraseFromParent();
490 case AMDGPU::V_SUB_F64: {
491 unsigned DestReg = MI->getOperand(0).getReg();
492 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64), DestReg)
493 .addImm(0) // SRC0 modifiers
494 .addReg(MI->getOperand(1).getReg())
495 .addImm(1) // SRC1 modifiers
496 .addReg(MI->getOperand(2).getReg())
497 .addImm(0) // SRC2 modifiers
501 MI->eraseFromParent();
504 case AMDGPU::SI_RegisterStorePseudo: {
505 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
506 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
507 MachineInstrBuilder MIB =
508 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
510 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
511 MIB.addOperand(MI->getOperand(i));
513 MI->eraseFromParent();
516 case AMDGPU::FABS_SI: {
517 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
518 const SIInstrInfo *TII =
519 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
520 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
521 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
524 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_AND_B32_e32),
525 MI->getOperand(0).getReg())
526 .addReg(MI->getOperand(1).getReg())
528 MI->eraseFromParent();
531 case AMDGPU::FNEG_SI: {
532 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
533 const SIInstrInfo *TII =
534 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
535 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
536 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
539 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_XOR_B32_e32),
540 MI->getOperand(0).getReg())
541 .addReg(MI->getOperand(1).getReg())
543 MI->eraseFromParent();
546 case AMDGPU::FCLAMP_SI: {
547 const SIInstrInfo *TII =
548 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
549 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F32_e64),
550 MI->getOperand(0).getReg())
551 .addImm(0) // SRC0 modifiers
552 .addOperand(MI->getOperand(1))
553 .addImm(0) // SRC1 modifiers
557 MI->eraseFromParent();
563 EVT SITargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
564 if (!VT.isVector()) {
567 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
570 MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {
574 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
575 VT = VT.getScalarType();
580 switch (VT.getSimpleVT().SimpleTy) {
582 return false; /* There is V_MAD_F32 for f32 */
592 //===----------------------------------------------------------------------===//
593 // Custom DAG Lowering Operations
594 //===----------------------------------------------------------------------===//
596 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
597 MachineFunction &MF = DAG.getMachineFunction();
598 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
599 switch (Op.getOpcode()) {
600 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
601 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
603 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
604 EVT VT = Op.getValueType();
606 // These loads are legal.
607 if (Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
608 VT.isVector() && VT.getVectorNumElements() == 2 &&
609 VT.getVectorElementType() == MVT::i32)
612 if (Op.getValueType().isVector() &&
613 (Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
614 Load->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS ||
615 (Load->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
616 Op.getValueType().getVectorNumElements() > 4))) {
617 SDValue MergedValues[2] = {
618 SplitVectorLoad(Op, DAG),
621 return DAG.getMergeValues(MergedValues, SDLoc(Op));
623 return LowerLOAD(Op, DAG);
627 case ISD::SELECT: return LowerSELECT(Op, DAG);
628 case ISD::STORE: return LowerSTORE(Op, DAG);
629 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
630 case ISD::INTRINSIC_WO_CHAIN: {
631 unsigned IntrinsicID =
632 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
633 EVT VT = Op.getValueType();
635 //XXX: Hardcoded we only use two to store the pointer to the parameters.
636 unsigned NumUserSGPRs = 2;
637 switch (IntrinsicID) {
638 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
639 case Intrinsic::r600_read_ngroups_x:
640 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 0, false);
641 case Intrinsic::r600_read_ngroups_y:
642 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 4, false);
643 case Intrinsic::r600_read_ngroups_z:
644 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 8, false);
645 case Intrinsic::r600_read_global_size_x:
646 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 12, false);
647 case Intrinsic::r600_read_global_size_y:
648 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 16, false);
649 case Intrinsic::r600_read_global_size_z:
650 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 20, false);
651 case Intrinsic::r600_read_local_size_x:
652 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 24, false);
653 case Intrinsic::r600_read_local_size_y:
654 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 28, false);
655 case Intrinsic::r600_read_local_size_z:
656 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 32, false);
657 case Intrinsic::r600_read_tgid_x:
658 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
659 AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 0), VT);
660 case Intrinsic::r600_read_tgid_y:
661 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
662 AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 1), VT);
663 case Intrinsic::r600_read_tgid_z:
664 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
665 AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 2), VT);
666 case Intrinsic::r600_read_tidig_x:
667 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
669 case Intrinsic::r600_read_tidig_y:
670 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
672 case Intrinsic::r600_read_tidig_z:
673 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
675 case AMDGPUIntrinsic::SI_load_const: {
681 MachineMemOperand *MMO = MF.getMachineMemOperand(
682 MachinePointerInfo(),
683 MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
684 VT.getSizeInBits() / 8, 4);
685 return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
686 Op->getVTList(), Ops, VT, MMO);
688 case AMDGPUIntrinsic::SI_sample:
689 return LowerSampleIntrinsic(AMDGPUISD::SAMPLE, Op, DAG);
690 case AMDGPUIntrinsic::SI_sampleb:
691 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEB, Op, DAG);
692 case AMDGPUIntrinsic::SI_sampled:
693 return LowerSampleIntrinsic(AMDGPUISD::SAMPLED, Op, DAG);
694 case AMDGPUIntrinsic::SI_samplel:
695 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEL, Op, DAG);
696 case AMDGPUIntrinsic::SI_vs_load_input:
697 return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
704 case ISD::INTRINSIC_VOID:
705 SDValue Chain = Op.getOperand(0);
706 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
708 switch (IntrinsicID) {
709 case AMDGPUIntrinsic::SI_tbuffer_store: {
727 EVT VT = Op.getOperand(3).getValueType();
729 MachineMemOperand *MMO = MF.getMachineMemOperand(
730 MachinePointerInfo(),
731 MachineMemOperand::MOStore,
732 VT.getSizeInBits() / 8, 4);
733 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
734 Op->getVTList(), Ops, VT, MMO);
743 /// \brief Helper function for LowerBRCOND
744 static SDNode *findUser(SDValue Value, unsigned Opcode) {
746 SDNode *Parent = Value.getNode();
747 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
750 if (I.getUse().get() != Value)
753 if (I->getOpcode() == Opcode)
759 /// This transforms the control flow intrinsics to get the branch destination as
760 /// last parameter, also switches branch target with BR if the need arise
761 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
762 SelectionDAG &DAG) const {
766 SDNode *Intr = BRCOND.getOperand(1).getNode();
767 SDValue Target = BRCOND.getOperand(2);
768 SDNode *BR = nullptr;
770 if (Intr->getOpcode() == ISD::SETCC) {
771 // As long as we negate the condition everything is fine
772 SDNode *SetCC = Intr;
773 assert(SetCC->getConstantOperandVal(1) == 1);
774 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
776 Intr = SetCC->getOperand(0).getNode();
779 // Get the target from BR if we don't negate the condition
780 BR = findUser(BRCOND, ISD::BR);
781 Target = BR->getOperand(1);
784 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
786 // Build the result and
787 SmallVector<EVT, 4> Res;
788 for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i)
789 Res.push_back(Intr->getValueType(i));
791 // operands of the new intrinsic call
792 SmallVector<SDValue, 4> Ops;
793 Ops.push_back(BRCOND.getOperand(0));
794 for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i)
795 Ops.push_back(Intr->getOperand(i));
796 Ops.push_back(Target);
798 // build the new intrinsic call
799 SDNode *Result = DAG.getNode(
800 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
801 DAG.getVTList(Res), Ops).getNode();
804 // Give the branch instruction our target
809 DAG.MorphNodeTo(BR, ISD::BR, BR->getVTList(), Ops);
812 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
814 // Copy the intrinsic results to registers
815 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
816 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
820 Chain = DAG.getCopyToReg(
822 CopyToReg->getOperand(1),
823 SDValue(Result, i - 1),
826 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
829 // Remove the old intrinsic from the chain
830 DAG.ReplaceAllUsesOfValueWith(
831 SDValue(Intr, Intr->getNumValues() - 1),
832 Intr->getOperand(0));
837 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
839 LoadSDNode *Load = cast<LoadSDNode>(Op);
840 SDValue Ret = AMDGPUTargetLowering::LowerLOAD(Op, DAG);
841 SDValue MergedValues[2];
842 MergedValues[1] = Load->getChain();
844 MergedValues[0] = Ret;
845 return DAG.getMergeValues(MergedValues, DL);
848 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
852 EVT MemVT = Load->getMemoryVT();
854 assert(!MemVT.isVector() && "Private loads should be scalarized");
855 assert(!MemVT.isFloatingPoint() && "FP loads should be promoted to int");
857 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
858 DAG.getConstant(2, MVT::i32));
859 Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
860 Load->getChain(), Ptr,
861 DAG.getTargetConstant(0, MVT::i32),
863 if (MemVT.getSizeInBits() == 64) {
864 SDValue IncPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
865 DAG.getConstant(1, MVT::i32));
867 SDValue LoadUpper = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
868 Load->getChain(), IncPtr,
869 DAG.getTargetConstant(0, MVT::i32),
872 Ret = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ret, LoadUpper);
875 MergedValues[0] = Ret;
876 return DAG.getMergeValues(MergedValues, DL);
880 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
882 SelectionDAG &DAG) const {
883 return DAG.getNode(Opcode, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
889 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
890 if (Op.getValueType() != MVT::i64)
894 SDValue Cond = Op.getOperand(0);
896 SDValue Zero = DAG.getConstant(0, MVT::i32);
897 SDValue One = DAG.getConstant(1, MVT::i32);
899 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
900 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
902 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
903 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
905 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
907 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
908 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
910 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
912 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
913 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
916 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
918 StoreSDNode *Store = cast<StoreSDNode>(Op);
919 EVT VT = Store->getMemoryVT();
921 // These stores are legal.
922 if (Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
923 VT.isVector() && VT.getVectorNumElements() == 2 &&
924 VT.getVectorElementType() == MVT::i32)
927 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
931 if (VT.isVector() && VT.getVectorNumElements() >= 8)
932 return SplitVectorStore(Op, DAG);
935 return DAG.getTruncStore(Store->getChain(), DL,
936 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
937 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
939 if (Store->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS)
942 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Store->getBasePtr(),
943 DAG.getConstant(2, MVT::i32));
944 SDValue Chain = Store->getChain();
945 SmallVector<SDValue, 8> Values;
947 if (Store->isTruncatingStore()) {
949 if (Store->getMemoryVT() == MVT::i8) {
951 } else if (Store->getMemoryVT() == MVT::i16) {
954 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
955 Chain, Store->getBasePtr(),
956 DAG.getConstant(0, MVT::i32));
957 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, Store->getBasePtr(),
958 DAG.getConstant(0x3, MVT::i32));
959 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
960 DAG.getConstant(3, MVT::i32));
961 SDValue MaskedValue = DAG.getNode(ISD::AND, DL, MVT::i32, Store->getValue(),
962 DAG.getConstant(Mask, MVT::i32));
963 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
964 MaskedValue, ShiftAmt);
965 SDValue RotrAmt = DAG.getNode(ISD::SUB, DL, MVT::i32,
966 DAG.getConstant(32, MVT::i32), ShiftAmt);
967 SDValue DstMask = DAG.getNode(ISD::ROTR, DL, MVT::i32,
968 DAG.getConstant(Mask, MVT::i32),
970 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
971 Dst = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
973 Values.push_back(Dst);
974 } else if (VT == MVT::i64) {
975 for (unsigned i = 0; i < 2; ++i) {
976 Values.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
977 Store->getValue(), DAG.getConstant(i, MVT::i32)));
979 } else if (VT == MVT::i128) {
980 for (unsigned i = 0; i < 2; ++i) {
981 for (unsigned j = 0; j < 2; ++j) {
982 Values.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
983 DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i64,
984 Store->getValue(), DAG.getConstant(i, MVT::i32)),
985 DAG.getConstant(j, MVT::i32)));
989 Values.push_back(Store->getValue());
992 for (unsigned i = 0; i < Values.size(); ++i) {
993 SDValue PartPtr = DAG.getNode(ISD::ADD, DL, MVT::i32,
994 Ptr, DAG.getConstant(i, MVT::i32));
995 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
996 Chain, Values[i], PartPtr,
997 DAG.getTargetConstant(0, MVT::i32));
1002 //===----------------------------------------------------------------------===//
1003 // Custom DAG optimizations
1004 //===----------------------------------------------------------------------===//
1006 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
1007 DAGCombinerInfo &DCI) {
1008 EVT VT = N->getValueType(0);
1009 EVT ScalarVT = VT.getScalarType();
1010 if (ScalarVT != MVT::f32)
1013 SelectionDAG &DAG = DCI.DAG;
1016 SDValue Src = N->getOperand(0);
1017 EVT SrcVT = Src.getValueType();
1019 // TODO: We could try to match extracting the higher bytes, which would be
1020 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
1021 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
1022 // about in practice.
1023 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
1024 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
1025 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
1026 DCI.AddToWorklist(Cvt.getNode());
1031 // We are primarily trying to catch operations on illegal vector types
1032 // before they are expanded.
1033 // For scalars, we can use the more flexible method of checking masked bits
1034 // after legalization.
1035 if (!DCI.isBeforeLegalize() ||
1036 !SrcVT.isVector() ||
1037 SrcVT.getVectorElementType() != MVT::i8) {
1041 assert(DCI.isBeforeLegalize() && "Unexpected legal type");
1043 // Weird sized vectors are a pain to handle, but we know 3 is really the same
1045 unsigned NElts = SrcVT.getVectorNumElements();
1046 if (!SrcVT.isSimple() && NElts != 3)
1049 // Handle v4i8 -> v4f32 extload. Replace the v4i8 with a legal i32 load to
1050 // prevent a mess from expanding to v4i32 and repacking.
1051 if (ISD::isNormalLoad(Src.getNode()) && Src.hasOneUse()) {
1052 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT);
1053 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT);
1054 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f32, NElts);
1056 LoadSDNode *Load = cast<LoadSDNode>(Src);
1057 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT,
1061 Load->getMemOperand());
1063 // Make sure successors of the original load stay after it by updating
1064 // them to use the new Chain.
1065 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), NewLoad.getValue(1));
1067 SmallVector<SDValue, 4> Elts;
1068 if (RegVT.isVector())
1069 DAG.ExtractVectorElements(NewLoad, Elts);
1071 Elts.push_back(NewLoad);
1073 SmallVector<SDValue, 4> Ops;
1075 unsigned EltIdx = 0;
1076 for (SDValue Elt : Elts) {
1077 unsigned ComponentsInElt = std::min(4u, NElts - 4 * EltIdx);
1078 for (unsigned I = 0; I < ComponentsInElt; ++I) {
1079 unsigned Opc = AMDGPUISD::CVT_F32_UBYTE0 + I;
1080 SDValue Cvt = DAG.getNode(Opc, DL, MVT::f32, Elt);
1081 DCI.AddToWorklist(Cvt.getNode());
1088 assert(Ops.size() == NElts);
1090 return DAG.getNode(ISD::BUILD_VECTOR, DL, FloatVT, Ops);
1096 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
1097 DAGCombinerInfo &DCI) const {
1098 SelectionDAG &DAG = DCI.DAG;
1100 EVT VT = N->getValueType(0);
1102 switch (N->getOpcode()) {
1103 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1104 case ISD::SELECT_CC: {
1105 ConstantSDNode *True, *False;
1106 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
1107 if ((True = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1108 && (False = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1109 && True->isAllOnesValue()
1110 && False->isNullValue()
1112 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
1113 N->getOperand(1), N->getOperand(4));
1119 SDValue Arg0 = N->getOperand(0);
1120 SDValue Arg1 = N->getOperand(1);
1121 SDValue CC = N->getOperand(2);
1122 ConstantSDNode * C = nullptr;
1123 ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
1125 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
1127 && Arg0.getOpcode() == ISD::SIGN_EXTEND
1128 && Arg0.getOperand(0).getValueType() == MVT::i1
1129 && (C = dyn_cast<ConstantSDNode>(Arg1))
1131 && CCOp == ISD::SETNE) {
1132 return SimplifySetCC(VT, Arg0.getOperand(0),
1133 DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL);
1138 case AMDGPUISD::CVT_F32_UBYTE0:
1139 case AMDGPUISD::CVT_F32_UBYTE1:
1140 case AMDGPUISD::CVT_F32_UBYTE2:
1141 case AMDGPUISD::CVT_F32_UBYTE3: {
1142 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
1144 SDValue Src = N->getOperand(0);
1145 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
1147 APInt KnownZero, KnownOne;
1148 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1149 !DCI.isBeforeLegalizeOps());
1150 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1151 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
1152 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
1153 DCI.CommitTargetLoweringOpt(TLO);
1159 case ISD::UINT_TO_FP: {
1160 return performUCharToFloatCombine(N, DCI);
1164 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1167 /// \brief Test if RegClass is one of the VSrc classes
1168 static bool isVSrc(unsigned RegClass) {
1169 return AMDGPU::VSrc_32RegClassID == RegClass ||
1170 AMDGPU::VSrc_64RegClassID == RegClass;
1173 /// \brief Test if RegClass is one of the SSrc classes
1174 static bool isSSrc(unsigned RegClass) {
1175 return AMDGPU::SSrc_32RegClassID == RegClass ||
1176 AMDGPU::SSrc_64RegClassID == RegClass;
1179 /// \brief Analyze the possible immediate value Op
1181 /// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
1182 /// and the immediate value if it's a literal immediate
1183 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
1190 if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
1191 if (Node->getZExtValue() >> 32) {
1194 Imm.I = Node->getSExtValue();
1195 } else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
1196 if (N->getValueType(0) != MVT::f32)
1198 Imm.F = Node->getValueAPF().convertToFloat();
1200 return -1; // It isn't an immediate
1202 if ((Imm.I >= -16 && Imm.I <= 64) ||
1203 Imm.F == 0.5f || Imm.F == -0.5f ||
1204 Imm.F == 1.0f || Imm.F == -1.0f ||
1205 Imm.F == 2.0f || Imm.F == -2.0f ||
1206 Imm.F == 4.0f || Imm.F == -4.0f)
1207 return 0; // It's an inline immediate
1209 return Imm.I; // It's a literal immediate
1212 /// \brief Try to fold an immediate directly into an instruction
1213 bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
1214 bool &ScalarSlotUsed) const {
1216 MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
1217 const SIInstrInfo *TII =
1218 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1219 if (!Mov || !TII->isMov(Mov->getMachineOpcode()))
1222 const SDValue &Op = Mov->getOperand(0);
1223 int32_t Value = analyzeImmediate(Op.getNode());
1225 // Not an immediate at all
1228 } else if (Value == 0) {
1229 // Inline immediates can always be fold
1233 } else if (Value == Immediate) {
1234 // Already fold literal immediate
1238 } else if (!ScalarSlotUsed && !Immediate) {
1239 // Fold this literal immediate
1240 ScalarSlotUsed = true;
1250 const TargetRegisterClass *SITargetLowering::getRegClassForNode(
1251 SelectionDAG &DAG, const SDValue &Op) const {
1252 const SIInstrInfo *TII =
1253 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1254 const SIRegisterInfo &TRI = TII->getRegisterInfo();
1256 if (!Op->isMachineOpcode()) {
1257 switch(Op->getOpcode()) {
1258 case ISD::CopyFromReg: {
1259 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1260 unsigned Reg = cast<RegisterSDNode>(Op->getOperand(1))->getReg();
1261 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1262 return MRI.getRegClass(Reg);
1264 return TRI.getPhysRegClass(Reg);
1266 default: return nullptr;
1269 const MCInstrDesc &Desc = TII->get(Op->getMachineOpcode());
1270 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
1271 if (OpClassID != -1) {
1272 return TRI.getRegClass(OpClassID);
1274 switch(Op.getMachineOpcode()) {
1275 case AMDGPU::COPY_TO_REGCLASS:
1276 // Operand 1 is the register class id for COPY_TO_REGCLASS instructions.
1277 OpClassID = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1279 // If the COPY_TO_REGCLASS instruction is copying to a VSrc register
1280 // class, then the register class for the value could be either a
1281 // VReg or and SReg. In order to get a more accurate
1282 if (OpClassID == AMDGPU::VSrc_32RegClassID ||
1283 OpClassID == AMDGPU::VSrc_64RegClassID) {
1284 return getRegClassForNode(DAG, Op.getOperand(0));
1286 return TRI.getRegClass(OpClassID);
1287 case AMDGPU::EXTRACT_SUBREG: {
1288 int SubIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1289 const TargetRegisterClass *SuperClass =
1290 getRegClassForNode(DAG, Op.getOperand(0));
1291 return TRI.getSubClassWithSubReg(SuperClass, SubIdx);
1293 case AMDGPU::REG_SEQUENCE:
1294 // Operand 0 is the register class id for REG_SEQUENCE instructions.
1295 return TRI.getRegClass(
1296 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue());
1298 return getRegClassFor(Op.getSimpleValueType());
1302 /// \brief Does "Op" fit into register class "RegClass" ?
1303 bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
1304 unsigned RegClass) const {
1305 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1306 const TargetRegisterClass *RC = getRegClassForNode(DAG, Op);
1310 return TRI->getRegClass(RegClass)->hasSubClassEq(RC);
1313 /// \brief Make sure that we don't exeed the number of allowed scalars
1314 void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
1316 bool &ScalarSlotUsed) const {
1318 // First map the operands register class to a destination class
1319 if (RegClass == AMDGPU::VSrc_32RegClassID)
1320 RegClass = AMDGPU::VReg_32RegClassID;
1321 else if (RegClass == AMDGPU::VSrc_64RegClassID)
1322 RegClass = AMDGPU::VReg_64RegClassID;
1326 // Nothing to do if they fit naturally
1327 if (fitsRegClass(DAG, Operand, RegClass))
1330 // If the scalar slot isn't used yet use it now
1331 if (!ScalarSlotUsed) {
1332 ScalarSlotUsed = true;
1336 // This is a conservative aproach. It is possible that we can't determine the
1337 // correct register class and copy too often, but better safe than sorry.
1338 SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32);
1339 SDNode *Node = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, SDLoc(),
1340 Operand.getValueType(), Operand, RC);
1341 Operand = SDValue(Node, 0);
1344 /// \returns true if \p Node's operands are different from the SDValue list
1346 static bool isNodeChanged(const SDNode *Node, const std::vector<SDValue> &Ops) {
1347 for (unsigned i = 0, e = Node->getNumOperands(); i < e; ++i) {
1348 if (Ops[i].getNode() != Node->getOperand(i).getNode()) {
1355 /// \brief Try to fold the Nodes operands into the Node
1356 SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
1357 SelectionDAG &DAG) const {
1359 // Original encoding (either e32 or e64)
1360 int Opcode = Node->getMachineOpcode();
1361 const SIInstrInfo *TII =
1362 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1363 const MCInstrDesc *Desc = &TII->get(Opcode);
1365 unsigned NumDefs = Desc->getNumDefs();
1366 unsigned NumOps = Desc->getNumOperands();
1368 // Commuted opcode if available
1369 int OpcodeRev = Desc->isCommutable() ? TII->commuteOpcode(Opcode) : -1;
1370 const MCInstrDesc *DescRev = OpcodeRev == -1 ? nullptr : &TII->get(OpcodeRev);
1372 assert(!DescRev || DescRev->getNumDefs() == NumDefs);
1373 assert(!DescRev || DescRev->getNumOperands() == NumOps);
1375 // e64 version if available, -1 otherwise
1376 int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
1377 const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? nullptr : &TII->get(OpcodeE64);
1378 int InputModifiers[3] = {0};
1380 assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
1382 int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
1383 bool HaveVSrc = false, HaveSSrc = false;
1385 // First figure out what we already have in this instruction.
1386 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1387 i != e && Op < NumOps; ++i, ++Op) {
1389 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1390 if (isVSrc(RegClass))
1392 else if (isSSrc(RegClass))
1397 int32_t Imm = analyzeImmediate(Node->getOperand(i).getNode());
1398 if (Imm != -1 && Imm != 0) {
1399 // Literal immediate
1404 // If we neither have VSrc nor SSrc, it makes no sense to continue.
1405 if (!HaveVSrc && !HaveSSrc)
1408 // No scalar allowed when we have both VSrc and SSrc
1409 bool ScalarSlotUsed = HaveVSrc && HaveSSrc;
1411 // Second go over the operands and try to fold them
1412 std::vector<SDValue> Ops;
1413 bool Promote2e64 = false;
1414 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1415 i != e && Op < NumOps; ++i, ++Op) {
1417 const SDValue &Operand = Node->getOperand(i);
1418 Ops.push_back(Operand);
1420 // Already folded immediate?
1421 if (isa<ConstantSDNode>(Operand.getNode()) ||
1422 isa<ConstantFPSDNode>(Operand.getNode()))
1425 // Is this a VSrc or SSrc operand?
1426 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1427 if (isVSrc(RegClass) || isSSrc(RegClass)) {
1428 // Try to fold the immediates
1429 if (!foldImm(Ops[i], Immediate, ScalarSlotUsed)) {
1430 // Folding didn't work, make sure we don't hit the SReg limit.
1431 ensureSRegLimit(DAG, Ops[i], RegClass, ScalarSlotUsed);
1436 if (i == 1 && DescRev && fitsRegClass(DAG, Ops[0], RegClass)) {
1438 unsigned OtherRegClass = Desc->OpInfo[NumDefs].RegClass;
1439 assert(isVSrc(OtherRegClass) || isSSrc(OtherRegClass));
1441 // Test if it makes sense to swap operands
1442 if (foldImm(Ops[1], Immediate, ScalarSlotUsed) ||
1443 (!fitsRegClass(DAG, Ops[1], RegClass) &&
1444 fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1446 // Swap commutable operands
1447 std::swap(Ops[0], Ops[1]);
1459 // Test if it makes sense to switch to e64 encoding
1460 unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass;
1461 if (!isVSrc(OtherRegClass) && !isSSrc(OtherRegClass))
1464 int32_t TmpImm = -1;
1465 if (foldImm(Ops[i], TmpImm, ScalarSlotUsed) ||
1466 (!fitsRegClass(DAG, Ops[i], RegClass) &&
1467 fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1469 // Switch to e64 encoding
1477 if (!DescE64 && !Promote2e64)
1479 if (!Operand.isMachineOpcode())
1481 if (Operand.getMachineOpcode() == AMDGPU::FNEG_SI) {
1483 Ops.push_back(Operand.getOperand(0));
1484 InputModifiers[i] = 1;
1491 else if (Operand.getMachineOpcode() == AMDGPU::FABS_SI) {
1493 Ops.push_back(Operand.getOperand(0));
1494 InputModifiers[i] = 2;
1504 std::vector<SDValue> OldOps(Ops);
1506 for (unsigned i = 0; i < OldOps.size(); ++i) {
1508 Ops.push_back(DAG.getTargetConstant(InputModifiers[i], MVT::i32));
1509 Ops.push_back(OldOps[i]);
1511 // Add the modifier flags while promoting
1512 for (unsigned i = 0; i < 2; ++i)
1513 Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
1516 // Add optional chain and glue
1517 for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
1518 Ops.push_back(Node->getOperand(i));
1520 // Nodes that have a glue result are not CSE'd by getMachineNode(), so in
1521 // this case a brand new node is always be created, even if the operands
1522 // are the same as before. So, manually check if anything has been changed.
1523 if (Desc->Opcode == Opcode && !isNodeChanged(Node, Ops)) {
1527 // Create a complete new instruction
1528 return DAG.getMachineNode(Desc->Opcode, SDLoc(Node), Node->getVTList(), Ops);
1531 /// \brief Helper function for adjustWritemask
1532 static unsigned SubIdx2Lane(unsigned Idx) {
1535 case AMDGPU::sub0: return 0;
1536 case AMDGPU::sub1: return 1;
1537 case AMDGPU::sub2: return 2;
1538 case AMDGPU::sub3: return 3;
1542 /// \brief Adjust the writemask of MIMG instructions
1543 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
1544 SelectionDAG &DAG) const {
1545 SDNode *Users[4] = { };
1547 unsigned OldDmask = Node->getConstantOperandVal(0);
1548 unsigned NewDmask = 0;
1550 // Try to figure out the used register components
1551 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
1554 // Abort if we can't understand the usage
1555 if (!I->isMachineOpcode() ||
1556 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
1559 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
1560 // Note that subregs are packed, i.e. Lane==0 is the first bit set
1561 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
1563 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
1565 // Set which texture component corresponds to the lane.
1567 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
1569 Comp = countTrailingZeros(Dmask);
1570 Dmask &= ~(1 << Comp);
1573 // Abort if we have more than one user per component
1578 NewDmask |= 1 << Comp;
1581 // Abort if there's no change
1582 if (NewDmask == OldDmask)
1585 // Adjust the writemask in the node
1586 std::vector<SDValue> Ops;
1587 Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32));
1588 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1589 Ops.push_back(Node->getOperand(i));
1590 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
1592 // If we only got one lane, replace it with a copy
1593 // (if NewDmask has only one bit set...)
1594 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
1595 SDValue RC = DAG.getTargetConstant(AMDGPU::VReg_32RegClassID, MVT::i32);
1596 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
1597 SDLoc(), Users[Lane]->getValueType(0),
1598 SDValue(Node, 0), RC);
1599 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
1603 // Update the users of the node with the new indices
1604 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
1606 SDNode *User = Users[i];
1610 SDValue Op = DAG.getTargetConstant(Idx, MVT::i32);
1611 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
1615 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
1616 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
1617 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
1622 /// \brief Fold the instructions after selecting them.
1623 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
1624 SelectionDAG &DAG) const {
1625 const SIInstrInfo *TII =
1626 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1627 Node = AdjustRegClass(Node, DAG);
1629 if (TII->isMIMG(Node->getMachineOpcode()))
1630 adjustWritemask(Node, DAG);
1632 return foldOperands(Node, DAG);
1635 /// \brief Assign the register class depending on the number of
1636 /// bits set in the writemask
1637 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
1638 SDNode *Node) const {
1639 const SIInstrInfo *TII =
1640 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1641 if (!TII->isMIMG(MI->getOpcode()))
1644 unsigned VReg = MI->getOperand(0).getReg();
1645 unsigned Writemask = MI->getOperand(1).getImm();
1646 unsigned BitsSet = 0;
1647 for (unsigned i = 0; i < 4; ++i)
1648 BitsSet += Writemask & (1 << i) ? 1 : 0;
1650 const TargetRegisterClass *RC;
1653 case 1: RC = &AMDGPU::VReg_32RegClass; break;
1654 case 2: RC = &AMDGPU::VReg_64RegClass; break;
1655 case 3: RC = &AMDGPU::VReg_96RegClass; break;
1658 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
1659 MI->setDesc(TII->get(NewOpcode));
1660 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1661 MRI.setRegClass(VReg, RC);
1664 MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N,
1665 SelectionDAG &DAG) const {
1668 unsigned NewOpcode = N->getMachineOpcode();
1670 switch (N->getMachineOpcode()) {
1672 case AMDGPU::S_LOAD_DWORD_IMM:
1673 NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1675 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1676 if (NewOpcode == N->getMachineOpcode()) {
1677 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1680 case AMDGPU::S_LOAD_DWORDX4_IMM:
1681 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1682 if (NewOpcode == N->getMachineOpcode()) {
1683 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1685 if (fitsRegClass(DAG, N->getOperand(0), AMDGPU::SReg_64RegClassID)) {
1688 ConstantSDNode *Offset = cast<ConstantSDNode>(N->getOperand(1));
1690 SDValue(DAG.getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::i128,
1691 DAG.getConstant(0, MVT::i64)), 0),
1693 DAG.getConstant(Offset->getSExtValue() << 2, MVT::i32)
1695 return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops);
1700 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
1701 const TargetRegisterClass *RC,
1702 unsigned Reg, EVT VT) const {
1703 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
1705 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
1706 cast<RegisterSDNode>(VReg)->getReg(), VT);