1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for SI
13 //===----------------------------------------------------------------------===//
17 #define _USE_MATH_DEFINES
21 #include "SIISelLowering.h"
23 #include "AMDGPUIntrinsicInfo.h"
24 #include "AMDGPUSubtarget.h"
25 #include "SIInstrInfo.h"
26 #include "SIMachineFunctionInfo.h"
27 #include "SIRegisterInfo.h"
28 #include "llvm/ADT/BitVector.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/ADT/SmallString.h"
38 SITargetLowering::SITargetLowering(TargetMachine &TM,
39 const AMDGPUSubtarget &STI)
40 : AMDGPUTargetLowering(TM, STI) {
41 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
42 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
44 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
45 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
47 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
48 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
50 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
51 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
52 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
54 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
55 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
57 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
58 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
60 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
61 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
63 computeRegisterProperties();
65 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
66 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
67 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
68 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
70 setOperationAction(ISD::ADD, MVT::i32, Legal);
71 setOperationAction(ISD::ADDC, MVT::i32, Legal);
72 setOperationAction(ISD::ADDE, MVT::i32, Legal);
73 setOperationAction(ISD::SUBC, MVT::i32, Legal);
74 setOperationAction(ISD::SUBE, MVT::i32, Legal);
76 setOperationAction(ISD::FSIN, MVT::f32, Custom);
77 setOperationAction(ISD::FCOS, MVT::f32, Custom);
79 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
80 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
81 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
82 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
84 // We need to custom lower vector stores from local memory
85 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
86 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
87 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
89 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
90 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
92 setOperationAction(ISD::STORE, MVT::i1, Custom);
93 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
95 setOperationAction(ISD::SELECT, MVT::i64, Custom);
96 setOperationAction(ISD::SELECT, MVT::f64, Promote);
97 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
99 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
100 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
101 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
102 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
104 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
105 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
107 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
111 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
114 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
124 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
125 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
126 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
127 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
129 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
130 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
132 for (MVT VT : MVT::integer_valuetypes()) {
136 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
137 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal);
138 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal);
139 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
141 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
142 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
143 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
144 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
146 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
147 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal);
148 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal);
149 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
152 for (MVT VT : MVT::integer_vector_valuetypes()) {
153 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i16, Expand);
154 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v16i16, Expand);
157 for (MVT VT : MVT::fp_valuetypes())
158 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
160 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
161 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
162 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
163 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
165 setOperationAction(ISD::LOAD, MVT::i1, Custom);
167 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
168 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
169 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
171 // These should use UDIVREM, so set them to expand
172 setOperationAction(ISD::UDIV, MVT::i64, Expand);
173 setOperationAction(ISD::UREM, MVT::i64, Expand);
175 // We only support LOAD/STORE and vector manipulation ops for vectors
176 // with > 4 elements.
178 MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32
181 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
182 setOperationAction(ISD::SELECT, MVT::i1, Promote);
184 for (MVT VT : VecTypes) {
185 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
189 case ISD::BUILD_VECTOR:
191 case ISD::EXTRACT_VECTOR_ELT:
192 case ISD::INSERT_VECTOR_ELT:
193 case ISD::INSERT_SUBVECTOR:
194 case ISD::EXTRACT_SUBVECTOR:
196 case ISD::CONCAT_VECTORS:
197 setOperationAction(Op, VT, Custom);
200 setOperationAction(Op, VT, Expand);
206 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
207 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
208 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
209 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
210 setOperationAction(ISD::FRINT, MVT::f64, Legal);
213 setOperationAction(ISD::FDIV, MVT::f32, Custom);
214 setOperationAction(ISD::FDIV, MVT::f64, Custom);
216 setTargetDAGCombine(ISD::FADD);
217 setTargetDAGCombine(ISD::FSUB);
218 setTargetDAGCombine(ISD::FMINNUM);
219 setTargetDAGCombine(ISD::FMAXNUM);
220 setTargetDAGCombine(ISD::SELECT_CC);
221 setTargetDAGCombine(ISD::SETCC);
222 setTargetDAGCombine(ISD::AND);
223 setTargetDAGCombine(ISD::OR);
224 setTargetDAGCombine(ISD::UINT_TO_FP);
226 // All memory operations. Some folding on the pointer operand is done to help
227 // matching the constant offsets in the addressing modes.
228 setTargetDAGCombine(ISD::LOAD);
229 setTargetDAGCombine(ISD::STORE);
230 setTargetDAGCombine(ISD::ATOMIC_LOAD);
231 setTargetDAGCombine(ISD::ATOMIC_STORE);
232 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
233 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
234 setTargetDAGCombine(ISD::ATOMIC_SWAP);
235 setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
236 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
237 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
238 setTargetDAGCombine(ISD::ATOMIC_LOAD_OR);
239 setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
240 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND);
241 setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN);
242 setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX);
243 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN);
244 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX);
246 setSchedulingPreference(Sched::RegPressure);
249 //===----------------------------------------------------------------------===//
250 // TargetLowering queries
251 //===----------------------------------------------------------------------===//
253 bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,
255 // SI has some legal vector types, but no legal vector operations. Say no
256 // shuffles are legal in order to prefer scalarizing some vector operations.
260 // FIXME: This really needs an address space argument. The immediate offset
261 // size is different for different sets of memory instruction sets.
263 // The single offset DS instructions have a 16-bit unsigned byte offset.
265 // MUBUF / MTBUF have a 12-bit unsigned byte offset, and additionally can do r +
266 // r + i with addr64. 32-bit has more addressing mode options. Depending on the
267 // resource constant, it can also do (i64 r0) + (i32 r1) * (i14 i).
269 // SMRD instructions have an 8-bit, dword offset.
271 bool SITargetLowering::isLegalAddressingMode(const AddrMode &AM,
273 // No global is ever allowed as a base.
277 // Allow a 16-bit unsigned immediate field, since this is what DS instructions
279 if (!isUInt<16>(AM.BaseOffs))
284 case 0: // "r+i" or just "i", depending on HasBaseReg.
287 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
289 // Otherwise we have r+r or r+i.
292 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
296 default: // Don't allow n * r
303 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
306 bool *IsFast) const {
310 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
311 // which isn't a simple VT.
312 if (!VT.isSimple() || VT == MVT::Other)
315 // TODO - CI+ supports unaligned memory accesses, but this requires driver
318 // XXX - The only mention I see of this in the ISA manual is for LDS direct
319 // reads the "byte address and must be dword aligned". Is it also true for the
320 // normal loads and stores?
321 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS) {
322 // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
323 // aligned, 8 byte access in a single operation using ds_read2/write2_b32
324 // with adjacent offsets.
325 return Align % 4 == 0;
328 // Smaller than dword value must be aligned.
329 // FIXME: This should be allowed on CI+
330 if (VT.bitsLT(MVT::i32))
333 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
334 // byte-address are ignored, thus forcing Dword alignment.
335 // This applies to private, global, and constant memory.
339 return VT.bitsGT(MVT::i32) && Align % 4 == 0;
342 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
343 unsigned SrcAlign, bool IsMemset,
346 MachineFunction &MF) const {
347 // FIXME: Should account for address space here.
349 // The default fallback uses the private pointer size as a guess for a type to
350 // use. Make sure we switch these to 64-bit accesses.
352 if (Size >= 16 && DstAlign >= 4) // XXX: Should only do for global
355 if (Size >= 8 && DstAlign >= 4)
362 TargetLoweringBase::LegalizeTypeAction
363 SITargetLowering::getPreferredVectorAction(EVT VT) const {
364 if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
365 return TypeSplitVector;
367 return TargetLoweringBase::getPreferredVectorAction(VT);
370 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
372 const SIInstrInfo *TII =
373 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
374 return TII->isInlineConstant(Imm);
377 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
378 SDLoc SL, SDValue Chain,
379 unsigned Offset, bool Signed) const {
380 const DataLayout *DL = getDataLayout();
381 MachineFunction &MF = DAG.getMachineFunction();
382 const SIRegisterInfo *TRI =
383 static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
384 unsigned InputPtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR);
386 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
388 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
389 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
390 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
391 MRI.getLiveInVirtReg(InputPtrReg), MVT::i64);
392 SDValue Ptr = DAG.getNode(ISD::ADD, SL, MVT::i64, BasePtr,
393 DAG.getConstant(Offset, MVT::i64));
394 SDValue PtrOffset = DAG.getUNDEF(getPointerTy(AMDGPUAS::CONSTANT_ADDRESS));
395 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
397 return DAG.getLoad(ISD::UNINDEXED, Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD,
398 VT, SL, Chain, Ptr, PtrOffset, PtrInfo, MemVT,
400 true, // isNonTemporal
402 DL->getABITypeAlignment(Ty)); // Alignment
405 SDValue SITargetLowering::LowerFormalArguments(
406 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
407 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
408 SmallVectorImpl<SDValue> &InVals) const {
409 const SIRegisterInfo *TRI =
410 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
412 MachineFunction &MF = DAG.getMachineFunction();
413 FunctionType *FType = MF.getFunction()->getFunctionType();
414 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
416 assert(CallConv == CallingConv::C);
418 SmallVector<ISD::InputArg, 16> Splits;
419 BitVector Skipped(Ins.size());
421 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
422 const ISD::InputArg &Arg = Ins[i];
424 // First check if it's a PS input addr
425 if (Info->getShaderType() == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
426 !Arg.Flags.isByVal()) {
428 assert((PSInputNum <= 15) && "Too many PS inputs!");
431 // We can savely skip PS inputs
437 Info->PSInputAddr |= 1 << PSInputNum++;
440 // Second split vertices into their elements
441 if (Info->getShaderType() != ShaderType::COMPUTE && Arg.VT.isVector()) {
442 ISD::InputArg NewArg = Arg;
443 NewArg.Flags.setSplit();
444 NewArg.VT = Arg.VT.getVectorElementType();
446 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
447 // three or five element vertex only needs three or five registers,
448 // NOT four or eigth.
449 Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
450 unsigned NumElements = ParamType->getVectorNumElements();
452 for (unsigned j = 0; j != NumElements; ++j) {
453 Splits.push_back(NewArg);
454 NewArg.PartOffset += NewArg.VT.getStoreSize();
457 } else if (Info->getShaderType() != ShaderType::COMPUTE) {
458 Splits.push_back(Arg);
462 SmallVector<CCValAssign, 16> ArgLocs;
463 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
466 // At least one interpolation mode must be enabled or else the GPU will hang.
467 if (Info->getShaderType() == ShaderType::PIXEL &&
468 (Info->PSInputAddr & 0x7F) == 0) {
469 Info->PSInputAddr |= 1;
470 CCInfo.AllocateReg(AMDGPU::VGPR0);
471 CCInfo.AllocateReg(AMDGPU::VGPR1);
474 // The pointer to the list of arguments is stored in SGPR0, SGPR1
475 // The pointer to the scratch buffer is stored in SGPR2, SGPR3
476 if (Info->getShaderType() == ShaderType::COMPUTE) {
477 if (Subtarget->isAmdHsaOS())
478 Info->NumUserSGPRs = 2; // FIXME: Need to support scratch buffers.
480 Info->NumUserSGPRs = 4;
482 unsigned InputPtrReg =
483 TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR);
484 unsigned InputPtrRegLo =
485 TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 0);
486 unsigned InputPtrRegHi =
487 TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 1);
489 unsigned ScratchPtrReg =
490 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR);
491 unsigned ScratchPtrRegLo =
492 TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 0);
493 unsigned ScratchPtrRegHi =
494 TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 1);
496 CCInfo.AllocateReg(InputPtrRegLo);
497 CCInfo.AllocateReg(InputPtrRegHi);
498 CCInfo.AllocateReg(ScratchPtrRegLo);
499 CCInfo.AllocateReg(ScratchPtrRegHi);
500 MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass);
501 MF.addLiveIn(ScratchPtrReg, &AMDGPU::SReg_64RegClass);
504 if (Info->getShaderType() == ShaderType::COMPUTE) {
505 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
509 AnalyzeFormalArguments(CCInfo, Splits);
511 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
513 const ISD::InputArg &Arg = Ins[i];
515 InVals.push_back(DAG.getUNDEF(Arg.VT));
519 CCValAssign &VA = ArgLocs[ArgIdx++];
520 MVT VT = VA.getLocVT();
524 EVT MemVT = Splits[i].VT;
525 const unsigned Offset = 36 + VA.getLocMemOffset();
526 // The first 36 bytes of the input buffer contains information about
527 // thread group and global sizes.
528 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, DAG.getRoot(),
529 Offset, Ins[i].Flags.isSExt());
531 const PointerType *ParamTy =
532 dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
533 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
534 ParamTy && ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
535 // On SI local pointers are just offsets into LDS, so they are always
536 // less than 16-bits. On CI and newer they could potentially be
537 // real pointers, so we can't guarantee their size.
538 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
539 DAG.getValueType(MVT::i16));
542 InVals.push_back(Arg);
543 Info->ABIArgOffset = Offset + MemVT.getStoreSize();
546 assert(VA.isRegLoc() && "Parameter must be in a register!");
548 unsigned Reg = VA.getLocReg();
550 if (VT == MVT::i64) {
551 // For now assume it is a pointer
552 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
553 &AMDGPU::SReg_64RegClass);
554 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
555 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
559 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
561 Reg = MF.addLiveIn(Reg, RC);
562 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
564 if (Arg.VT.isVector()) {
566 // Build a vector from the registers
567 Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
568 unsigned NumElements = ParamType->getVectorNumElements();
570 SmallVector<SDValue, 4> Regs;
572 for (unsigned j = 1; j != NumElements; ++j) {
573 Reg = ArgLocs[ArgIdx++].getLocReg();
574 Reg = MF.addLiveIn(Reg, RC);
575 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
578 // Fill up the missing vector elements
579 NumElements = Arg.VT.getVectorNumElements() - NumElements;
580 Regs.append(NumElements, DAG.getUNDEF(VT));
582 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
586 InVals.push_back(Val);
589 if (Info->getShaderType() != ShaderType::COMPUTE) {
590 unsigned ScratchIdx = CCInfo.getFirstUnallocated(ArrayRef<MCPhysReg>(
591 AMDGPU::SGPR_32RegClass.begin(), AMDGPU::SGPR_32RegClass.getNumRegs()));
592 Info->ScratchOffsetReg = AMDGPU::SGPR_32RegClass.getRegister(ScratchIdx);
597 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
598 MachineInstr * MI, MachineBasicBlock * BB) const {
600 MachineBasicBlock::iterator I = *MI;
601 const SIInstrInfo *TII =
602 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
604 switch (MI->getOpcode()) {
606 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
609 case AMDGPU::SI_RegisterStorePseudo: {
610 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
611 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
612 MachineInstrBuilder MIB =
613 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
615 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
616 MIB.addOperand(MI->getOperand(i));
618 MI->eraseFromParent();
625 bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
626 // This currently forces unfolding various combinations of fsub into fma with
627 // free fneg'd operands. As long as we have fast FMA (controlled by
628 // isFMAFasterThanFMulAndFAdd), we should perform these.
630 // When fma is quarter rate, for f64 where add / sub are at best half rate,
631 // most of these combines appear to be cycle neutral but save on instruction
632 // count / code size.
636 EVT SITargetLowering::getSetCCResultType(LLVMContext &Ctx, EVT VT) const {
637 if (!VT.isVector()) {
640 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
643 MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {
647 // Answering this is somewhat tricky and depends on the specific device which
648 // have different rates for fma or all f64 operations.
650 // v_fma_f64 and v_mul_f64 always take the same number of cycles as each other
651 // regardless of which device (although the number of cycles differs between
652 // devices), so it is always profitable for f64.
654 // v_fma_f32 takes 4 or 16 cycles depending on the device, so it is profitable
655 // only on full rate devices. Normally, we should prefer selecting v_mad_f32
656 // which we can always do even without fused FP ops since it returns the same
657 // result as the separate operations and since it is always full
658 // rate. Therefore, we lie and report that it is not faster for f32. v_mad_f32
659 // however does not support denormals, so we do report fma as faster if we have
660 // a fast fma device and require denormals.
662 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
663 VT = VT.getScalarType();
668 switch (VT.getSimpleVT().SimpleTy) {
670 // This is as fast on some subtargets. However, we always have full rate f32
671 // mad available which returns the same result as the separate operations
672 // which we should prefer over fma. We can't use this if we want to support
673 // denormals, so only report this in these cases.
674 return Subtarget->hasFP32Denormals() && Subtarget->hasFastFMAF32();
684 //===----------------------------------------------------------------------===//
685 // Custom DAG Lowering Operations
686 //===----------------------------------------------------------------------===//
688 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
689 switch (Op.getOpcode()) {
690 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
691 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
692 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
694 SDValue Result = LowerLOAD(Op, DAG);
695 assert((!Result.getNode() ||
696 Result.getNode()->getNumValues() == 2) &&
697 "Load should return a value and a chain");
703 return LowerTrig(Op, DAG);
704 case ISD::SELECT: return LowerSELECT(Op, DAG);
705 case ISD::FDIV: return LowerFDIV(Op, DAG);
706 case ISD::STORE: return LowerSTORE(Op, DAG);
707 case ISD::GlobalAddress: {
708 MachineFunction &MF = DAG.getMachineFunction();
709 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
710 return LowerGlobalAddress(MFI, Op, DAG);
712 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
713 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
718 /// \brief Helper function for LowerBRCOND
719 static SDNode *findUser(SDValue Value, unsigned Opcode) {
721 SDNode *Parent = Value.getNode();
722 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
725 if (I.getUse().get() != Value)
728 if (I->getOpcode() == Opcode)
734 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
736 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Op);
737 unsigned FrameIndex = FINode->getIndex();
739 return DAG.getTargetFrameIndex(FrameIndex, MVT::i32);
742 /// This transforms the control flow intrinsics to get the branch destination as
743 /// last parameter, also switches branch target with BR if the need arise
744 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
745 SelectionDAG &DAG) const {
749 SDNode *Intr = BRCOND.getOperand(1).getNode();
750 SDValue Target = BRCOND.getOperand(2);
751 SDNode *BR = nullptr;
753 if (Intr->getOpcode() == ISD::SETCC) {
754 // As long as we negate the condition everything is fine
755 SDNode *SetCC = Intr;
756 assert(SetCC->getConstantOperandVal(1) == 1);
757 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
759 Intr = SetCC->getOperand(0).getNode();
762 // Get the target from BR if we don't negate the condition
763 BR = findUser(BRCOND, ISD::BR);
764 Target = BR->getOperand(1);
767 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
769 // Build the result and
770 ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());
772 // operands of the new intrinsic call
773 SmallVector<SDValue, 4> Ops;
774 Ops.push_back(BRCOND.getOperand(0));
775 Ops.append(Intr->op_begin() + 1, Intr->op_end());
776 Ops.push_back(Target);
778 // build the new intrinsic call
779 SDNode *Result = DAG.getNode(
780 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
781 DAG.getVTList(Res), Ops).getNode();
784 // Give the branch instruction our target
789 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
790 DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
791 BR = NewBR.getNode();
794 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
796 // Copy the intrinsic results to registers
797 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
798 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
802 Chain = DAG.getCopyToReg(
804 CopyToReg->getOperand(1),
805 SDValue(Result, i - 1),
808 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
811 // Remove the old intrinsic from the chain
812 DAG.ReplaceAllUsesOfValueWith(
813 SDValue(Intr, Intr->getNumValues() - 1),
814 Intr->getOperand(0));
819 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
821 SelectionDAG &DAG) const {
822 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
824 if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
825 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
828 const GlobalValue *GV = GSD->getGlobal();
829 MVT PtrVT = getPointerTy(GSD->getAddressSpace());
831 SDValue Ptr = DAG.getNode(AMDGPUISD::CONST_DATA_PTR, DL, PtrVT);
832 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
834 SDValue PtrLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
835 DAG.getConstant(0, MVT::i32));
836 SDValue PtrHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
837 DAG.getConstant(1, MVT::i32));
839 SDValue Lo = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i32, MVT::Glue),
841 SDValue Hi = DAG.getNode(ISD::ADDE, DL, DAG.getVTList(MVT::i32, MVT::Glue),
842 PtrHi, DAG.getConstant(0, MVT::i32),
843 SDValue(Lo.getNode(), 1));
844 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
847 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
848 SelectionDAG &DAG) const {
849 MachineFunction &MF = DAG.getMachineFunction();
850 const SIRegisterInfo *TRI =
851 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
853 EVT VT = Op.getValueType();
855 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
857 switch (IntrinsicID) {
858 case Intrinsic::r600_read_ngroups_x:
859 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
860 SI::KernelInputOffsets::NGROUPS_X, false);
861 case Intrinsic::r600_read_ngroups_y:
862 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
863 SI::KernelInputOffsets::NGROUPS_Y, false);
864 case Intrinsic::r600_read_ngroups_z:
865 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
866 SI::KernelInputOffsets::NGROUPS_Z, false);
867 case Intrinsic::r600_read_global_size_x:
868 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
869 SI::KernelInputOffsets::GLOBAL_SIZE_X, false);
870 case Intrinsic::r600_read_global_size_y:
871 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
872 SI::KernelInputOffsets::GLOBAL_SIZE_Y, false);
873 case Intrinsic::r600_read_global_size_z:
874 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
875 SI::KernelInputOffsets::GLOBAL_SIZE_Z, false);
876 case Intrinsic::r600_read_local_size_x:
877 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
878 SI::KernelInputOffsets::LOCAL_SIZE_X, false);
879 case Intrinsic::r600_read_local_size_y:
880 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
881 SI::KernelInputOffsets::LOCAL_SIZE_Y, false);
882 case Intrinsic::r600_read_local_size_z:
883 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
884 SI::KernelInputOffsets::LOCAL_SIZE_Z, false);
886 case Intrinsic::AMDGPU_read_workdim:
887 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
888 MF.getInfo<SIMachineFunctionInfo>()->ABIArgOffset,
891 case Intrinsic::r600_read_tgid_x:
892 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
893 TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_X), VT);
894 case Intrinsic::r600_read_tgid_y:
895 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
896 TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_Y), VT);
897 case Intrinsic::r600_read_tgid_z:
898 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
899 TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_Z), VT);
900 case Intrinsic::r600_read_tidig_x:
901 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
902 TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_X), VT);
903 case Intrinsic::r600_read_tidig_y:
904 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
905 TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_Y), VT);
906 case Intrinsic::r600_read_tidig_z:
907 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
908 TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_Z), VT);
909 case AMDGPUIntrinsic::SI_load_const: {
915 MachineMemOperand *MMO = MF.getMachineMemOperand(
916 MachinePointerInfo(),
917 MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
918 VT.getStoreSize(), 4);
919 return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
920 Op->getVTList(), Ops, VT, MMO);
922 case AMDGPUIntrinsic::SI_sample:
923 return LowerSampleIntrinsic(AMDGPUISD::SAMPLE, Op, DAG);
924 case AMDGPUIntrinsic::SI_sampleb:
925 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEB, Op, DAG);
926 case AMDGPUIntrinsic::SI_sampled:
927 return LowerSampleIntrinsic(AMDGPUISD::SAMPLED, Op, DAG);
928 case AMDGPUIntrinsic::SI_samplel:
929 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEL, Op, DAG);
930 case AMDGPUIntrinsic::SI_vs_load_input:
931 return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
936 return AMDGPUTargetLowering::LowerOperation(Op, DAG);
940 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
941 SelectionDAG &DAG) const {
942 MachineFunction &MF = DAG.getMachineFunction();
943 SDValue Chain = Op.getOperand(0);
944 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
946 switch (IntrinsicID) {
947 case AMDGPUIntrinsic::SI_tbuffer_store: {
966 EVT VT = Op.getOperand(3).getValueType();
968 MachineMemOperand *MMO = MF.getMachineMemOperand(
969 MachinePointerInfo(),
970 MachineMemOperand::MOStore,
971 VT.getStoreSize(), 4);
972 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
973 Op->getVTList(), Ops, VT, MMO);
980 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
982 LoadSDNode *Load = cast<LoadSDNode>(Op);
984 if (Op.getValueType().isVector()) {
985 assert(Op.getValueType().getVectorElementType() == MVT::i32 &&
986 "Custom lowering for non-i32 vectors hasn't been implemented.");
987 unsigned NumElements = Op.getValueType().getVectorNumElements();
988 assert(NumElements != 2 && "v2 loads are supported for all address spaces.");
989 switch (Load->getAddressSpace()) {
991 case AMDGPUAS::GLOBAL_ADDRESS:
992 case AMDGPUAS::PRIVATE_ADDRESS:
993 // v4 loads are supported for private and global memory.
994 if (NumElements <= 4)
997 case AMDGPUAS::LOCAL_ADDRESS:
998 return ScalarizeVectorLoad(Op, DAG);
1002 return AMDGPUTargetLowering::LowerLOAD(Op, DAG);
1005 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
1007 SelectionDAG &DAG) const {
1008 return DAG.getNode(Opcode, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
1014 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
1015 if (Op.getValueType() != MVT::i64)
1019 SDValue Cond = Op.getOperand(0);
1021 SDValue Zero = DAG.getConstant(0, MVT::i32);
1022 SDValue One = DAG.getConstant(1, MVT::i32);
1024 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
1025 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
1027 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
1028 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
1030 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
1032 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
1033 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
1035 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
1037 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
1038 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
1041 // Catch division cases where we can use shortcuts with rcp and rsq
1043 SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
1045 SDValue LHS = Op.getOperand(0);
1046 SDValue RHS = Op.getOperand(1);
1047 EVT VT = Op.getValueType();
1048 bool Unsafe = DAG.getTarget().Options.UnsafeFPMath;
1050 if (const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(LHS)) {
1051 if ((Unsafe || (VT == MVT::f32 && !Subtarget->hasFP32Denormals())) &&
1052 CLHS->isExactlyValue(1.0)) {
1053 // v_rcp_f32 and v_rsq_f32 do not support denormals, and according to
1054 // the CI documentation has a worst case error of 1 ulp.
1055 // OpenCL requires <= 2.5 ulp for 1.0 / x, so it should always be OK to
1056 // use it as long as we aren't trying to use denormals.
1058 // 1.0 / sqrt(x) -> rsq(x)
1060 // XXX - Is UnsafeFPMath sufficient to do this for f64? The maximum ULP
1061 // error seems really high at 2^29 ULP.
1062 if (RHS.getOpcode() == ISD::FSQRT)
1063 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0));
1065 // 1.0 / x -> rcp(x)
1066 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1071 // Turn into multiply by the reciprocal.
1072 // x / y -> x * (1.0 / y)
1073 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1074 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip);
1080 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
1081 SDValue FastLowered = LowerFastFDIV(Op, DAG);
1082 if (FastLowered.getNode())
1085 // This uses v_rcp_f32 which does not handle denormals. Let this hit a
1086 // selection error for now rather than do something incorrect.
1087 if (Subtarget->hasFP32Denormals())
1091 SDValue LHS = Op.getOperand(0);
1092 SDValue RHS = Op.getOperand(1);
1094 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
1096 const APFloat K0Val(BitsToFloat(0x6f800000));
1097 const SDValue K0 = DAG.getConstantFP(K0Val, MVT::f32);
1099 const APFloat K1Val(BitsToFloat(0x2f800000));
1100 const SDValue K1 = DAG.getConstantFP(K1Val, MVT::f32);
1102 const SDValue One = DAG.getConstantFP(1.0, MVT::f32);
1104 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f32);
1106 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
1108 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
1110 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
1112 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
1114 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
1116 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
1119 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
1120 if (DAG.getTarget().Options.UnsafeFPMath)
1121 return LowerFastFDIV(Op, DAG);
1124 SDValue X = Op.getOperand(0);
1125 SDValue Y = Op.getOperand(1);
1127 const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
1129 SDVTList ScaleVT = DAG.getVTList(MVT::f64, MVT::i1);
1131 SDValue DivScale0 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, Y, Y, X);
1133 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0);
1135 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0);
1137 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One);
1139 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp);
1141 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One);
1143 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X);
1145 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1);
1146 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3);
1148 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64,
1149 NegDivScale0, Mul, DivScale1);
1153 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
1154 // Workaround a hardware bug on SI where the condition output from div_scale
1157 const SDValue Hi = DAG.getConstant(1, MVT::i32);
1159 // Figure out if the scale to use for div_fmas.
1160 SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
1161 SDValue DenBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Y);
1162 SDValue Scale0BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale0);
1163 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1);
1165 SDValue NumHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, NumBC, Hi);
1166 SDValue DenHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, DenBC, Hi);
1169 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale0BC, Hi);
1171 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale1BC, Hi);
1173 SDValue CmpDen = DAG.getSetCC(SL, MVT::i1, DenHi, Scale0Hi, ISD::SETEQ);
1174 SDValue CmpNum = DAG.getSetCC(SL, MVT::i1, NumHi, Scale1Hi, ISD::SETEQ);
1175 Scale = DAG.getNode(ISD::XOR, SL, MVT::i1, CmpNum, CmpDen);
1177 Scale = DivScale1.getValue(1);
1180 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f64,
1181 Fma4, Fma3, Mul, Scale);
1183 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f64, Fmas, Y, X);
1186 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
1187 EVT VT = Op.getValueType();
1190 return LowerFDIV32(Op, DAG);
1193 return LowerFDIV64(Op, DAG);
1195 llvm_unreachable("Unexpected type for fdiv");
1198 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1200 StoreSDNode *Store = cast<StoreSDNode>(Op);
1201 EVT VT = Store->getMemoryVT();
1203 // These stores are legal.
1204 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
1205 if (VT.isVector() && VT.getVectorNumElements() > 4)
1206 return ScalarizeVectorStore(Op, DAG);
1210 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1214 if (VT.isVector() && VT.getVectorNumElements() >= 8)
1215 return ScalarizeVectorStore(Op, DAG);
1218 return DAG.getTruncStore(Store->getChain(), DL,
1219 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
1220 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
1225 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
1226 EVT VT = Op.getValueType();
1227 SDValue Arg = Op.getOperand(0);
1228 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
1229 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
1230 DAG.getConstantFP(0.5 / M_PI, VT)));
1232 switch (Op.getOpcode()) {
1234 return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, FractPart);
1236 return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, FractPart);
1238 llvm_unreachable("Wrong trig opcode");
1242 //===----------------------------------------------------------------------===//
1243 // Custom DAG optimizations
1244 //===----------------------------------------------------------------------===//
1246 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
1247 DAGCombinerInfo &DCI) const {
1248 EVT VT = N->getValueType(0);
1249 EVT ScalarVT = VT.getScalarType();
1250 if (ScalarVT != MVT::f32)
1253 SelectionDAG &DAG = DCI.DAG;
1256 SDValue Src = N->getOperand(0);
1257 EVT SrcVT = Src.getValueType();
1259 // TODO: We could try to match extracting the higher bytes, which would be
1260 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
1261 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
1262 // about in practice.
1263 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
1264 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
1265 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
1266 DCI.AddToWorklist(Cvt.getNode());
1271 // We are primarily trying to catch operations on illegal vector types
1272 // before they are expanded.
1273 // For scalars, we can use the more flexible method of checking masked bits
1274 // after legalization.
1275 if (!DCI.isBeforeLegalize() ||
1276 !SrcVT.isVector() ||
1277 SrcVT.getVectorElementType() != MVT::i8) {
1281 assert(DCI.isBeforeLegalize() && "Unexpected legal type");
1283 // Weird sized vectors are a pain to handle, but we know 3 is really the same
1285 unsigned NElts = SrcVT.getVectorNumElements();
1286 if (!SrcVT.isSimple() && NElts != 3)
1289 // Handle v4i8 -> v4f32 extload. Replace the v4i8 with a legal i32 load to
1290 // prevent a mess from expanding to v4i32 and repacking.
1291 if (ISD::isNormalLoad(Src.getNode()) && Src.hasOneUse()) {
1292 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT);
1293 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT);
1294 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f32, NElts);
1295 LoadSDNode *Load = cast<LoadSDNode>(Src);
1297 unsigned AS = Load->getAddressSpace();
1298 unsigned Align = Load->getAlignment();
1299 Type *Ty = LoadVT.getTypeForEVT(*DAG.getContext());
1300 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
1302 // Don't try to replace the load if we have to expand it due to alignment
1303 // problems. Otherwise we will end up scalarizing the load, and trying to
1304 // repack into the vector for no real reason.
1305 if (Align < ABIAlignment &&
1306 !allowsMisalignedMemoryAccesses(LoadVT, AS, Align, nullptr)) {
1310 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT,
1314 Load->getMemOperand());
1316 // Make sure successors of the original load stay after it by updating
1317 // them to use the new Chain.
1318 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), NewLoad.getValue(1));
1320 SmallVector<SDValue, 4> Elts;
1321 if (RegVT.isVector())
1322 DAG.ExtractVectorElements(NewLoad, Elts);
1324 Elts.push_back(NewLoad);
1326 SmallVector<SDValue, 4> Ops;
1328 unsigned EltIdx = 0;
1329 for (SDValue Elt : Elts) {
1330 unsigned ComponentsInElt = std::min(4u, NElts - 4 * EltIdx);
1331 for (unsigned I = 0; I < ComponentsInElt; ++I) {
1332 unsigned Opc = AMDGPUISD::CVT_F32_UBYTE0 + I;
1333 SDValue Cvt = DAG.getNode(Opc, DL, MVT::f32, Elt);
1334 DCI.AddToWorklist(Cvt.getNode());
1341 assert(Ops.size() == NElts);
1343 return DAG.getNode(ISD::BUILD_VECTOR, DL, FloatVT, Ops);
1349 // (shl (add x, c1), c2) -> add (shl x, c2), (shl c1, c2)
1351 // This is a variant of
1352 // (mul (add x, c1), c2) -> add (mul x, c2), (mul c1, c2),
1354 // The normal DAG combiner will do this, but only if the add has one use since
1355 // that would increase the number of instructions.
1357 // This prevents us from seeing a constant offset that can be folded into a
1358 // memory instruction's addressing mode. If we know the resulting add offset of
1359 // a pointer can be folded into an addressing offset, we can replace the pointer
1360 // operand with the add of new constant offset. This eliminates one of the uses,
1361 // and may allow the remaining use to also be simplified.
1363 SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
1365 DAGCombinerInfo &DCI) const {
1366 SDValue N0 = N->getOperand(0);
1367 SDValue N1 = N->getOperand(1);
1369 if (N0.getOpcode() != ISD::ADD)
1372 const ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(N1);
1376 const ConstantSDNode *CAdd = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1380 const SIInstrInfo *TII =
1381 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
1383 // If the resulting offset is too large, we can't fold it into the addressing
1385 APInt Offset = CAdd->getAPIntValue() << CN1->getAPIntValue();
1386 if (!TII->canFoldOffset(Offset.getZExtValue(), AddrSpace))
1389 SelectionDAG &DAG = DCI.DAG;
1391 EVT VT = N->getValueType(0);
1393 SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1);
1394 SDValue COffset = DAG.getConstant(Offset, MVT::i32);
1396 return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset);
1399 SDValue SITargetLowering::performAndCombine(SDNode *N,
1400 DAGCombinerInfo &DCI) const {
1401 if (DCI.isBeforeLegalize())
1404 SelectionDAG &DAG = DCI.DAG;
1406 // (and (fcmp ord x, x), (fcmp une (fabs x), inf)) ->
1407 // fp_class x, ~(s_nan | q_nan | n_infinity | p_infinity)
1408 SDValue LHS = N->getOperand(0);
1409 SDValue RHS = N->getOperand(1);
1411 if (LHS.getOpcode() == ISD::SETCC &&
1412 RHS.getOpcode() == ISD::SETCC) {
1413 ISD::CondCode LCC = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
1414 ISD::CondCode RCC = cast<CondCodeSDNode>(RHS.getOperand(2))->get();
1416 SDValue X = LHS.getOperand(0);
1417 SDValue Y = RHS.getOperand(0);
1418 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X)
1421 if (LCC == ISD::SETO) {
1422 if (X != LHS.getOperand(1))
1425 if (RCC == ISD::SETUNE) {
1426 const ConstantFPSDNode *C1 = dyn_cast<ConstantFPSDNode>(RHS.getOperand(1));
1427 if (!C1 || !C1->isInfinity() || C1->isNegative())
1430 const uint32_t Mask = SIInstrFlags::N_NORMAL |
1431 SIInstrFlags::N_SUBNORMAL |
1432 SIInstrFlags::N_ZERO |
1433 SIInstrFlags::P_ZERO |
1434 SIInstrFlags::P_SUBNORMAL |
1435 SIInstrFlags::P_NORMAL;
1437 static_assert(((~(SIInstrFlags::S_NAN |
1438 SIInstrFlags::Q_NAN |
1439 SIInstrFlags::N_INFINITY |
1440 SIInstrFlags::P_INFINITY)) & 0x3ff) == Mask,
1443 return DAG.getNode(AMDGPUISD::FP_CLASS, SDLoc(N), MVT::i1,
1444 X, DAG.getConstant(Mask, MVT::i32));
1452 SDValue SITargetLowering::performOrCombine(SDNode *N,
1453 DAGCombinerInfo &DCI) const {
1454 SelectionDAG &DAG = DCI.DAG;
1455 SDValue LHS = N->getOperand(0);
1456 SDValue RHS = N->getOperand(1);
1458 // or (fp_class x, c1), (fp_class x, c2) -> fp_class x, (c1 | c2)
1459 if (LHS.getOpcode() == AMDGPUISD::FP_CLASS &&
1460 RHS.getOpcode() == AMDGPUISD::FP_CLASS) {
1461 SDValue Src = LHS.getOperand(0);
1462 if (Src != RHS.getOperand(0))
1465 const ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
1466 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
1470 // Only 10 bits are used.
1471 static const uint32_t MaxMask = 0x3ff;
1473 uint32_t NewMask = (CLHS->getZExtValue() | CRHS->getZExtValue()) & MaxMask;
1474 return DAG.getNode(AMDGPUISD::FP_CLASS, SDLoc(N), MVT::i1,
1475 Src, DAG.getConstant(NewMask, MVT::i32));
1481 SDValue SITargetLowering::performClassCombine(SDNode *N,
1482 DAGCombinerInfo &DCI) const {
1483 SelectionDAG &DAG = DCI.DAG;
1484 SDValue Mask = N->getOperand(1);
1486 // fp_class x, 0 -> false
1487 if (const ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Mask)) {
1488 if (CMask->isNullValue())
1489 return DAG.getConstant(0, MVT::i1);
1495 static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
1498 return AMDGPUISD::FMAX3;
1499 case AMDGPUISD::SMAX:
1500 return AMDGPUISD::SMAX3;
1501 case AMDGPUISD::UMAX:
1502 return AMDGPUISD::UMAX3;
1504 return AMDGPUISD::FMIN3;
1505 case AMDGPUISD::SMIN:
1506 return AMDGPUISD::SMIN3;
1507 case AMDGPUISD::UMIN:
1508 return AMDGPUISD::UMIN3;
1510 llvm_unreachable("Not a min/max opcode");
1514 SDValue SITargetLowering::performMin3Max3Combine(SDNode *N,
1515 DAGCombinerInfo &DCI) const {
1516 SelectionDAG &DAG = DCI.DAG;
1518 unsigned Opc = N->getOpcode();
1519 SDValue Op0 = N->getOperand(0);
1520 SDValue Op1 = N->getOperand(1);
1522 // Only do this if the inner op has one use since this will just increases
1523 // register pressure for no benefit.
1525 // max(max(a, b), c)
1526 if (Op0.getOpcode() == Opc && Op0.hasOneUse()) {
1528 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
1536 // max(a, max(b, c))
1537 if (Op1.getOpcode() == Opc && Op1.hasOneUse()) {
1539 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
1550 SDValue SITargetLowering::performSetCCCombine(SDNode *N,
1551 DAGCombinerInfo &DCI) const {
1552 SelectionDAG &DAG = DCI.DAG;
1555 SDValue LHS = N->getOperand(0);
1556 SDValue RHS = N->getOperand(1);
1557 EVT VT = LHS.getValueType();
1559 if (VT != MVT::f32 && VT != MVT::f64)
1562 // Match isinf pattern
1563 // (fcmp oeq (fabs x), inf) -> (fp_class x, (p_infinity | n_infinity))
1564 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
1565 if (CC == ISD::SETOEQ && LHS.getOpcode() == ISD::FABS) {
1566 const ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
1570 const APFloat &APF = CRHS->getValueAPF();
1571 if (APF.isInfinity() && !APF.isNegative()) {
1572 unsigned Mask = SIInstrFlags::P_INFINITY | SIInstrFlags::N_INFINITY;
1573 return DAG.getNode(AMDGPUISD::FP_CLASS, SL, MVT::i1,
1574 LHS.getOperand(0), DAG.getConstant(Mask, MVT::i32));
1581 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
1582 DAGCombinerInfo &DCI) const {
1583 SelectionDAG &DAG = DCI.DAG;
1586 switch (N->getOpcode()) {
1588 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1590 return performSetCCCombine(N, DCI);
1591 case ISD::FMAXNUM: // TODO: What about fmax_legacy?
1593 case AMDGPUISD::SMAX:
1594 case AMDGPUISD::SMIN:
1595 case AMDGPUISD::UMAX:
1596 case AMDGPUISD::UMIN: {
1597 if (DCI.getDAGCombineLevel() >= AfterLegalizeDAG &&
1598 getTargetMachine().getOptLevel() > CodeGenOpt::None)
1599 return performMin3Max3Combine(N, DCI);
1603 case AMDGPUISD::CVT_F32_UBYTE0:
1604 case AMDGPUISD::CVT_F32_UBYTE1:
1605 case AMDGPUISD::CVT_F32_UBYTE2:
1606 case AMDGPUISD::CVT_F32_UBYTE3: {
1607 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
1609 SDValue Src = N->getOperand(0);
1610 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
1612 APInt KnownZero, KnownOne;
1613 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1614 !DCI.isBeforeLegalizeOps());
1615 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1616 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
1617 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
1618 DCI.CommitTargetLoweringOpt(TLO);
1624 case ISD::UINT_TO_FP: {
1625 return performUCharToFloatCombine(N, DCI);
1628 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
1631 EVT VT = N->getValueType(0);
1635 // Only do this if we are not trying to support denormals. v_mad_f32 does
1636 // not support denormals ever.
1637 if (Subtarget->hasFP32Denormals())
1640 SDValue LHS = N->getOperand(0);
1641 SDValue RHS = N->getOperand(1);
1643 // These should really be instruction patterns, but writing patterns with
1644 // source modiifiers is a pain.
1646 // fadd (fadd (a, a), b) -> mad 2.0, a, b
1647 if (LHS.getOpcode() == ISD::FADD) {
1648 SDValue A = LHS.getOperand(0);
1649 if (A == LHS.getOperand(1)) {
1650 const SDValue Two = DAG.getConstantFP(2.0, MVT::f32);
1651 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, RHS);
1655 // fadd (b, fadd (a, a)) -> mad 2.0, a, b
1656 if (RHS.getOpcode() == ISD::FADD) {
1657 SDValue A = RHS.getOperand(0);
1658 if (A == RHS.getOperand(1)) {
1659 const SDValue Two = DAG.getConstantFP(2.0, MVT::f32);
1660 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, LHS);
1667 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
1670 EVT VT = N->getValueType(0);
1672 // Try to get the fneg to fold into the source modifier. This undoes generic
1673 // DAG combines and folds them into the mad.
1675 // Only do this if we are not trying to support denormals. v_mad_f32 does
1676 // not support denormals ever.
1677 if (VT == MVT::f32 &&
1678 !Subtarget->hasFP32Denormals()) {
1679 SDValue LHS = N->getOperand(0);
1680 SDValue RHS = N->getOperand(1);
1681 if (LHS.getOpcode() == ISD::FADD) {
1682 // (fsub (fadd a, a), c) -> mad 2.0, a, (fneg c)
1684 SDValue A = LHS.getOperand(0);
1685 if (A == LHS.getOperand(1)) {
1686 const SDValue Two = DAG.getConstantFP(2.0, MVT::f32);
1687 SDValue NegRHS = DAG.getNode(ISD::FNEG, DL, VT, RHS);
1689 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, NegRHS);
1693 if (RHS.getOpcode() == ISD::FADD) {
1694 // (fsub c, (fadd a, a)) -> mad -2.0, a, c
1696 SDValue A = RHS.getOperand(0);
1697 if (A == RHS.getOperand(1)) {
1698 const SDValue NegTwo = DAG.getConstantFP(-2.0, MVT::f32);
1699 return DAG.getNode(ISD::FMAD, DL, VT, NegTwo, A, LHS);
1711 case ISD::ATOMIC_LOAD:
1712 case ISD::ATOMIC_STORE:
1713 case ISD::ATOMIC_CMP_SWAP:
1714 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
1715 case ISD::ATOMIC_SWAP:
1716 case ISD::ATOMIC_LOAD_ADD:
1717 case ISD::ATOMIC_LOAD_SUB:
1718 case ISD::ATOMIC_LOAD_AND:
1719 case ISD::ATOMIC_LOAD_OR:
1720 case ISD::ATOMIC_LOAD_XOR:
1721 case ISD::ATOMIC_LOAD_NAND:
1722 case ISD::ATOMIC_LOAD_MIN:
1723 case ISD::ATOMIC_LOAD_MAX:
1724 case ISD::ATOMIC_LOAD_UMIN:
1725 case ISD::ATOMIC_LOAD_UMAX: { // TODO: Target mem intrinsics.
1726 if (DCI.isBeforeLegalize())
1729 MemSDNode *MemNode = cast<MemSDNode>(N);
1730 SDValue Ptr = MemNode->getBasePtr();
1732 // TODO: We could also do this for multiplies.
1733 unsigned AS = MemNode->getAddressSpace();
1734 if (Ptr.getOpcode() == ISD::SHL && AS != AMDGPUAS::PRIVATE_ADDRESS) {
1735 SDValue NewPtr = performSHLPtrCombine(Ptr.getNode(), AS, DCI);
1737 SmallVector<SDValue, 8> NewOps(MemNode->op_begin(), MemNode->op_end());
1739 NewOps[N->getOpcode() == ISD::STORE ? 2 : 1] = NewPtr;
1740 return SDValue(DAG.UpdateNodeOperands(MemNode, NewOps), 0);
1746 return performAndCombine(N, DCI);
1748 return performOrCombine(N, DCI);
1749 case AMDGPUISD::FP_CLASS:
1750 return performClassCombine(N, DCI);
1752 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1755 /// \brief Analyze the possible immediate value Op
1757 /// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
1758 /// and the immediate value if it's a literal immediate
1759 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
1761 const SIInstrInfo *TII =
1762 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
1764 if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
1765 if (TII->isInlineConstant(Node->getAPIntValue()))
1768 uint64_t Val = Node->getZExtValue();
1769 return isUInt<32>(Val) ? Val : -1;
1772 if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
1773 if (TII->isInlineConstant(Node->getValueAPF().bitcastToAPInt()))
1776 if (Node->getValueType(0) == MVT::f32)
1777 return FloatToBits(Node->getValueAPF().convertToFloat());
1785 /// \brief Helper function for adjustWritemask
1786 static unsigned SubIdx2Lane(unsigned Idx) {
1789 case AMDGPU::sub0: return 0;
1790 case AMDGPU::sub1: return 1;
1791 case AMDGPU::sub2: return 2;
1792 case AMDGPU::sub3: return 3;
1796 /// \brief Adjust the writemask of MIMG instructions
1797 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
1798 SelectionDAG &DAG) const {
1799 SDNode *Users[4] = { };
1801 unsigned OldDmask = Node->getConstantOperandVal(0);
1802 unsigned NewDmask = 0;
1804 // Try to figure out the used register components
1805 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
1808 // Abort if we can't understand the usage
1809 if (!I->isMachineOpcode() ||
1810 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
1813 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
1814 // Note that subregs are packed, i.e. Lane==0 is the first bit set
1815 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
1817 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
1819 // Set which texture component corresponds to the lane.
1821 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
1823 Comp = countTrailingZeros(Dmask);
1824 Dmask &= ~(1 << Comp);
1827 // Abort if we have more than one user per component
1832 NewDmask |= 1 << Comp;
1835 // Abort if there's no change
1836 if (NewDmask == OldDmask)
1839 // Adjust the writemask in the node
1840 std::vector<SDValue> Ops;
1841 Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32));
1842 Ops.insert(Ops.end(), Node->op_begin() + 1, Node->op_end());
1843 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
1845 // If we only got one lane, replace it with a copy
1846 // (if NewDmask has only one bit set...)
1847 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
1848 SDValue RC = DAG.getTargetConstant(AMDGPU::VGPR_32RegClassID, MVT::i32);
1849 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
1850 SDLoc(), Users[Lane]->getValueType(0),
1851 SDValue(Node, 0), RC);
1852 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
1856 // Update the users of the node with the new indices
1857 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
1859 SDNode *User = Users[i];
1863 SDValue Op = DAG.getTargetConstant(Idx, MVT::i32);
1864 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
1868 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
1869 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
1870 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
1875 /// \brief Legalize target independent instructions (e.g. INSERT_SUBREG)
1876 /// with frame index operands.
1877 /// LLVM assumes that inputs are to these instructions are registers.
1878 void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
1879 SelectionDAG &DAG) const {
1881 SmallVector<SDValue, 8> Ops;
1882 for (unsigned i = 0; i < Node->getNumOperands(); ++i) {
1883 if (!isa<FrameIndexSDNode>(Node->getOperand(i))) {
1884 Ops.push_back(Node->getOperand(i));
1889 Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
1890 Node->getOperand(i).getValueType(),
1891 Node->getOperand(i)), 0));
1894 DAG.UpdateNodeOperands(Node, Ops);
1897 /// \brief Fold the instructions after selecting them.
1898 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
1899 SelectionDAG &DAG) const {
1900 const SIInstrInfo *TII =
1901 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
1903 if (TII->isMIMG(Node->getMachineOpcode()))
1904 adjustWritemask(Node, DAG);
1906 if (Node->getMachineOpcode() == AMDGPU::INSERT_SUBREG ||
1907 Node->getMachineOpcode() == AMDGPU::REG_SEQUENCE) {
1908 legalizeTargetIndependentNode(Node, DAG);
1914 /// \brief Assign the register class depending on the number of
1915 /// bits set in the writemask
1916 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
1917 SDNode *Node) const {
1918 const SIInstrInfo *TII =
1919 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
1921 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1922 TII->legalizeOperands(MI);
1924 if (TII->isMIMG(MI->getOpcode())) {
1925 unsigned VReg = MI->getOperand(0).getReg();
1926 unsigned Writemask = MI->getOperand(1).getImm();
1927 unsigned BitsSet = 0;
1928 for (unsigned i = 0; i < 4; ++i)
1929 BitsSet += Writemask & (1 << i) ? 1 : 0;
1931 const TargetRegisterClass *RC;
1934 case 1: RC = &AMDGPU::VGPR_32RegClass; break;
1935 case 2: RC = &AMDGPU::VReg_64RegClass; break;
1936 case 3: RC = &AMDGPU::VReg_96RegClass; break;
1939 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
1940 MI->setDesc(TII->get(NewOpcode));
1941 MRI.setRegClass(VReg, RC);
1945 // Replace unused atomics with the no return version.
1946 int NoRetAtomicOp = AMDGPU::getAtomicNoRetOp(MI->getOpcode());
1947 if (NoRetAtomicOp != -1) {
1948 if (!Node->hasAnyUseOfValue(0)) {
1949 MI->setDesc(TII->get(NoRetAtomicOp));
1950 MI->RemoveOperand(0);
1957 static SDValue buildSMovImm32(SelectionDAG &DAG, SDLoc DL, uint64_t Val) {
1958 SDValue K = DAG.getTargetConstant(Val, MVT::i32);
1959 return SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0);
1962 MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
1964 SDValue Ptr) const {
1965 const SIInstrInfo *TII =
1966 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
1968 // XXX - Workaround for moveToVALU not handling different register class
1969 // inserts for REG_SEQUENCE.
1971 // Build the half of the subregister with the constants.
1972 const SDValue Ops0[] = {
1973 DAG.getTargetConstant(AMDGPU::SGPR_64RegClassID, MVT::i32),
1974 buildSMovImm32(DAG, DL, 0),
1975 DAG.getTargetConstant(AMDGPU::sub0, MVT::i32),
1976 buildSMovImm32(DAG, DL, TII->getDefaultRsrcDataFormat() >> 32),
1977 DAG.getTargetConstant(AMDGPU::sub1, MVT::i32)
1980 SDValue SubRegHi = SDValue(DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL,
1981 MVT::v2i32, Ops0), 0);
1983 // Combine the constants and the pointer.
1984 const SDValue Ops1[] = {
1985 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32),
1987 DAG.getTargetConstant(AMDGPU::sub0_sub1, MVT::i32),
1989 DAG.getTargetConstant(AMDGPU::sub2_sub3, MVT::i32)
1992 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1);
1994 const SDValue Ops[] = {
1995 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32),
1997 DAG.getTargetConstant(AMDGPU::sub0_sub1, MVT::i32),
1998 buildSMovImm32(DAG, DL, 0),
1999 DAG.getTargetConstant(AMDGPU::sub2, MVT::i32),
2000 buildSMovImm32(DAG, DL, TII->getDefaultRsrcFormat() >> 32),
2001 DAG.getTargetConstant(AMDGPU::sub3, MVT::i32)
2004 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
2009 /// \brief Return a resource descriptor with the 'Add TID' bit enabled
2010 /// The TID (Thread ID) is multipled by the stride value (bits [61:48]
2011 /// of the resource descriptor) to create an offset, which is added to the
2012 /// resource ponter.
2013 MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG,
2016 uint32_t RsrcDword1,
2017 uint64_t RsrcDword2And3) const {
2018 SDValue PtrLo = DAG.getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr);
2019 SDValue PtrHi = DAG.getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
2021 PtrHi = SDValue(DAG.getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,
2022 DAG.getConstant(RsrcDword1, MVT::i32)), 0);
2025 SDValue DataLo = buildSMovImm32(DAG, DL,
2026 RsrcDword2And3 & UINT64_C(0xFFFFFFFF));
2027 SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32);
2029 const SDValue Ops[] = {
2030 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32),
2032 DAG.getTargetConstant(AMDGPU::sub0, MVT::i32),
2034 DAG.getTargetConstant(AMDGPU::sub1, MVT::i32),
2036 DAG.getTargetConstant(AMDGPU::sub2, MVT::i32),
2038 DAG.getTargetConstant(AMDGPU::sub3, MVT::i32)
2041 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
2044 MachineSDNode *SITargetLowering::buildScratchRSRC(SelectionDAG &DAG,
2046 SDValue Ptr) const {
2047 const SIInstrInfo *TII =
2048 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2049 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | AMDGPU::RSRC_TID_ENABLE |
2052 return buildRSRC(DAG, DL, Ptr, 0, Rsrc);
2055 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2056 const TargetRegisterClass *RC,
2057 unsigned Reg, EVT VT) const {
2058 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
2060 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
2061 cast<RegisterSDNode>(VReg)->getReg(), VT);