1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for SI
13 //===----------------------------------------------------------------------===//
15 #include "SIISelLowering.h"
17 #include "AMDILIntrinsicInfo.h"
18 #include "SIInstrInfo.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "SIRegisterInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
27 SITargetLowering::SITargetLowering(TargetMachine &TM) :
28 AMDGPUTargetLowering(TM),
29 TII(static_cast<const SIInstrInfo*>(TM.getInstrInfo())) {
30 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
31 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
32 addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass);
33 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
34 addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass);
36 addRegisterClass(MVT::v1i32, &AMDGPU::VReg_32RegClass);
37 addRegisterClass(MVT::v2i32, &AMDGPU::VReg_64RegClass);
38 addRegisterClass(MVT::v4i32, &AMDGPU::VReg_128RegClass);
39 addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
40 addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
42 computeRegisterProperties();
44 setOperationAction(ISD::ADD, MVT::i64, Legal);
45 setOperationAction(ISD::ADD, MVT::i32, Legal);
47 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
49 // We need to custom lower loads from the USER_SGPR address space, so we can
50 // add the SGPRs as livein registers.
51 setOperationAction(ISD::LOAD, MVT::i32, Custom);
52 setOperationAction(ISD::LOAD, MVT::i64, Custom);
54 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
55 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
57 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
58 setTargetDAGCombine(ISD::SELECT_CC);
60 setTargetDAGCombine(ISD::SETCC);
63 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
64 MachineInstr * MI, MachineBasicBlock * BB) const {
65 const TargetInstrInfo * TII = getTargetMachine().getInstrInfo();
66 MachineRegisterInfo & MRI = BB->getParent()->getRegInfo();
67 MachineBasicBlock::iterator I = MI;
69 switch (MI->getOpcode()) {
71 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
72 case AMDGPU::BRANCH: return BB;
73 case AMDGPU::CLAMP_SI:
74 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_ADD_F32_e64))
75 .addOperand(MI->getOperand(0))
76 .addOperand(MI->getOperand(1))
83 MI->eraseFromParent();
87 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_ADD_F32_e64))
88 .addOperand(MI->getOperand(0))
89 .addOperand(MI->getOperand(1))
96 MI->eraseFromParent();
100 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_ADD_F32_e64))
101 .addOperand(MI->getOperand(0))
102 .addOperand(MI->getOperand(1))
103 .addImm(0x80) // SRC1
104 .addImm(0x80) // SRC2
109 MI->eraseFromParent();
111 case AMDGPU::SHADER_TYPE:
112 BB->getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType =
113 MI->getOperand(0).getImm();
114 MI->eraseFromParent();
117 case AMDGPU::SI_INTERP:
118 LowerSI_INTERP(MI, *BB, I, MRI);
121 LowerSI_WQM(MI, *BB, I, MRI);
123 case AMDGPU::SI_V_CNDLT:
124 LowerSI_V_CNDLT(MI, *BB, I, MRI);
130 void SITargetLowering::LowerSI_WQM(MachineInstr *MI, MachineBasicBlock &BB,
131 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const {
132 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_WQM_B64), AMDGPU::EXEC)
133 .addReg(AMDGPU::EXEC);
135 MI->eraseFromParent();
138 void SITargetLowering::LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB,
139 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const {
140 unsigned tmp = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
141 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass);
142 MachineOperand dst = MI->getOperand(0);
143 MachineOperand iReg = MI->getOperand(1);
144 MachineOperand jReg = MI->getOperand(2);
145 MachineOperand attr_chan = MI->getOperand(3);
146 MachineOperand attr = MI->getOperand(4);
147 MachineOperand params = MI->getOperand(5);
149 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
152 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P1_F32), tmp)
154 .addOperand(attr_chan)
158 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P2_F32))
162 .addOperand(attr_chan)
166 MI->eraseFromParent();
169 void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
170 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const {
171 unsigned VCC = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
173 BuildMI(BB, I, BB.findDebugLoc(I),
174 TII->get(AMDGPU::V_CMP_GT_F32_e32),
177 .addOperand(MI->getOperand(1));
179 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CNDMASK_B32_e32))
180 .addOperand(MI->getOperand(0))
181 .addOperand(MI->getOperand(3))
182 .addOperand(MI->getOperand(2))
185 MI->eraseFromParent();
188 EVT SITargetLowering::getSetCCResultType(EVT VT) const {
192 //===----------------------------------------------------------------------===//
193 // Custom DAG Lowering Operations
194 //===----------------------------------------------------------------------===//
196 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
197 switch (Op.getOpcode()) {
198 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
199 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
200 case ISD::LOAD: return LowerLOAD(Op, DAG);
201 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
202 case ISD::INTRINSIC_WO_CHAIN: {
203 unsigned IntrinsicID =
204 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
205 EVT VT = Op.getValueType();
206 switch (IntrinsicID) {
207 case AMDGPUIntrinsic::SI_vs_load_buffer_index:
208 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
210 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
218 /// \brief Helper function for LowerBRCOND
219 static SDNode *findUser(SDValue Value, unsigned Opcode) {
221 SDNode *Parent = Value.getNode();
222 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
225 if (I.getUse().get() != Value)
228 if (I->getOpcode() == Opcode)
234 /// This transforms the control flow intrinsics to get the branch destination as
235 /// last parameter, also switches branch target with BR if the need arise
236 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
237 SelectionDAG &DAG) const {
239 DebugLoc DL = BRCOND.getDebugLoc();
241 SDNode *Intr = BRCOND.getOperand(1).getNode();
242 SDValue Target = BRCOND.getOperand(2);
245 if (Intr->getOpcode() == ISD::SETCC) {
246 // As long as we negate the condition everything is fine
247 SDNode *SetCC = Intr;
248 assert(SetCC->getConstantOperandVal(1) == 1);
249 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
251 Intr = SetCC->getOperand(0).getNode();
254 // Get the target from BR if we don't negate the condition
255 BR = findUser(BRCOND, ISD::BR);
256 Target = BR->getOperand(1);
259 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
261 // Build the result and
262 SmallVector<EVT, 4> Res;
263 for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i)
264 Res.push_back(Intr->getValueType(i));
266 // operands of the new intrinsic call
267 SmallVector<SDValue, 4> Ops;
268 Ops.push_back(BRCOND.getOperand(0));
269 for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i)
270 Ops.push_back(Intr->getOperand(i));
271 Ops.push_back(Target);
273 // build the new intrinsic call
274 SDNode *Result = DAG.getNode(
275 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
276 DAG.getVTList(Res.data(), Res.size()), Ops.data(), Ops.size()).getNode();
279 // Give the branch instruction our target
284 DAG.MorphNodeTo(BR, ISD::BR, BR->getVTList(), Ops, 2);
287 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
289 // Copy the intrinsic results to registers
290 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
291 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
295 Chain = DAG.getCopyToReg(
297 CopyToReg->getOperand(1),
298 SDValue(Result, i - 1),
301 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
304 // Remove the old intrinsic from the chain
305 DAG.ReplaceAllUsesOfValueWith(
306 SDValue(Intr, Intr->getNumValues() - 1),
307 Intr->getOperand(0));
312 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
313 EVT VT = Op.getValueType();
314 LoadSDNode *Ptr = dyn_cast<LoadSDNode>(Op);
318 unsigned AddrSpace = Ptr->getPointerInfo().getAddrSpace();
320 // We only need to lower USER_SGPR address space loads
321 if (AddrSpace != AMDGPUAS::USER_SGPR_ADDRESS) {
325 // Loads from the USER_SGPR address space can only have constant value
327 ConstantSDNode *BasePtr = dyn_cast<ConstantSDNode>(Ptr->getBasePtr());
330 unsigned TypeDwordWidth = VT.getSizeInBits() / 32;
331 const TargetRegisterClass * dstClass;
332 switch (TypeDwordWidth) {
334 assert(!"USER_SGPR value size not implemented");
337 dstClass = &AMDGPU::SReg_32RegClass;
340 dstClass = &AMDGPU::SReg_64RegClass;
343 uint64_t Index = BasePtr->getZExtValue();
344 assert(Index % TypeDwordWidth == 0 && "USER_SGPR not properly aligned");
345 unsigned SGPRIndex = Index / TypeDwordWidth;
346 unsigned Reg = dstClass->getRegister(SGPRIndex);
348 DAG.ReplaceAllUsesOfValueWith(Op, CreateLiveInRegister(DAG, dstClass, Reg,
353 SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
354 SDValue LHS = Op.getOperand(0);
355 SDValue RHS = Op.getOperand(1);
356 SDValue True = Op.getOperand(2);
357 SDValue False = Op.getOperand(3);
358 SDValue CC = Op.getOperand(4);
359 EVT VT = Op.getValueType();
360 DebugLoc DL = Op.getDebugLoc();
362 // Possible Min/Max pattern
363 SDValue MinMax = LowerMinMax(Op, DAG);
364 if (MinMax.getNode()) {
368 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
369 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
372 //===----------------------------------------------------------------------===//
373 // Custom DAG optimizations
374 //===----------------------------------------------------------------------===//
376 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
377 DAGCombinerInfo &DCI) const {
378 SelectionDAG &DAG = DCI.DAG;
379 DebugLoc DL = N->getDebugLoc();
380 EVT VT = N->getValueType(0);
382 switch (N->getOpcode()) {
384 case ISD::SELECT_CC: {
386 ConstantSDNode *True, *False;
387 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
388 if ((True = dyn_cast<ConstantSDNode>(N->getOperand(2)))
389 && (False = dyn_cast<ConstantSDNode>(N->getOperand(3)))
390 && True->isAllOnesValue()
391 && False->isNullValue()
393 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
394 N->getOperand(1), N->getOperand(4));
400 SDValue Arg0 = N->getOperand(0);
401 SDValue Arg1 = N->getOperand(1);
402 SDValue CC = N->getOperand(2);
403 ConstantSDNode * C = NULL;
404 ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
406 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
408 && Arg0.getOpcode() == ISD::SIGN_EXTEND
409 && Arg0.getOperand(0).getValueType() == MVT::i1
410 && (C = dyn_cast<ConstantSDNode>(Arg1))
412 && CCOp == ISD::SETNE) {
413 return SimplifySetCC(VT, Arg0.getOperand(0),
414 DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL);