1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // R600 Tablegen instruction definitions
12 //===----------------------------------------------------------------------===//
14 include "R600Intrinsics.td"
16 class InstR600 <bits<11> inst, dag outs, dag ins, string asm, list<dag> pattern,
18 : AMDGPUInst <outs, ins, asm, pattern> {
24 bits<2> FlagOperandIdx = 0;
27 bit HasNativeOperands = 0;
29 bits<11> op_code = inst;
31 let Namespace = "AMDGPU";
32 let OutOperandList = outs;
33 let InOperandList = ins;
35 let Pattern = pattern;
38 let TSFlags{4} = Trig;
41 // Vector instructions are instructions that must fill all slots in an
43 let TSFlags{6} = isVector;
44 let TSFlags{8-7} = FlagOperandIdx;
45 let TSFlags{9} = HasNativeOperands;
46 let TSFlags{10} = Op1;
47 let TSFlags{11} = Op2;
50 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
51 AMDGPUInst <outs, ins, asm, pattern> {
54 let Namespace = "AMDGPU";
57 def MEMxi : Operand<iPTR> {
58 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
59 let PrintMethod = "printMemOperand";
62 def MEMrr : Operand<iPTR> {
63 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
66 // Operands for non-registers
68 class InstFlag<string PM = "printOperand", int Default = 0>
69 : OperandWithDefaultOps <i32, (ops (i32 Default))> {
73 // src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
74 def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
75 let PrintMethod = "printSel";
78 def LITERAL : InstFlag<"printLiteral">;
80 def WRITE : InstFlag <"printWrite", 1>;
81 def OMOD : InstFlag <"printOMOD">;
82 def REL : InstFlag <"printRel">;
83 def CLAMP : InstFlag <"printClamp">;
84 def NEG : InstFlag <"printNeg">;
85 def ABS : InstFlag <"printAbs">;
86 def UEM : InstFlag <"printUpdateExecMask">;
87 def UP : InstFlag <"printUpdatePred">;
89 // XXX: The r600g finalizer in Mesa expects last to be one in most cases.
90 // Once we start using the packetizer in this backend we should have this
92 def LAST : InstFlag<"printLast", 1>;
94 def FRAMEri : Operand<iPTR> {
95 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index);
98 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
99 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
100 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
101 def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;
102 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
103 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
105 class R600ALU_Word0 {
106 field bits<32> Word0;
114 bits<3> index_mode = 0;
118 bits<9> src0_sel = src0{8-0};
119 bits<2> src0_chan = src0{10-9};
120 bits<9> src1_sel = src1{8-0};
121 bits<2> src1_chan = src1{10-9};
123 let Word0{8-0} = src0_sel;
124 let Word0{9} = src0_rel;
125 let Word0{11-10} = src0_chan;
126 let Word0{12} = src0_neg;
127 let Word0{21-13} = src1_sel;
128 let Word0{22} = src1_rel;
129 let Word0{24-23} = src1_chan;
130 let Word0{25} = src1_neg;
131 let Word0{28-26} = index_mode;
132 let Word0{30-29} = pred_sel;
133 let Word0{31} = last;
136 class R600ALU_Word1 {
137 field bits<32> Word1;
140 bits<3> bank_swizzle = 0;
144 bits<7> dst_sel = dst{6-0};
145 bits<2> dst_chan = dst{10-9};
147 let Word1{20-18} = bank_swizzle;
148 let Word1{27-21} = dst_sel;
149 let Word1{28} = dst_rel;
150 let Word1{30-29} = dst_chan;
151 let Word1{31} = clamp;
154 class R600ALU_Word1_OP2 <bits<11> alu_inst> : R600ALU_Word1{
158 bits<1> update_exec_mask;
163 let Word1{0} = src0_abs;
164 let Word1{1} = src1_abs;
165 let Word1{2} = update_exec_mask;
166 let Word1{3} = update_pred;
167 let Word1{4} = write;
168 let Word1{6-5} = omod;
169 let Word1{17-7} = alu_inst;
172 class R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{
178 bits<9> src2_sel = src2{8-0};
179 bits<2> src2_chan = src2{10-9};
181 let Word1{8-0} = src2_sel;
182 let Word1{9} = src2_rel;
183 let Word1{11-10} = src2_chan;
184 let Word1{12} = src2_neg;
185 let Word1{17-13} = alu_inst;
189 field bits<32> Word0;
193 bits<1> FETCH_WHOLE_QUAD;
197 bits<6> MEGA_FETCH_COUNT;
199 let Word0{4-0} = VC_INST;
200 let Word0{6-5} = FETCH_TYPE;
201 let Word0{7} = FETCH_WHOLE_QUAD;
202 let Word0{15-8} = BUFFER_ID;
203 let Word0{22-16} = SRC_GPR;
204 let Word0{23} = SRC_REL;
205 let Word0{25-24} = SRC_SEL_X;
206 let Word0{31-26} = MEGA_FETCH_COUNT;
209 class VTX_WORD1_GPR {
210 field bits<32> Word1;
217 bits<1> USE_CONST_FIELDS;
219 bits<2> NUM_FORMAT_ALL;
220 bits<1> FORMAT_COMP_ALL;
221 bits<1> SRF_MODE_ALL;
223 let Word1{6-0} = DST_GPR;
224 let Word1{7} = DST_REL;
225 let Word1{8} = 0; // Reserved
226 let Word1{11-9} = DST_SEL_X;
227 let Word1{14-12} = DST_SEL_Y;
228 let Word1{17-15} = DST_SEL_Z;
229 let Word1{20-18} = DST_SEL_W;
230 let Word1{21} = USE_CONST_FIELDS;
231 let Word1{27-22} = DATA_FORMAT;
232 let Word1{29-28} = NUM_FORMAT_ALL;
233 let Word1{30} = FORMAT_COMP_ALL;
234 let Word1{31} = SRF_MODE_ALL;
238 field bits<32> Word0;
242 bits<1> FETCH_WHOLE_QUAD;
247 bits<2> RESOURCE_INDEX_MODE;
248 bits<2> SAMPLER_INDEX_MODE;
250 let Word0{4-0} = TEX_INST;
251 let Word0{6-5} = INST_MOD;
252 let Word0{7} = FETCH_WHOLE_QUAD;
253 let Word0{15-8} = RESOURCE_ID;
254 let Word0{22-16} = SRC_GPR;
255 let Word0{23} = SRC_REL;
256 let Word0{24} = ALT_CONST;
257 let Word0{26-25} = RESOURCE_INDEX_MODE;
258 let Word0{28-27} = SAMPLER_INDEX_MODE;
262 field bits<32> Word1;
271 bits<1> COORD_TYPE_X;
272 bits<1> COORD_TYPE_Y;
273 bits<1> COORD_TYPE_Z;
274 bits<1> COORD_TYPE_W;
276 let Word1{6-0} = DST_GPR;
277 let Word1{7} = DST_REL;
278 let Word1{11-9} = DST_SEL_X;
279 let Word1{14-12} = DST_SEL_Y;
280 let Word1{17-15} = DST_SEL_Z;
281 let Word1{20-18} = DST_SEL_W;
282 let Word1{27-21} = LOD_BIAS;
283 let Word1{28} = COORD_TYPE_X;
284 let Word1{29} = COORD_TYPE_Y;
285 let Word1{30} = COORD_TYPE_Z;
286 let Word1{31} = COORD_TYPE_W;
290 field bits<32> Word2;
301 let Word2{4-0} = OFFSET_X;
302 let Word2{9-5} = OFFSET_Y;
303 let Word2{14-10} = OFFSET_Z;
304 let Word2{19-15} = SAMPLER_ID;
305 let Word2{22-20} = SRC_SEL_X;
306 let Word2{25-23} = SRC_SEL_Y;
307 let Word2{28-26} = SRC_SEL_Z;
308 let Word2{31-29} = SRC_SEL_W;
312 XXX: R600 subtarget uses a slightly different encoding than the other
313 subtargets. We currently handle this in R600MCCodeEmitter, but we may
314 want to use these instruction classes in the future.
316 class R600ALU_Word1_OP2_r600 : R600ALU_Word1_OP2 {
321 let Inst{37} = fog_merge;
322 let Inst{39-38} = omod;
323 let Inst{49-40} = alu_inst;
326 class R600ALU_Word1_OP2_r700 : R600ALU_Word1_OP2 {
330 let Inst{38-37} = omod;
331 let Inst{49-39} = alu_inst;
335 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
339 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
341 // Class for instructions with only one source register.
342 // If you add new ins to this instruction, make sure they are listed before
343 // $literal, because the backend currently assumes that the last operand is
344 // a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in
345 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(),
346 // and R600InstrInfo::getOperandIdx().
347 class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
348 InstrItinClass itin = AnyALU> :
350 (outs R600_Reg32:$dst),
351 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
352 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
353 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
355 "$clamp $dst$write$dst_rel$omod, "
356 "$src0_neg$src0_abs$src0$src0_sel$src0_abs$src0_rel, "
357 "$literal $pred_sel$last"),
361 R600ALU_Word1_OP2 <inst> {
367 let update_exec_mask = 0;
369 let HasNativeOperands = 1;
371 let DisableEncoding = "$literal";
373 let Inst{31-0} = Word0;
374 let Inst{63-32} = Word1;
377 class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
378 InstrItinClass itin = AnyALU> :
379 R600_1OP <inst, opName,
380 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))]
383 // If you add our change the operands for R600_2OP instructions, you must
384 // also update the R600Op2OperandIndex::ROI enum in R600Defines.h,
385 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
386 class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
387 InstrItinClass itin = AnyALU> :
389 (outs R600_Reg32:$dst),
390 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
391 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
392 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
393 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
394 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
396 "$clamp $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
397 "$src0_neg$src0_abs$src0$src0_sel$src0_abs$src0_rel, "
398 "$src1_neg$src1_abs$src1$src1_sel$src1_abs$src1_rel, "
399 "$literal $pred_sel$last"),
403 R600ALU_Word1_OP2 <inst> {
405 let HasNativeOperands = 1;
407 let DisableEncoding = "$literal";
409 let Inst{31-0} = Word0;
410 let Inst{63-32} = Word1;
413 class R600_2OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
414 InstrItinClass itim = AnyALU> :
415 R600_2OP <inst, opName,
416 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
420 // If you add our change the operands for R600_3OP instructions, you must
421 // also update the R600Op3OperandIndex::ROI enum in R600Defines.h,
422 // R600InstrInfo::buildDefaultInstruction(), and
423 // R600InstrInfo::getOperandIdx().
424 class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
425 InstrItinClass itin = AnyALU> :
427 (outs R600_Reg32:$dst),
428 (ins REL:$dst_rel, CLAMP:$clamp,
429 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
430 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
431 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
432 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
433 !strconcat(opName, "$clamp $dst$dst_rel, "
434 "$src0_neg$src0$src0_sel$src0_rel, "
435 "$src1_neg$src1$src1_sel$src1_rel, "
436 "$src2_neg$src2$src2_sel$src2_rel, "
437 "$literal $pred_sel$last"),
441 R600ALU_Word1_OP3<inst>{
443 let HasNativeOperands = 1;
444 let DisableEncoding = "$literal";
447 let Inst{31-0} = Word0;
448 let Inst{63-32} = Word1;
451 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
452 InstrItinClass itin = VecALU> :
454 (outs R600_Reg32:$dst),
460 class R600_TEX <bits<11> inst, string opName, list<dag> pattern,
461 InstrItinClass itin = AnyALU> :
463 (outs R600_Reg128:$DST_GPR),
464 (ins R600_Reg128:$SRC_GPR, i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID, i32imm:$textureTarget),
465 !strconcat(opName, "$DST_GPR, $SRC_GPR, $RESOURCE_ID, $SAMPLER_ID, $textureTarget"),
467 itin>, TEX_WORD0, TEX_WORD1, TEX_WORD2 {
468 let Inst{31-0} = Word0;
469 let Inst{63-32} = Word1;
471 let TEX_INST = inst{4-0};
481 let FETCH_WHOLE_QUAD = 0;
483 let SAMPLER_INDEX_MODE = 0;
485 let COORD_TYPE_X = 0;
486 let COORD_TYPE_Y = 0;
487 let COORD_TYPE_Z = 0;
488 let COORD_TYPE_W = 0;
491 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
493 def TEX_SHADOW : PatLeaf<
495 [{uint32_t TType = (uint32_t)N->getZExtValue();
496 return (TType >= 6 && TType <= 8) || (TType >= 11 && TType <= 13);
500 def TEX_RECT : PatLeaf<
502 [{uint32_t TType = (uint32_t)N->getZExtValue();
507 def TEX_ARRAY : PatLeaf<
509 [{uint32_t TType = (uint32_t)N->getZExtValue();
510 return TType == 9 || TType == 10 || TType == 15 || TType == 16;
514 def TEX_SHADOW_ARRAY : PatLeaf<
516 [{uint32_t TType = (uint32_t)N->getZExtValue();
517 return TType == 11 || TType == 12 || TType == 17;
521 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
522 dag ins, string asm, list<dag> pattern> :
523 InstR600ISA <outs, ins, asm, pattern> {
540 // CF_ALLOC_EXPORT_WORD0_RAT
541 let Inst{3-0} = rat_id;
542 let Inst{9-4} = rat_inst;
543 let Inst{10} = 0; // Reserved
544 let Inst{12-11} = RIM;
545 let Inst{14-13} = TYPE;
546 let Inst{21-15} = RW_GPR;
547 let Inst{22} = RW_REL;
548 let Inst{29-23} = INDEX_GPR;
549 let Inst{31-30} = ELEM_SIZE;
551 // CF_ALLOC_EXPORT_WORD1_BUF
552 let Inst{43-32} = ARRAY_SIZE;
553 let Inst{47-44} = COMP_MASK;
554 let Inst{51-48} = BURST_COUNT;
557 let Inst{61-54} = cf_inst;
559 let Inst{63} = BARRIER;
562 class LoadParamFrag <PatFrag load_type> : PatFrag <
563 (ops node:$ptr), (load_type node:$ptr),
564 [{ return isParamLoad(dyn_cast<LoadSDNode>(N)); }]
567 def load_param : LoadParamFrag<load>;
568 def load_param_zexti8 : LoadParamFrag<zextloadi8>;
569 def load_param_zexti16 : LoadParamFrag<zextloadi16>;
571 def isR600 : Predicate<"Subtarget.device()"
572 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX">;
573 def isR700 : Predicate<"Subtarget.device()"
574 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX &&"
575 "Subtarget.device()->getDeviceFlag()"
576 ">= OCL_DEVICE_RV710">;
577 def isEG : Predicate<
578 "Subtarget.device()->getGeneration() >= AMDGPUDeviceInfo::HD5XXX && "
579 "Subtarget.device()->getGeneration() < AMDGPUDeviceInfo::HD7XXX && "
580 "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
582 def isCayman : Predicate<"Subtarget.device()"
583 "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
584 def isEGorCayman : Predicate<"Subtarget.device()"
585 "->getGeneration() == AMDGPUDeviceInfo::HD5XXX"
586 "|| Subtarget.device()->getGeneration() =="
587 "AMDGPUDeviceInfo::HD6XXX">;
589 def isR600toCayman : Predicate<
590 "Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX">;
592 //===----------------------------------------------------------------------===//
594 //===----------------------------------------------------------------------===//
596 def INTERP_PAIR_XY : AMDGPUShaderInst <
597 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),
598 (ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
599 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
602 def INTERP_PAIR_ZW : AMDGPUShaderInst <
603 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),
604 (ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
605 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
608 def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS",
609 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>,
613 //===----------------------------------------------------------------------===//
614 // Interpolation Instructions
615 //===----------------------------------------------------------------------===//
617 def INTERP_VEC_LOAD : AMDGPUShaderInst <
618 (outs R600_Reg128:$dst),
620 "INTERP_LOAD $src0 : $dst",
623 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {
624 let bank_swizzle = 5;
627 def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> {
628 let bank_swizzle = 5;
631 def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
633 //===----------------------------------------------------------------------===//
634 // Export Instructions
635 //===----------------------------------------------------------------------===//
637 def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
639 def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
640 [SDNPHasChain, SDNPSideEffect]>;
643 field bits<32> Word0;
650 let Word0{12-0} = arraybase;
651 let Word0{14-13} = type;
652 let Word0{21-15} = gpr;
653 let Word0{22} = 0; // RW_REL
654 let Word0{29-23} = 0; // INDEX_GPR
655 let Word0{31-30} = elem_size;
658 class ExportSwzWord1 {
659 field bits<32> Word1;
668 let Word1{2-0} = sw_x;
669 let Word1{5-3} = sw_y;
670 let Word1{8-6} = sw_z;
671 let Word1{11-9} = sw_w;
674 class ExportBufWord1 {
675 field bits<32> Word1;
682 let Word1{11-0} = arraySize;
683 let Word1{15-12} = compMask;
686 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
687 def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg),
689 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
690 0, 61, 0, 7, 7, 7, cf_inst, 0)
693 def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg),
695 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
696 0, 61, 7, 0, 7, 7, cf_inst, 0)
699 def : Pat<(int_R600_store_dummy (i32 imm:$type)),
701 (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
704 def : Pat<(int_R600_store_dummy 1),
706 (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
709 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
710 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
711 (ExportInst R600_Reg128:$src, imm:$type, imm:$base,
712 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)
717 multiclass SteamOutputExportPattern<Instruction ExportInst,
718 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
720 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
721 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),
722 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
723 4095, imm:$mask, buf0inst, 0)>;
725 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
726 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),
727 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
728 4095, imm:$mask, buf1inst, 0)>;
730 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
731 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),
732 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
733 4095, imm:$mask, buf2inst, 0)>;
735 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
736 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),
737 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
738 4095, imm:$mask, buf3inst, 0)>;
741 let usesCustomInserter = 1 in {
743 class ExportSwzInst : InstR600ISA<(
745 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
746 i32imm:$sw_x, i32imm:$sw_y, i32imm:$sw_z, i32imm:$sw_w, i32imm:$inst,
748 !strconcat("EXPORT", " $gpr"),
749 []>, ExportWord0, ExportSwzWord1 {
751 let Inst{31-0} = Word0;
752 let Inst{63-32} = Word1;
755 } // End usesCustomInserter = 1
757 class ExportBufInst : InstR600ISA<(
759 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
760 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop),
761 !strconcat("EXPORT", " $gpr"),
762 []>, ExportWord0, ExportBufWord1 {
764 let Inst{31-0} = Word0;
765 let Inst{63-32} = Word1;
768 let Predicates = [isR600toCayman] in {
770 //===----------------------------------------------------------------------===//
771 // Common Instructions R600, R700, Evergreen, Cayman
772 //===----------------------------------------------------------------------===//
774 def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;
775 // Non-IEEE MUL: 0 * anything = 0
776 def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>;
777 def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
778 def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax>;
779 def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin>;
781 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
782 // so some of the instruction names don't match the asm string.
783 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
784 def SETE : R600_2OP <
786 [(set R600_Reg32:$dst,
787 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
793 [(set R600_Reg32:$dst,
794 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
800 [(set R600_Reg32:$dst,
801 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
807 [(set R600_Reg32:$dst,
808 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
812 def SETE_DX10 : R600_2OP <
814 [(set R600_Reg32:$dst,
815 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
819 def SETGT_DX10 : R600_2OP <
821 [(set R600_Reg32:$dst,
822 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
826 def SETGE_DX10 : R600_2OP <
828 [(set R600_Reg32:$dst,
829 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
833 def SETNE_DX10 : R600_2OP <
835 [(set R600_Reg32:$dst,
836 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
840 def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;
841 def TRUNC : R600_1OP_Helper <0x11, "TRUNC", int_AMDGPU_trunc>;
842 def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
843 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
844 def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
846 def MOV : R600_1OP <0x19, "MOV", []>;
848 let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
850 class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst <
851 (outs R600_Reg32:$dst),
857 } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1
859 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
862 (MOV_IMM_I32 imm:$val)
865 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
868 (MOV_IMM_F32 fpimm:$val)
871 def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>;
872 def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>;
873 def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>;
874 def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>;
876 let hasSideEffects = 1 in {
878 def KILLGT : R600_2OP <0x2D, "KILLGT", []>;
880 } // end hasSideEffects
882 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
883 def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;
884 def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;
885 def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;
886 def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;
887 def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;
888 def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>;
889 def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>;
890 def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUumax>;
891 def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>;
893 def SETE_INT : R600_2OP <
895 [(set (i32 R600_Reg32:$dst),
896 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
899 def SETGT_INT : R600_2OP <
901 [(set (i32 R600_Reg32:$dst),
902 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
905 def SETGE_INT : R600_2OP <
907 [(set (i32 R600_Reg32:$dst),
908 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
911 def SETNE_INT : R600_2OP <
913 [(set (i32 R600_Reg32:$dst),
914 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
917 def SETGT_UINT : R600_2OP <
919 [(set (i32 R600_Reg32:$dst),
920 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
923 def SETGE_UINT : R600_2OP <
925 [(set (i32 R600_Reg32:$dst),
926 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
929 def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>;
930 def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>;
931 def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>;
932 def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>;
934 def CNDE_INT : R600_3OP <
936 [(set (i32 R600_Reg32:$dst),
937 (selectcc (i32 R600_Reg32:$src0), 0,
938 (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
942 def CNDGE_INT : R600_3OP <
944 [(set (i32 R600_Reg32:$dst),
945 (selectcc (i32 R600_Reg32:$src0), 0,
946 (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
950 def CNDGT_INT : R600_3OP <
952 [(set (i32 R600_Reg32:$dst),
953 (selectcc (i32 R600_Reg32:$src0), 0,
954 (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
958 //===----------------------------------------------------------------------===//
959 // Texture instructions
960 //===----------------------------------------------------------------------===//
962 def TEX_LD : R600_TEX <
964 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txf R600_Reg128:$SRC_GPR,
965 imm:$OFFSET_X, imm:$OFFSET_Y, imm:$OFFSET_Z, imm:$RESOURCE_ID,
966 imm:$SAMPLER_ID, imm:$textureTarget))]
968 let AsmString = "TEX_LD $DST_GPR, $SRC_GPR, $OFFSET_X, $OFFSET_Y, $OFFSET_Z,"
969 "$RESOURCE_ID, $SAMPLER_ID, $textureTarget";
970 let InOperandList = (ins R600_Reg128:$SRC_GPR, i32imm:$OFFSET_X,
971 i32imm:$OFFSET_Y, i32imm:$OFFSET_Z, i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID,
972 i32imm:$textureTarget);
975 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
976 0x04, "TEX_GET_TEXTURE_RESINFO",
977 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txq R600_Reg128:$SRC_GPR,
978 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
981 def TEX_GET_GRADIENTS_H : R600_TEX <
982 0x07, "TEX_GET_GRADIENTS_H",
983 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_ddx R600_Reg128:$SRC_GPR,
984 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
987 def TEX_GET_GRADIENTS_V : R600_TEX <
988 0x08, "TEX_GET_GRADIENTS_V",
989 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_ddy R600_Reg128:$SRC_GPR,
990 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
993 def TEX_SET_GRADIENTS_H : R600_TEX <
994 0x0B, "TEX_SET_GRADIENTS_H",
998 def TEX_SET_GRADIENTS_V : R600_TEX <
999 0x0C, "TEX_SET_GRADIENTS_V",
1003 def TEX_SAMPLE : R600_TEX <
1005 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_tex R600_Reg128:$SRC_GPR,
1006 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1009 def TEX_SAMPLE_C : R600_TEX <
1010 0x18, "TEX_SAMPLE_C",
1011 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_tex R600_Reg128:$SRC_GPR,
1012 imm:$RESOURCE_ID, imm:$SAMPLER_ID, TEX_SHADOW:$textureTarget))]
1015 def TEX_SAMPLE_L : R600_TEX <
1016 0x11, "TEX_SAMPLE_L",
1017 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txl R600_Reg128:$SRC_GPR,
1018 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1021 def TEX_SAMPLE_C_L : R600_TEX <
1022 0x19, "TEX_SAMPLE_C_L",
1023 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txl R600_Reg128:$SRC_GPR,
1024 imm:$RESOURCE_ID, imm:$SAMPLER_ID, TEX_SHADOW:$textureTarget))]
1027 def TEX_SAMPLE_LB : R600_TEX <
1028 0x12, "TEX_SAMPLE_LB",
1029 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txb R600_Reg128:$SRC_GPR,
1030 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1033 def TEX_SAMPLE_C_LB : R600_TEX <
1034 0x1A, "TEX_SAMPLE_C_LB",
1035 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txb R600_Reg128:$SRC_GPR,
1036 imm:$RESOURCE_ID, imm:$SAMPLER_ID, TEX_SHADOW:$textureTarget))]
1039 def TEX_SAMPLE_G : R600_TEX <
1040 0x14, "TEX_SAMPLE_G",
1044 def TEX_SAMPLE_C_G : R600_TEX <
1045 0x1C, "TEX_SAMPLE_C_G",
1049 //===----------------------------------------------------------------------===//
1050 // Helper classes for common instructions
1051 //===----------------------------------------------------------------------===//
1053 class MUL_LIT_Common <bits<5> inst> : R600_3OP <
1058 class MULADD_Common <bits<5> inst> : R600_3OP <
1063 class MULADD_IEEE_Common <bits<5> inst> : R600_3OP <
1064 inst, "MULADD_IEEE",
1065 [(set (f32 R600_Reg32:$dst),
1066 (fadd (fmul R600_Reg32:$src0, R600_Reg32:$src1), R600_Reg32:$src2))]
1069 class CNDE_Common <bits<5> inst> : R600_3OP <
1071 [(set R600_Reg32:$dst,
1072 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
1073 (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
1077 class CNDGT_Common <bits<5> inst> : R600_3OP <
1079 [(set R600_Reg32:$dst,
1080 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
1081 (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
1085 class CNDGE_Common <bits<5> inst> : R600_3OP <
1087 [(set R600_Reg32:$dst,
1088 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
1089 (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
1093 multiclass DOT4_Common <bits<11> inst> {
1095 def _pseudo : R600_REDUCTION <inst,
1096 (ins R600_Reg128:$src0, R600_Reg128:$src1),
1097 "DOT4 $dst $src0, $src1",
1098 [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
1101 def _real : R600_2OP <inst, "DOT4", []>;
1104 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
1105 multiclass CUBE_Common <bits<11> inst> {
1107 def _pseudo : InstR600 <
1109 (outs R600_Reg128:$dst),
1110 (ins R600_Reg128:$src),
1112 [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
1118 def _real : R600_2OP <inst, "CUBE", []>;
1120 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
1122 class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1123 inst, "EXP_IEEE", fexp2
1126 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper <
1127 inst, "FLT_TO_INT", fp_to_sint
1130 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1131 inst, "INT_TO_FLT", sint_to_fp
1134 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1135 inst, "FLT_TO_UINT", fp_to_uint
1138 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1139 inst, "UINT_TO_FLT", uint_to_fp
1142 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
1143 inst, "LOG_CLAMPED", []
1146 class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1147 inst, "LOG_IEEE", flog2
1150 class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;
1151 class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;
1152 class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;
1153 class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <
1154 inst, "MULHI_INT", mulhs
1156 class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <
1157 inst, "MULHI", mulhu
1159 class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <
1160 inst, "MULLO_INT", mul
1162 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []>;
1164 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
1165 inst, "RECIP_CLAMPED", []
1168 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
1169 inst, "RECIP_IEEE", [(set R600_Reg32:$dst, (fdiv FP_ONE, R600_Reg32:$src0))]
1172 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1173 inst, "RECIP_UINT", AMDGPUurecip
1176 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <
1177 inst, "RECIPSQRT_CLAMPED", int_AMDGPU_rsq
1180 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP <
1181 inst, "RECIPSQRT_IEEE", []
1184 class SIN_Common <bits<11> inst> : R600_1OP <
1189 class COS_Common <bits<11> inst> : R600_1OP <
1194 //===----------------------------------------------------------------------===//
1195 // Helper patterns for complex intrinsics
1196 //===----------------------------------------------------------------------===//
1198 multiclass DIV_Common <InstR600 recip_ieee> {
1200 (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
1201 (MUL_IEEE R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
1205 (fdiv R600_Reg32:$src0, R600_Reg32:$src1),
1206 (MUL_IEEE R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
1210 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
1211 (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
1212 (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
1215 //===----------------------------------------------------------------------===//
1216 // R600 / R700 Instructions
1217 //===----------------------------------------------------------------------===//
1219 let Predicates = [isR600] in {
1221 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
1222 def MULADD_r600 : MULADD_Common<0x10>;
1223 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>;
1224 def CNDE_r600 : CNDE_Common<0x18>;
1225 def CNDGT_r600 : CNDGT_Common<0x19>;
1226 def CNDGE_r600 : CNDGE_Common<0x1A>;
1227 defm DOT4_r600 : DOT4_Common<0x50>;
1228 defm CUBE_r600 : CUBE_Common<0x52>;
1229 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
1230 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
1231 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
1232 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
1233 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
1234 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
1235 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
1236 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
1237 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
1238 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
1239 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
1240 def SIN_r600 : SIN_Common<0x6E>;
1241 def COS_r600 : COS_Common<0x6F>;
1242 def ASHR_r600 : ASHR_Common<0x70>;
1243 def LSHR_r600 : LSHR_Common<0x71>;
1244 def LSHL_r600 : LSHL_Common<0x72>;
1245 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
1246 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
1247 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
1248 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
1249 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
1251 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
1252 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL, R600_Reg32>;
1253 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
1255 def : Pat<(fsqrt R600_Reg32:$src),
1256 (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_r600 R600_Reg32:$src))>;
1258 def R600_ExportSwz : ExportSwzInst {
1259 let Word1{20-17} = 1; // BURST_COUNT
1260 let Word1{21} = eop;
1261 let Word1{22} = 1; // VALID_PIXEL_MODE
1262 let Word1{30-23} = inst;
1263 let Word1{31} = 1; // BARRIER
1265 defm : ExportPattern<R600_ExportSwz, 39>;
1267 def R600_ExportBuf : ExportBufInst {
1268 let Word1{20-17} = 1; // BURST_COUNT
1269 let Word1{21} = eop;
1270 let Word1{22} = 1; // VALID_PIXEL_MODE
1271 let Word1{30-23} = inst;
1272 let Word1{31} = 1; // BARRIER
1274 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>;
1277 // Helper pattern for normalizing inputs to triginomic instructions for R700+
1279 class COS_PAT <InstR600 trig> : Pat<
1280 (fcos R600_Reg32:$src),
1281 (trig (MUL_IEEE (MOV_IMM_I32 CONST.TWO_PI_INV), R600_Reg32:$src))
1284 class SIN_PAT <InstR600 trig> : Pat<
1285 (fsin R600_Reg32:$src),
1286 (trig (MUL_IEEE (MOV_IMM_I32 CONST.TWO_PI_INV), R600_Reg32:$src))
1289 //===----------------------------------------------------------------------===//
1290 // R700 Only instructions
1291 //===----------------------------------------------------------------------===//
1293 let Predicates = [isR700] in {
1294 def SIN_r700 : SIN_Common<0x6E>;
1295 def COS_r700 : COS_Common<0x6F>;
1297 // R700 normalizes inputs to SIN/COS the same as EG
1298 def : SIN_PAT <SIN_r700>;
1299 def : COS_PAT <COS_r700>;
1302 //===----------------------------------------------------------------------===//
1303 // Evergreen Only instructions
1304 //===----------------------------------------------------------------------===//
1306 let Predicates = [isEG] in {
1308 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
1309 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
1311 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
1312 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
1313 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
1314 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
1315 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
1316 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
1317 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
1318 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
1319 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
1320 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
1321 def SIN_eg : SIN_Common<0x8D>;
1322 def COS_eg : COS_Common<0x8E>;
1324 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL, R600_Reg32>;
1325 def : SIN_PAT <SIN_eg>;
1326 def : COS_PAT <COS_eg>;
1327 def : Pat<(fsqrt R600_Reg32:$src),
1328 (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_eg R600_Reg32:$src))>;
1329 } // End Predicates = [isEG]
1331 //===----------------------------------------------------------------------===//
1332 // Evergreen / Cayman Instructions
1333 //===----------------------------------------------------------------------===//
1335 let Predicates = [isEGorCayman] in {
1337 // BFE_UINT - bit_extract, an optimization for mask and shift
1342 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
1347 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
1348 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
1349 // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
1350 // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
1351 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
1352 [(set R600_Reg32:$dst, (int_AMDIL_bit_extract_u32 R600_Reg32:$src0,
1354 R600_Reg32:$src2))],
1358 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT",
1359 [(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1,
1360 R600_Reg32:$src2))],
1364 def MULADD_eg : MULADD_Common<0x14>;
1365 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
1366 def ASHR_eg : ASHR_Common<0x15>;
1367 def LSHR_eg : LSHR_Common<0x16>;
1368 def LSHL_eg : LSHL_Common<0x17>;
1369 def CNDE_eg : CNDE_Common<0x19>;
1370 def CNDGT_eg : CNDGT_Common<0x1A>;
1371 def CNDGE_eg : CNDGE_Common<0x1B>;
1372 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
1373 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
1374 defm DOT4_eg : DOT4_Common<0xBE>;
1375 defm CUBE_eg : CUBE_Common<0xC0>;
1377 let hasSideEffects = 1 in {
1378 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", []>;
1381 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
1383 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
1387 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
1389 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
1393 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
1395 // TRUNC is used for the FLT_TO_INT instructions to work around a
1396 // perceived problem where the rounding modes are applied differently
1397 // depending on the instruction and the slot they are in.
1399 // https://bugs.freedesktop.org/show_bug.cgi?id=50232
1400 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
1402 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
1403 // which do not need to be truncated since the fp values are 0.0f or 1.0f.
1404 // We should look into handling these cases separately.
1405 def : Pat<(fp_to_sint R600_Reg32:$src0),
1406 (FLT_TO_INT_eg (TRUNC R600_Reg32:$src0))>;
1408 def : Pat<(fp_to_uint R600_Reg32:$src0),
1409 (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src0))>;
1411 def EG_ExportSwz : ExportSwzInst {
1412 let Word1{19-16} = 1; // BURST_COUNT
1413 let Word1{20} = 1; // VALID_PIXEL_MODE
1414 let Word1{21} = eop;
1415 let Word1{29-22} = inst;
1416 let Word1{30} = 0; // MARK
1417 let Word1{31} = 1; // BARRIER
1419 defm : ExportPattern<EG_ExportSwz, 83>;
1421 def EG_ExportBuf : ExportBufInst {
1422 let Word1{19-16} = 1; // BURST_COUNT
1423 let Word1{20} = 1; // VALID_PIXEL_MODE
1424 let Word1{21} = eop;
1425 let Word1{29-22} = inst;
1426 let Word1{30} = 0; // MARK
1427 let Word1{31} = 1; // BARRIER
1429 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
1431 //===----------------------------------------------------------------------===//
1432 // Memory read/write instructions
1433 //===----------------------------------------------------------------------===//
1434 let usesCustomInserter = 1 in {
1436 class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> comp_mask, string name,
1438 : EG_CF_RAT <0x57, 0x2, 0, (outs), ins,
1439 !strconcat(name, " $rw_gpr, $index_gpr, $eop"), pattern> {
1441 // XXX: Have a separate instruction for non-indexed writes.
1447 let COMP_MASK = comp_mask;
1448 let BURST_COUNT = 0;
1454 } // End usesCustomInserter = 1
1457 def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
1458 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1459 0x1, "RAT_WRITE_CACHELESS_32_eg",
1460 [(global_store (i32 R600_TReg32_X:$rw_gpr), R600_TReg32_X:$index_gpr)]
1464 def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
1465 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1466 0xf, "RAT_WRITE_CACHELESS_128",
1467 [(global_store (v4i32 R600_Reg128:$rw_gpr), R600_TReg32_X:$index_gpr)]
1470 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
1471 : InstR600ISA <outs, (ins MEMxi:$ptr), name#" $dst, $ptr", pattern>,
1472 VTX_WORD1_GPR, VTX_WORD0 {
1477 let FETCH_WHOLE_QUAD = 0;
1478 let BUFFER_ID = buffer_id;
1480 // XXX: We can infer this field based on the SRC_GPR. This would allow us
1481 // to store vertex addresses in any channel, not just X.
1484 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
1485 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
1486 // however, based on my testing if USE_CONST_FIELDS is set, then all
1487 // these fields need to be set to 0.
1488 let USE_CONST_FIELDS = 0;
1489 let NUM_FORMAT_ALL = 1;
1490 let FORMAT_COMP_ALL = 0;
1491 let SRF_MODE_ALL = 0;
1493 let Inst{31-0} = Word0;
1494 let Inst{63-32} = Word1;
1495 // LLVM can only encode 64-bit instructions, so these fields are manually
1496 // encoded in R600CodeEmitter
1499 // bits<2> ENDIAN_SWAP = 0;
1500 // bits<1> CONST_BUF_NO_STRIDE = 0;
1501 // bits<1> MEGA_FETCH = 0;
1502 // bits<1> ALT_CONST = 0;
1503 // bits<2> BUFFER_INDEX_MODE = 0;
1507 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1508 // is done in R600CodeEmitter
1510 // Inst{79-64} = OFFSET;
1511 // Inst{81-80} = ENDIAN_SWAP;
1512 // Inst{82} = CONST_BUF_NO_STRIDE;
1513 // Inst{83} = MEGA_FETCH;
1514 // Inst{84} = ALT_CONST;
1515 // Inst{86-85} = BUFFER_INDEX_MODE;
1516 // Inst{95-86} = 0; Reserved
1518 // VTX_WORD3 (Padding)
1520 // Inst{127-96} = 0;
1523 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
1524 : VTX_READ_eg <"VTX_READ_8", buffer_id, (outs R600_TReg32_X:$dst),
1527 let MEGA_FETCH_COUNT = 1;
1529 let DST_SEL_Y = 7; // Masked
1530 let DST_SEL_Z = 7; // Masked
1531 let DST_SEL_W = 7; // Masked
1532 let DATA_FORMAT = 1; // FMT_8
1535 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
1536 : VTX_READ_eg <"VTX_READ_16", buffer_id, (outs R600_TReg32_X:$dst),
1538 let MEGA_FETCH_COUNT = 2;
1540 let DST_SEL_Y = 7; // Masked
1541 let DST_SEL_Z = 7; // Masked
1542 let DST_SEL_W = 7; // Masked
1543 let DATA_FORMAT = 5; // FMT_16
1547 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
1548 : VTX_READ_eg <"VTX_READ_32", buffer_id, (outs R600_TReg32_X:$dst),
1551 let MEGA_FETCH_COUNT = 4;
1553 let DST_SEL_Y = 7; // Masked
1554 let DST_SEL_Z = 7; // Masked
1555 let DST_SEL_W = 7; // Masked
1556 let DATA_FORMAT = 0xD; // COLOR_32
1558 // This is not really necessary, but there were some GPU hangs that appeared
1559 // to be caused by ALU instructions in the next instruction group that wrote
1560 // to the $ptr registers of the VTX_READ.
1562 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
1563 // %T2_X<def> = MOV %ZERO
1564 //Adding this constraint prevents this from happening.
1565 let Constraints = "$ptr.ptr = $dst";
1568 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
1569 : VTX_READ_eg <"VTX_READ_128", buffer_id, (outs R600_Reg128:$dst),
1572 let MEGA_FETCH_COUNT = 16;
1577 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1579 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1580 // that holds its buffer address to avoid potential hangs. We can't use
1581 // the same constraint as VTX_READ_32_eg, because the $ptr.ptr and $dst
1582 // registers are different sizes.
1585 //===----------------------------------------------------------------------===//
1586 // VTX Read from parameter memory space
1587 //===----------------------------------------------------------------------===//
1589 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0,
1590 [(set (i32 R600_TReg32_X:$dst), (load_param_zexti8 ADDRVTX_READ:$ptr))]
1593 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0,
1594 [(set (i32 R600_TReg32_X:$dst), (load_param_zexti16 ADDRVTX_READ:$ptr))]
1597 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0,
1598 [(set (i32 R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))]
1601 def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0,
1602 [(set (v4i32 R600_Reg128:$dst), (load_param ADDRVTX_READ:$ptr))]
1605 //===----------------------------------------------------------------------===//
1606 // VTX Read from global memory space
1607 //===----------------------------------------------------------------------===//
1610 def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1,
1611 [(set (i32 R600_TReg32_X:$dst), (zextloadi8_global ADDRVTX_READ:$ptr))]
1615 def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1,
1616 [(set (i32 R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))]
1620 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
1621 [(set (v4i32 R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))]
1624 //===----------------------------------------------------------------------===//
1626 // XXX: We are currently storing all constants in the global address space.
1627 //===----------------------------------------------------------------------===//
1629 def CONSTANT_LOAD_eg : VTX_READ_32_eg <1,
1630 [(set (i32 R600_TReg32_X:$dst), (constant_load ADDRVTX_READ:$ptr))]
1635 //===----------------------------------------------------------------------===//
1636 // Regist loads and stores - for indirect addressing
1637 //===----------------------------------------------------------------------===//
1639 defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;
1641 let Predicates = [isCayman] in {
1643 let isVector = 1 in {
1645 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
1647 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
1648 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
1649 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
1650 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
1651 def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
1652 def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
1653 def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;
1654 def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
1655 def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
1656 def SIN_cm : SIN_Common<0x8D>;
1657 def COS_cm : COS_Common<0x8E>;
1658 } // End isVector = 1
1660 def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL, R600_Reg32>;
1661 def : SIN_PAT <SIN_cm>;
1662 def : COS_PAT <COS_cm>;
1664 defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
1666 // RECIP_UINT emulation for Cayman
1668 (AMDGPUurecip R600_Reg32:$src0),
1669 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)),
1670 (MOV_IMM_I32 0x4f800000)))
1674 def : Pat<(fsqrt R600_Reg32:$src),
1675 (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm R600_Reg32:$src))>;
1679 //===----------------------------------------------------------------------===//
1680 // Branch Instructions
1681 //===----------------------------------------------------------------------===//
1684 def IF_PREDICATE_SET : ILFormat<(outs), (ins GPRI32:$src),
1685 "IF_PREDICATE_SET $src", []>;
1687 def PREDICATED_BREAK : ILFormat<(outs), (ins GPRI32:$src),
1688 "PREDICATED_BREAK $src", []>;
1690 //===----------------------------------------------------------------------===//
1691 // Pseudo instructions
1692 //===----------------------------------------------------------------------===//
1694 let isPseudo = 1 in {
1696 def PRED_X : InstR600 <
1697 0, (outs R600_Predicate_Bit:$dst),
1698 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
1700 let FlagOperandIdx = 3;
1703 let isTerminator = 1, isBranch = 1 in {
1704 def JUMP_COND : InstR600 <0x10,
1706 (ins brtarget:$target, R600_Predicate_Bit:$p),
1707 "JUMP $target ($p)",
1711 def JUMP : InstR600 <0x10,
1713 (ins brtarget:$target),
1718 let isPredicable = 1;
1722 } // End isTerminator = 1, isBranch = 1
1724 let usesCustomInserter = 1 in {
1726 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
1728 def MASK_WRITE : AMDGPUShaderInst <
1730 (ins R600_Reg32:$src),
1735 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
1738 def TXD: AMDGPUShaderInst <
1739 (outs R600_Reg128:$dst),
1740 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1741 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1742 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
1745 def TXD_SHADOW: AMDGPUShaderInst <
1746 (outs R600_Reg128:$dst),
1747 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1748 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1749 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))]
1752 } // End isPseudo = 1
1753 } // End usesCustomInserter = 1
1755 def CLAMP_R600 : CLAMP <R600_Reg32>;
1756 def FABS_R600 : FABS<R600_Reg32>;
1757 def FNEG_R600 : FNEG<R600_Reg32>;
1759 //===---------------------------------------------------------------------===//
1760 // Return instruction
1761 //===---------------------------------------------------------------------===//
1762 let isTerminator = 1, isReturn = 1, hasCtrlDep = 1,
1763 usesCustomInserter = 1 in {
1764 def RETURN : ILFormat<(outs), (ins variable_ops),
1765 "RETURN", [(IL_retflag)]>;
1769 //===----------------------------------------------------------------------===//
1770 // Constant Buffer Addressing Support
1771 //===----------------------------------------------------------------------===//
1773 let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
1774 def CONST_COPY : Instruction {
1775 let OutOperandList = (outs R600_Reg32:$dst);
1776 let InOperandList = (ins i32imm:$src);
1778 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
1779 let AsmString = "CONST_COPY";
1780 let neverHasSideEffects = 1;
1781 let isAsCheapAsAMove = 1;
1782 let Itinerary = NullALU;
1784 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
1786 def TEX_VTX_CONSTBUF :
1787 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "VTX_READ_eg $dst, $ptr",
1788 [(set R600_Reg128:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$BUFFER_ID)))]>,
1789 VTX_WORD1_GPR, VTX_WORD0 {
1793 let FETCH_WHOLE_QUAD = 0;
1797 let USE_CONST_FIELDS = 0;
1798 let NUM_FORMAT_ALL = 2;
1799 let FORMAT_COMP_ALL = 1;
1800 let SRF_MODE_ALL = 1;
1801 let MEGA_FETCH_COUNT = 16;
1806 let DATA_FORMAT = 35;
1808 let Inst{31-0} = Word0;
1809 let Inst{63-32} = Word1;
1811 // LLVM can only encode 64-bit instructions, so these fields are manually
1812 // encoded in R600CodeEmitter
1815 // bits<2> ENDIAN_SWAP = 0;
1816 // bits<1> CONST_BUF_NO_STRIDE = 0;
1817 // bits<1> MEGA_FETCH = 0;
1818 // bits<1> ALT_CONST = 0;
1819 // bits<2> BUFFER_INDEX_MODE = 0;
1823 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1824 // is done in R600CodeEmitter
1826 // Inst{79-64} = OFFSET;
1827 // Inst{81-80} = ENDIAN_SWAP;
1828 // Inst{82} = CONST_BUF_NO_STRIDE;
1829 // Inst{83} = MEGA_FETCH;
1830 // Inst{84} = ALT_CONST;
1831 // Inst{86-85} = BUFFER_INDEX_MODE;
1832 // Inst{95-86} = 0; Reserved
1834 // VTX_WORD3 (Padding)
1836 // Inst{127-96} = 0;
1840 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr",
1841 [(set R600_Reg128:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>,
1842 VTX_WORD1_GPR, VTX_WORD0 {
1846 let FETCH_WHOLE_QUAD = 0;
1850 let USE_CONST_FIELDS = 1;
1851 let NUM_FORMAT_ALL = 0;
1852 let FORMAT_COMP_ALL = 0;
1853 let SRF_MODE_ALL = 1;
1854 let MEGA_FETCH_COUNT = 16;
1859 let DATA_FORMAT = 0;
1861 let Inst{31-0} = Word0;
1862 let Inst{63-32} = Word1;
1864 // LLVM can only encode 64-bit instructions, so these fields are manually
1865 // encoded in R600CodeEmitter
1868 // bits<2> ENDIAN_SWAP = 0;
1869 // bits<1> CONST_BUF_NO_STRIDE = 0;
1870 // bits<1> MEGA_FETCH = 0;
1871 // bits<1> ALT_CONST = 0;
1872 // bits<2> BUFFER_INDEX_MODE = 0;
1876 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1877 // is done in R600CodeEmitter
1879 // Inst{79-64} = OFFSET;
1880 // Inst{81-80} = ENDIAN_SWAP;
1881 // Inst{82} = CONST_BUF_NO_STRIDE;
1882 // Inst{83} = MEGA_FETCH;
1883 // Inst{84} = ALT_CONST;
1884 // Inst{86-85} = BUFFER_INDEX_MODE;
1885 // Inst{95-86} = 0; Reserved
1887 // VTX_WORD3 (Padding)
1889 // Inst{127-96} = 0;
1894 //===--------------------------------------------------------------------===//
1895 // Instructions support
1896 //===--------------------------------------------------------------------===//
1897 //===---------------------------------------------------------------------===//
1898 // Custom Inserter for Branches and returns, this eventually will be a
1900 //===---------------------------------------------------------------------===//
1901 let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
1902 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
1903 "; Pseudo unconditional branch instruction",
1905 defm BRANCH_COND : BranchConditional<IL_brcond>;
1908 //===---------------------------------------------------------------------===//
1909 // Flow and Program control Instructions
1910 //===---------------------------------------------------------------------===//
1911 let isTerminator=1 in {
1912 def SWITCH : ILFormat< (outs), (ins GPRI32:$src),
1913 !strconcat("SWITCH", " $src"), []>;
1914 def CASE : ILFormat< (outs), (ins GPRI32:$src),
1915 !strconcat("CASE", " $src"), []>;
1916 def BREAK : ILFormat< (outs), (ins),
1918 def CONTINUE : ILFormat< (outs), (ins),
1920 def DEFAULT : ILFormat< (outs), (ins),
1922 def ELSE : ILFormat< (outs), (ins),
1924 def ENDSWITCH : ILFormat< (outs), (ins),
1926 def ENDMAIN : ILFormat< (outs), (ins),
1928 def END : ILFormat< (outs), (ins),
1930 def ENDFUNC : ILFormat< (outs), (ins),
1932 def ENDIF : ILFormat< (outs), (ins),
1934 def WHILELOOP : ILFormat< (outs), (ins),
1936 def ENDLOOP : ILFormat< (outs), (ins),
1938 def FUNC : ILFormat< (outs), (ins),
1940 def RETDYN : ILFormat< (outs), (ins),
1942 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1943 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">;
1944 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1945 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">;
1946 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1947 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">;
1948 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1949 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">;
1950 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1951 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">;
1952 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1953 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">;
1954 defm IFC : BranchInstr2<"IFC">;
1955 defm BREAKC : BranchInstr2<"BREAKC">;
1956 defm CONTINUEC : BranchInstr2<"CONTINUEC">;
1959 //===----------------------------------------------------------------------===//
1961 //===----------------------------------------------------------------------===//
1963 // CND*_INT Pattterns for f32 True / False values
1965 class CND_INT_f32 <InstR600 cnd, CondCode cc> : Pat <
1966 (selectcc (i32 R600_Reg32:$src0), 0, (f32 R600_Reg32:$src1),
1967 R600_Reg32:$src2, cc),
1968 (cnd R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2)
1971 def : CND_INT_f32 <CNDE_INT, SETEQ>;
1972 def : CND_INT_f32 <CNDGT_INT, SETGT>;
1973 def : CND_INT_f32 <CNDGE_INT, SETGE>;
1975 //CNDGE_INT extra pattern
1977 (selectcc (i32 R600_Reg32:$src0), -1, (i32 R600_Reg32:$src1),
1978 (i32 R600_Reg32:$src2), COND_GT),
1979 (CNDGE_INT R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2)
1985 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
1989 (int_AMDGPU_kill R600_Reg32:$src0),
1990 (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
1995 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT),
1996 (SGT R600_Reg32:$src1, R600_Reg32:$src0)
2001 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE),
2002 (SGE R600_Reg32:$src1, R600_Reg32:$src0)
2005 // SETGT_DX10 reverse args
2007 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, COND_LT),
2008 (SETGT_DX10 R600_Reg32:$src1, R600_Reg32:$src0)
2011 // SETGE_DX10 reverse args
2013 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, COND_LE),
2014 (SETGE_DX10 R600_Reg32:$src1, R600_Reg32:$src0)
2017 // SETGT_INT reverse args
2019 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
2020 (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0)
2023 // SETGE_INT reverse args
2025 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE),
2026 (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0)
2029 // SETGT_UINT reverse args
2031 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
2032 (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0)
2035 // SETGE_UINT reverse args
2037 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE),
2038 (SETGE_UINT R600_Reg32:$src1, R600_Reg32:$src0)
2041 // The next two patterns are special cases for handling 'true if ordered' and
2042 // 'true if unordered' conditionals. The assumption here is that the behavior of
2043 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
2045 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
2046 // We assume that SETE returns false when one of the operands is NAN and
2047 // SNE returns true when on of the operands is NAN
2049 //SETE - 'true if ordered'
2051 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
2052 (SETE R600_Reg32:$src0, R600_Reg32:$src1)
2055 //SETE_DX10 - 'true if ordered'
2057 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETO),
2058 (SETE_DX10 R600_Reg32:$src0, R600_Reg32:$src1)
2061 //SNE - 'true if unordered'
2063 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO),
2064 (SNE R600_Reg32:$src0, R600_Reg32:$src1)
2067 //SETNE_DX10 - 'true if ordered'
2069 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUO),
2070 (SETNE_DX10 R600_Reg32:$src0, R600_Reg32:$src1)
2073 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sub0>;
2074 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sub1>;
2075 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sub2>;
2076 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sub3>;
2078 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 0, sub0>;
2079 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 1, sub1>;
2080 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 2, sub2>;
2081 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 3, sub3>;
2083 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sub0>;
2084 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sub1>;
2085 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sub2>;
2086 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sub3>;
2088 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 0, sub0>;
2089 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 1, sub1>;
2090 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 2, sub2>;
2091 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 3, sub3>;
2093 def : Vector4_Build <v4f32, R600_Reg128, f32, R600_Reg32>;
2094 def : Vector4_Build <v4i32, R600_Reg128, i32, R600_Reg32>;
2096 // bitconvert patterns
2098 def : BitConvert <i32, f32, R600_Reg32>;
2099 def : BitConvert <f32, i32, R600_Reg32>;
2100 def : BitConvert <v4f32, v4i32, R600_Reg128>;
2101 def : BitConvert <v4i32, v4f32, R600_Reg128>;
2103 // DWORDADDR pattern
2104 def : DwordAddrPat <i32, R600_Reg32>;
2106 } // End isR600toCayman Predicate