1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // R600 Tablegen instruction definitions
12 //===----------------------------------------------------------------------===//
14 include "R600Intrinsics.td"
15 include "R600InstrFormats.td"
17 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
18 InstR600 <outs, ins, asm, pattern, NullALU> {
20 let Namespace = "AMDGPU";
23 def MEMxi : Operand<iPTR> {
24 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
25 let PrintMethod = "printMemOperand";
28 def MEMrr : Operand<iPTR> {
29 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
32 // Operands for non-registers
34 class InstFlag<string PM = "printOperand", int Default = 0>
35 : OperandWithDefaultOps <i32, (ops (i32 Default))> {
39 // src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
40 def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
41 let PrintMethod = "printSel";
43 def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> {
44 let PrintMethod = "printBankSwizzle";
47 def LITERAL : InstFlag<"printLiteral">;
49 def WRITE : InstFlag <"printWrite", 1>;
50 def OMOD : InstFlag <"printOMOD">;
51 def REL : InstFlag <"printRel">;
52 def CLAMP : InstFlag <"printClamp">;
53 def NEG : InstFlag <"printNeg">;
54 def ABS : InstFlag <"printAbs">;
55 def UEM : InstFlag <"printUpdateExecMask">;
56 def UP : InstFlag <"printUpdatePred">;
58 // XXX: The r600g finalizer in Mesa expects last to be one in most cases.
59 // Once we start using the packetizer in this backend we should have this
61 def LAST : InstFlag<"printLast", 1>;
62 def RSel : Operand<i32> {
63 let PrintMethod = "printRSel";
65 def CT: Operand<i32> {
66 let PrintMethod = "printCT";
69 def FRAMEri : Operand<iPTR> {
70 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index);
73 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
74 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
75 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
76 def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;
77 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
78 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
81 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
85 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
87 // Class for instructions with only one source register.
88 // If you add new ins to this instruction, make sure they are listed before
89 // $literal, because the backend currently assumes that the last operand is
90 // a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in
91 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(),
92 // and R600InstrInfo::getOperandIdx().
93 class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
94 InstrItinClass itin = AnyALU> :
95 InstR600 <(outs R600_Reg32:$dst),
96 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
97 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
98 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
99 BANK_SWIZZLE:$bank_swizzle),
100 !strconcat(" ", opName,
101 "$clamp $last $dst$write$dst_rel$omod, "
102 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
103 "$pred_sel $bank_swizzle"),
107 R600ALU_Word1_OP2 <inst> {
113 let update_exec_mask = 0;
115 let HasNativeOperands = 1;
118 let DisableEncoding = "$literal";
119 let UseNamedOperandTable = 1;
121 let Inst{31-0} = Word0;
122 let Inst{63-32} = Word1;
125 class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
126 InstrItinClass itin = AnyALU> :
127 R600_1OP <inst, opName,
128 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))]
131 // If you add or change the operands for R600_2OP instructions, you must
132 // also update the R600Op2OperandIndex::ROI enum in R600Defines.h,
133 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
134 class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
135 InstrItinClass itin = AnyALU> :
136 InstR600 <(outs R600_Reg32:$dst),
137 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
138 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
139 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
140 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
141 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
142 BANK_SWIZZLE:$bank_swizzle),
143 !strconcat(" ", opName,
144 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
145 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
146 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
147 "$pred_sel $bank_swizzle"),
151 R600ALU_Word1_OP2 <inst> {
153 let HasNativeOperands = 1;
156 let DisableEncoding = "$literal";
157 let UseNamedOperandTable = 1;
159 let Inst{31-0} = Word0;
160 let Inst{63-32} = Word1;
163 class R600_2OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
164 InstrItinClass itim = AnyALU> :
165 R600_2OP <inst, opName,
166 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
170 // If you add our change the operands for R600_3OP instructions, you must
171 // also update the R600Op3OperandIndex::ROI enum in R600Defines.h,
172 // R600InstrInfo::buildDefaultInstruction(), and
173 // R600InstrInfo::getOperandIdx().
174 class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
175 InstrItinClass itin = AnyALU> :
176 InstR600 <(outs R600_Reg32:$dst),
177 (ins REL:$dst_rel, CLAMP:$clamp,
178 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
179 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
180 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
181 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
182 BANK_SWIZZLE:$bank_swizzle),
183 !strconcat(" ", opName, "$clamp $last $dst$dst_rel, "
184 "$src0_neg$src0$src0_rel, "
185 "$src1_neg$src1$src1_rel, "
186 "$src2_neg$src2$src2_rel, "
192 R600ALU_Word1_OP3<inst>{
194 let HasNativeOperands = 1;
195 let DisableEncoding = "$literal";
197 let UseNamedOperandTable = 1;
200 let Inst{31-0} = Word0;
201 let Inst{63-32} = Word1;
204 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
205 InstrItinClass itin = VecALU> :
206 InstR600 <(outs R600_Reg32:$dst),
214 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
216 def TEX_SHADOW : PatLeaf<
218 [{uint32_t TType = (uint32_t)N->getZExtValue();
219 return (TType >= 6 && TType <= 8) || (TType >= 11 && TType <= 13);
223 def TEX_RECT : PatLeaf<
225 [{uint32_t TType = (uint32_t)N->getZExtValue();
230 def TEX_ARRAY : PatLeaf<
232 [{uint32_t TType = (uint32_t)N->getZExtValue();
233 return TType == 9 || TType == 10 || TType == 16;
237 def TEX_SHADOW_ARRAY : PatLeaf<
239 [{uint32_t TType = (uint32_t)N->getZExtValue();
240 return TType == 11 || TType == 12 || TType == 17;
244 def TEX_MSAA : PatLeaf<
246 [{uint32_t TType = (uint32_t)N->getZExtValue();
251 def TEX_ARRAY_MSAA : PatLeaf<
253 [{uint32_t TType = (uint32_t)N->getZExtValue();
258 class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> ratid, bits<4> mask,
259 dag outs, dag ins, string asm, list<dag> pattern> :
260 InstR600ISA <outs, ins, asm, pattern>,
261 CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF {
264 let rat_inst = ratinst;
266 // XXX: Have a separate instruction for non-indexed writes.
272 let comp_mask = mask;
275 let cf_inst = cfinst;
279 let Inst{31-0} = Word0;
280 let Inst{63-32} = Word1;
285 class VTX_READ <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
286 : InstR600ISA <outs, (ins MEMxi:$src_gpr), name, pattern>,
291 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
292 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
293 // however, based on my testing if USE_CONST_FIELDS is set, then all
294 // these fields need to be set to 0.
295 let USE_CONST_FIELDS = 0;
296 let NUM_FORMAT_ALL = 1;
297 let FORMAT_COMP_ALL = 0;
298 let SRF_MODE_ALL = 0;
300 let Inst{63-32} = Word1;
301 // LLVM can only encode 64-bit instructions, so these fields are manually
302 // encoded in R600CodeEmitter
305 // bits<2> ENDIAN_SWAP = 0;
306 // bits<1> CONST_BUF_NO_STRIDE = 0;
307 // bits<1> MEGA_FETCH = 0;
308 // bits<1> ALT_CONST = 0;
309 // bits<2> BUFFER_INDEX_MODE = 0;
311 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
312 // is done in R600CodeEmitter
314 // Inst{79-64} = OFFSET;
315 // Inst{81-80} = ENDIAN_SWAP;
316 // Inst{82} = CONST_BUF_NO_STRIDE;
317 // Inst{83} = MEGA_FETCH;
318 // Inst{84} = ALT_CONST;
319 // Inst{86-85} = BUFFER_INDEX_MODE;
320 // Inst{95-86} = 0; Reserved
322 // VTX_WORD3 (Padding)
329 class LoadParamFrag <PatFrag load_type> : PatFrag <
330 (ops node:$ptr), (load_type node:$ptr),
331 [{ return isConstantLoad(dyn_cast<LoadSDNode>(N), 0); }]
334 def load_param : LoadParamFrag<load>;
335 def load_param_exti8 : LoadParamFrag<az_extloadi8>;
336 def load_param_exti16 : LoadParamFrag<az_extloadi16>;
338 def isR600 : Predicate<"Subtarget.getGeneration() <= AMDGPUSubtarget::R700">;
339 def isR700 : Predicate<"Subtarget.getGeneration() == AMDGPUSubtarget::R700">;
340 def isEG : Predicate<
341 "Subtarget.getGeneration() >= AMDGPUSubtarget::EVERGREEN && "
342 "Subtarget.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && "
343 "!Subtarget.hasCaymanISA()">;
345 def isCayman : Predicate<"Subtarget.hasCaymanISA()">;
346 def isEGorCayman : Predicate<"Subtarget.getGeneration() == "
347 "AMDGPUSubtarget::EVERGREEN"
348 "|| Subtarget.getGeneration() =="
349 "AMDGPUSubtarget::NORTHERN_ISLANDS">;
351 def isR600toCayman : Predicate<
352 "Subtarget.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">;
354 //===----------------------------------------------------------------------===//
356 //===----------------------------------------------------------------------===//
358 def INTERP_PAIR_XY : AMDGPUShaderInst <
359 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),
360 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
361 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
364 def INTERP_PAIR_ZW : AMDGPUShaderInst <
365 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),
366 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
367 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
370 def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS",
371 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>,
375 def DOT4 : SDNode<"AMDGPUISD::DOT4",
376 SDTypeProfile<1, 8, [SDTCisFP<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32>,
377 SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>,
378 SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>,
382 def COS_HW : SDNode<"AMDGPUISD::COS_HW",
383 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>
386 def SIN_HW : SDNode<"AMDGPUISD::SIN_HW",
387 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>
390 def TEXTURE_FETCH_Type : SDTypeProfile<1, 19, [SDTCisFP<0>]>;
392 def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>;
394 multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> {
395 def : Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR,
396 (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw),
397 (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz),
398 (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z),
399 (i32 imm:$DST_SEL_W),
400 (i32 imm:$RESOURCE_ID), (i32 imm:$SAMPLER_ID),
401 (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z),
402 (i32 imm:$COORD_TYPE_W)),
403 (inst R600_Reg128:$SRC_GPR,
404 imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw,
405 imm:$offsetx, imm:$offsety, imm:$offsetz,
406 imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z,
408 imm:$RESOURCE_ID, imm:$SAMPLER_ID,
409 imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z,
413 //===----------------------------------------------------------------------===//
414 // Interpolation Instructions
415 //===----------------------------------------------------------------------===//
417 def INTERP_VEC_LOAD : AMDGPUShaderInst <
418 (outs R600_Reg128:$dst),
420 "INTERP_LOAD $src0 : $dst",
423 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {
424 let bank_swizzle = 5;
427 def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> {
428 let bank_swizzle = 5;
431 def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
433 //===----------------------------------------------------------------------===//
434 // Export Instructions
435 //===----------------------------------------------------------------------===//
437 def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
439 def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
440 [SDNPHasChain, SDNPSideEffect]>;
443 field bits<32> Word0;
450 let Word0{12-0} = arraybase;
451 let Word0{14-13} = type;
452 let Word0{21-15} = gpr;
453 let Word0{22} = 0; // RW_REL
454 let Word0{29-23} = 0; // INDEX_GPR
455 let Word0{31-30} = elem_size;
458 class ExportSwzWord1 {
459 field bits<32> Word1;
468 let Word1{2-0} = sw_x;
469 let Word1{5-3} = sw_y;
470 let Word1{8-6} = sw_z;
471 let Word1{11-9} = sw_w;
474 class ExportBufWord1 {
475 field bits<32> Word1;
482 let Word1{11-0} = arraySize;
483 let Word1{15-12} = compMask;
486 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
487 def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg),
489 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
490 0, 61, 0, 7, 7, 7, cf_inst, 0)
493 def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg),
495 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
496 0, 61, 7, 0, 7, 7, cf_inst, 0)
499 def : Pat<(int_R600_store_dummy (i32 imm:$type)),
501 (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
504 def : Pat<(int_R600_store_dummy 1),
506 (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
509 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
510 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
511 (ExportInst R600_Reg128:$src, imm:$type, imm:$base,
512 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)
517 multiclass SteamOutputExportPattern<Instruction ExportInst,
518 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
520 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
521 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),
522 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
523 4095, imm:$mask, buf0inst, 0)>;
525 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
526 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),
527 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
528 4095, imm:$mask, buf1inst, 0)>;
530 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
531 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),
532 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
533 4095, imm:$mask, buf2inst, 0)>;
535 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
536 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),
537 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
538 4095, imm:$mask, buf3inst, 0)>;
541 // Export Instructions should not be duplicated by TailDuplication pass
542 // (which assumes that duplicable instruction are affected by exec mask)
543 let usesCustomInserter = 1, isNotDuplicable = 1 in {
545 class ExportSwzInst : InstR600ISA<(
547 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
548 RSel:$sw_x, RSel:$sw_y, RSel:$sw_z, RSel:$sw_w, i32imm:$inst,
550 !strconcat("EXPORT", " $gpr.$sw_x$sw_y$sw_z$sw_w"),
551 []>, ExportWord0, ExportSwzWord1 {
553 let Inst{31-0} = Word0;
554 let Inst{63-32} = Word1;
558 } // End usesCustomInserter = 1
560 class ExportBufInst : InstR600ISA<(
562 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
563 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop),
564 !strconcat("EXPORT", " $gpr"),
565 []>, ExportWord0, ExportBufWord1 {
567 let Inst{31-0} = Word0;
568 let Inst{63-32} = Word1;
572 //===----------------------------------------------------------------------===//
573 // Control Flow Instructions
574 //===----------------------------------------------------------------------===//
577 def KCACHE : InstFlag<"printKCache">;
579 class ALU_CLAUSE<bits<4> inst, string OpName> : AMDGPUInst <(outs),
580 (ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1,
581 KCACHE:$KCACHE_MODE0, KCACHE:$KCACHE_MODE1,
582 i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1,
583 i32imm:$COUNT, i32imm:$Enabled),
584 !strconcat(OpName, " $COUNT, @$ADDR, "
585 "KC0[$KCACHE_MODE0], KC1[$KCACHE_MODE1]"),
586 [] >, CF_ALU_WORD0, CF_ALU_WORD1 {
591 let WHOLE_QUAD_MODE = 0;
594 let Inst{31-0} = Word0;
595 let Inst{63-32} = Word1;
598 class CF_WORD0_R600 {
599 field bits<32> Word0;
606 class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
607 ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 {
614 let VALID_PIXEL_MODE = 0;
616 let COUNT = CNT{2-0};
618 let COUNT_3 = CNT{3};
619 let END_OF_PROGRAM = 0;
620 let WHOLE_QUAD_MODE = 0;
622 let Inst{31-0} = Word0;
623 let Inst{63-32} = Word1;
626 class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
627 ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG {
632 let JUMPTABLE_SEL = 0;
634 let VALID_PIXEL_MODE = 0;
636 let END_OF_PROGRAM = 0;
638 let Inst{31-0} = Word0;
639 let Inst{63-32} = Word1;
642 def CF_ALU : ALU_CLAUSE<8, "ALU">;
643 def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">;
644 def CF_ALU_POP_AFTER : ALU_CLAUSE<10, "ALU_POP_AFTER">;
646 def FETCH_CLAUSE : AMDGPUInst <(outs),
647 (ins i32imm:$addr), "Fetch clause starting at $addr:", [] > {
653 def ALU_CLAUSE : AMDGPUInst <(outs),
654 (ins i32imm:$addr), "ALU clause starting at $addr:", [] > {
660 def LITERALS : AMDGPUInst <(outs),
661 (ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > {
666 let Inst{31-0} = literal1;
667 let Inst{63-32} = literal2;
670 def PAD : AMDGPUInst <(outs), (ins), "PAD", [] > {
674 let Predicates = [isR600toCayman] in {
676 //===----------------------------------------------------------------------===//
677 // Common Instructions R600, R700, Evergreen, Cayman
678 //===----------------------------------------------------------------------===//
680 def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;
681 // Non-IEEE MUL: 0 * anything = 0
682 def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>;
683 def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
684 def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax>;
685 def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin>;
687 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
688 // so some of the instruction names don't match the asm string.
689 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
690 def SETE : R600_2OP <
692 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_EQ))]
697 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_GT))]
702 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_GE))]
707 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_NE))]
710 def SETE_DX10 : R600_2OP <
712 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_EQ))]
715 def SETGT_DX10 : R600_2OP <
717 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_GT))]
720 def SETGE_DX10 : R600_2OP <
722 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_GE))]
725 def SETNE_DX10 : R600_2OP <
727 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_NE))]
730 def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;
731 def TRUNC : R600_1OP_Helper <0x11, "TRUNC", int_AMDGPU_trunc>;
732 def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
733 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
734 def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
736 def MOV : R600_1OP <0x19, "MOV", []>;
738 let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
740 class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst <
741 (outs R600_Reg32:$dst),
747 } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1
749 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
752 (MOV_IMM_I32 imm:$val)
755 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
758 (MOV_IMM_F32 fpimm:$val)
761 def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>;
762 def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>;
763 def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>;
764 def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>;
766 let hasSideEffects = 1 in {
768 def KILLGT : R600_2OP <0x2D, "KILLGT", []>;
770 } // end hasSideEffects
772 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
773 def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;
774 def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;
775 def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;
776 def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;
777 def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;
778 def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>;
779 def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>;
780 def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUumax>;
781 def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>;
783 def SETE_INT : R600_2OP <
785 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETEQ))]
788 def SETGT_INT : R600_2OP <
790 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))]
793 def SETGE_INT : R600_2OP <
795 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))]
798 def SETNE_INT : R600_2OP <
800 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))]
803 def SETGT_UINT : R600_2OP <
805 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))]
808 def SETGE_UINT : R600_2OP <
810 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))]
813 def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>;
814 def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>;
815 def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>;
816 def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>;
818 def CNDE_INT : R600_3OP <
820 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_EQ))]
823 def CNDGE_INT : R600_3OP <
825 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_GE))]
828 def CNDGT_INT : R600_3OP <
830 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_GT))]
833 //===----------------------------------------------------------------------===//
834 // Texture instructions
835 //===----------------------------------------------------------------------===//
837 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
839 class R600_TEX <bits<11> inst, string opName> :
840 InstR600 <(outs R600_Reg128:$DST_GPR),
841 (ins R600_Reg128:$SRC_GPR,
842 RSel:$srcx, RSel:$srcy, RSel:$srcz, RSel:$srcw,
843 i32imm:$offsetx, i32imm:$offsety, i32imm:$offsetz,
844 RSel:$DST_SEL_X, RSel:$DST_SEL_Y, RSel:$DST_SEL_Z, RSel:$DST_SEL_W,
845 i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID,
846 CT:$COORD_TYPE_X, CT:$COORD_TYPE_Y, CT:$COORD_TYPE_Z,
849 " $DST_GPR.$DST_SEL_X$DST_SEL_Y$DST_SEL_Z$DST_SEL_W, "
850 "$SRC_GPR.$srcx$srcy$srcz$srcw "
851 "RID:$RESOURCE_ID SID:$SAMPLER_ID "
852 "CT:$COORD_TYPE_X$COORD_TYPE_Y$COORD_TYPE_Z$COORD_TYPE_W"),
854 NullALU>, TEX_WORD0, TEX_WORD1, TEX_WORD2 {
855 let Inst{31-0} = Word0;
856 let Inst{63-32} = Word1;
858 let TEX_INST = inst{4-0};
864 let FETCH_WHOLE_QUAD = 0;
866 let SAMPLER_INDEX_MODE = 0;
867 let RESOURCE_INDEX_MODE = 0;
872 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
876 def TEX_SAMPLE : R600_TEX <0x10, "TEX_SAMPLE">;
877 def TEX_SAMPLE_C : R600_TEX <0x18, "TEX_SAMPLE_C">;
878 def TEX_SAMPLE_L : R600_TEX <0x11, "TEX_SAMPLE_L">;
879 def TEX_SAMPLE_C_L : R600_TEX <0x19, "TEX_SAMPLE_C_L">;
880 def TEX_SAMPLE_LB : R600_TEX <0x12, "TEX_SAMPLE_LB">;
881 def TEX_SAMPLE_C_LB : R600_TEX <0x1A, "TEX_SAMPLE_C_LB">;
882 def TEX_LD : R600_TEX <0x03, "TEX_LD">;
883 def TEX_GET_TEXTURE_RESINFO : R600_TEX <0x04, "TEX_GET_TEXTURE_RESINFO">;
884 def TEX_GET_GRADIENTS_H : R600_TEX <0x07, "TEX_GET_GRADIENTS_H">;
885 def TEX_GET_GRADIENTS_V : R600_TEX <0x08, "TEX_GET_GRADIENTS_V">;
886 def TEX_SET_GRADIENTS_H : R600_TEX <0x0B, "TEX_SET_GRADIENTS_H">;
887 def TEX_SET_GRADIENTS_V : R600_TEX <0x0C, "TEX_SET_GRADIENTS_V">;
888 def TEX_SAMPLE_G : R600_TEX <0x14, "TEX_SAMPLE_G">;
889 def TEX_SAMPLE_C_G : R600_TEX <0x1C, "TEX_SAMPLE_C_G">;
891 defm : TexPattern<0, TEX_SAMPLE>;
892 defm : TexPattern<1, TEX_SAMPLE_C>;
893 defm : TexPattern<2, TEX_SAMPLE_L>;
894 defm : TexPattern<3, TEX_SAMPLE_C_L>;
895 defm : TexPattern<4, TEX_SAMPLE_LB>;
896 defm : TexPattern<5, TEX_SAMPLE_C_LB>;
897 defm : TexPattern<6, TEX_LD, v4i32>;
898 defm : TexPattern<7, TEX_GET_TEXTURE_RESINFO, v4i32>;
899 defm : TexPattern<8, TEX_GET_GRADIENTS_H>;
900 defm : TexPattern<9, TEX_GET_GRADIENTS_V>;
902 //===----------------------------------------------------------------------===//
903 // Helper classes for common instructions
904 //===----------------------------------------------------------------------===//
906 class MUL_LIT_Common <bits<5> inst> : R600_3OP <
911 class MULADD_Common <bits<5> inst> : R600_3OP <
916 class MULADD_IEEE_Common <bits<5> inst> : R600_3OP <
918 [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))]
921 class CNDE_Common <bits<5> inst> : R600_3OP <
923 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_EQ))]
926 class CNDGT_Common <bits<5> inst> : R600_3OP <
928 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_GT))]
930 let Itinerary = VecALU;
933 class CNDGE_Common <bits<5> inst> : R600_3OP <
935 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_GE))]
937 let Itinerary = VecALU;
941 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
942 class R600_VEC2OP<list<dag> pattern> : InstR600 <(outs R600_Reg32:$dst), (ins
944 UEM:$update_exec_mask_X, UP:$update_pred_X, WRITE:$write_X,
945 OMOD:$omod_X, REL:$dst_rel_X, CLAMP:$clamp_X,
946 R600_TReg32_X:$src0_X, NEG:$src0_neg_X, REL:$src0_rel_X, ABS:$src0_abs_X, SEL:$src0_sel_X,
947 R600_TReg32_X:$src1_X, NEG:$src1_neg_X, REL:$src1_rel_X, ABS:$src1_abs_X, SEL:$src1_sel_X,
948 R600_Pred:$pred_sel_X,
950 UEM:$update_exec_mask_Y, UP:$update_pred_Y, WRITE:$write_Y,
951 OMOD:$omod_Y, REL:$dst_rel_Y, CLAMP:$clamp_Y,
952 R600_TReg32_Y:$src0_Y, NEG:$src0_neg_Y, REL:$src0_rel_Y, ABS:$src0_abs_Y, SEL:$src0_sel_Y,
953 R600_TReg32_Y:$src1_Y, NEG:$src1_neg_Y, REL:$src1_rel_Y, ABS:$src1_abs_Y, SEL:$src1_sel_Y,
954 R600_Pred:$pred_sel_Y,
956 UEM:$update_exec_mask_Z, UP:$update_pred_Z, WRITE:$write_Z,
957 OMOD:$omod_Z, REL:$dst_rel_Z, CLAMP:$clamp_Z,
958 R600_TReg32_Z:$src0_Z, NEG:$src0_neg_Z, REL:$src0_rel_Z, ABS:$src0_abs_Z, SEL:$src0_sel_Z,
959 R600_TReg32_Z:$src1_Z, NEG:$src1_neg_Z, REL:$src1_rel_Z, ABS:$src1_abs_Z, SEL:$src1_sel_Z,
960 R600_Pred:$pred_sel_Z,
962 UEM:$update_exec_mask_W, UP:$update_pred_W, WRITE:$write_W,
963 OMOD:$omod_W, REL:$dst_rel_W, CLAMP:$clamp_W,
964 R600_TReg32_W:$src0_W, NEG:$src0_neg_W, REL:$src0_rel_W, ABS:$src0_abs_W, SEL:$src0_sel_W,
965 R600_TReg32_W:$src1_W, NEG:$src1_neg_W, REL:$src1_rel_W, ABS:$src1_abs_W, SEL:$src1_sel_W,
966 R600_Pred:$pred_sel_W,
967 LITERAL:$literal0, LITERAL:$literal1),
972 let UseNamedOperandTable = 1;
977 def DOT_4 : R600_VEC2OP<[(set R600_Reg32:$dst, (DOT4
978 R600_TReg32_X:$src0_X, R600_TReg32_X:$src1_X,
979 R600_TReg32_Y:$src0_Y, R600_TReg32_Y:$src1_Y,
980 R600_TReg32_Z:$src0_Z, R600_TReg32_Z:$src1_Z,
981 R600_TReg32_W:$src0_W, R600_TReg32_W:$src1_W))]>;
984 class DOT4_Common <bits<11> inst> : R600_2OP <inst, "DOT4", []>;
987 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
988 multiclass CUBE_Common <bits<11> inst> {
990 def _pseudo : InstR600 <
991 (outs R600_Reg128:$dst),
992 (ins R600_Reg128:$src0),
994 [(set v4f32:$dst, (int_AMDGPU_cube v4f32:$src0))],
998 let UseNamedOperandTable = 1;
1001 def _real : R600_2OP <inst, "CUBE", []>;
1003 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
1005 class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1006 inst, "EXP_IEEE", fexp2
1008 let Itinerary = TransALU;
1011 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper <
1012 inst, "FLT_TO_INT", fp_to_sint
1014 let Itinerary = TransALU;
1017 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1018 inst, "INT_TO_FLT", sint_to_fp
1020 let Itinerary = TransALU;
1023 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1024 inst, "FLT_TO_UINT", fp_to_uint
1026 let Itinerary = TransALU;
1029 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1030 inst, "UINT_TO_FLT", uint_to_fp
1032 let Itinerary = TransALU;
1035 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
1036 inst, "LOG_CLAMPED", []
1039 class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1040 inst, "LOG_IEEE", flog2
1042 let Itinerary = TransALU;
1045 class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;
1046 class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;
1047 class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;
1048 class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <
1049 inst, "MULHI_INT", mulhs
1051 let Itinerary = TransALU;
1053 class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <
1054 inst, "MULHI", mulhu
1056 let Itinerary = TransALU;
1058 class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <
1059 inst, "MULLO_INT", mul
1061 let Itinerary = TransALU;
1063 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []> {
1064 let Itinerary = TransALU;
1067 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
1068 inst, "RECIP_CLAMPED", []
1070 let Itinerary = TransALU;
1073 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
1074 inst, "RECIP_IEEE", [(set f32:$dst, (fdiv FP_ONE, f32:$src0))]
1076 let Itinerary = TransALU;
1079 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1080 inst, "RECIP_UINT", AMDGPUurecip
1082 let Itinerary = TransALU;
1085 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <
1086 inst, "RECIPSQRT_CLAMPED", int_AMDGPU_rsq
1088 let Itinerary = TransALU;
1091 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP <
1092 inst, "RECIPSQRT_IEEE", []
1094 let Itinerary = TransALU;
1097 class SIN_Common <bits<11> inst> : R600_1OP <
1098 inst, "SIN", [(set f32:$dst, (SIN_HW f32:$src0))]>{
1100 let Itinerary = TransALU;
1103 class COS_Common <bits<11> inst> : R600_1OP <
1104 inst, "COS", [(set f32:$dst, (COS_HW f32:$src0))]> {
1106 let Itinerary = TransALU;
1109 //===----------------------------------------------------------------------===//
1110 // Helper patterns for complex intrinsics
1111 //===----------------------------------------------------------------------===//
1113 multiclass DIV_Common <InstR600 recip_ieee> {
1115 (int_AMDGPU_div f32:$src0, f32:$src1),
1116 (MUL_IEEE $src0, (recip_ieee $src1))
1120 (fdiv f32:$src0, f32:$src1),
1121 (MUL_IEEE $src0, (recip_ieee $src1))
1125 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee>
1127 (int_TGSI_lit_z f32:$src_x, f32:$src_y, f32:$src_w),
1128 (exp_ieee (mul_lit (log_clamped (MAX $src_y, (f32 ZERO))), $src_w, $src_x))
1131 //===----------------------------------------------------------------------===//
1132 // R600 / R700 Instructions
1133 //===----------------------------------------------------------------------===//
1135 let Predicates = [isR600] in {
1137 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
1138 def MULADD_r600 : MULADD_Common<0x10>;
1139 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>;
1140 def CNDE_r600 : CNDE_Common<0x18>;
1141 def CNDGT_r600 : CNDGT_Common<0x19>;
1142 def CNDGE_r600 : CNDGE_Common<0x1A>;
1143 def DOT4_r600 : DOT4_Common<0x50>;
1144 defm CUBE_r600 : CUBE_Common<0x52>;
1145 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
1146 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
1147 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
1148 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
1149 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
1150 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
1151 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
1152 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
1153 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
1154 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
1155 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
1156 def SIN_r600 : SIN_Common<0x6E>;
1157 def COS_r600 : COS_Common<0x6F>;
1158 def ASHR_r600 : ASHR_Common<0x70>;
1159 def LSHR_r600 : LSHR_Common<0x71>;
1160 def LSHL_r600 : LSHL_Common<0x72>;
1161 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
1162 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
1163 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
1164 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
1165 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
1167 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
1168 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>;
1169 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
1171 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>;
1173 def R600_ExportSwz : ExportSwzInst {
1174 let Word1{20-17} = 0; // BURST_COUNT
1175 let Word1{21} = eop;
1176 let Word1{22} = 1; // VALID_PIXEL_MODE
1177 let Word1{30-23} = inst;
1178 let Word1{31} = 1; // BARRIER
1180 defm : ExportPattern<R600_ExportSwz, 39>;
1182 def R600_ExportBuf : ExportBufInst {
1183 let Word1{20-17} = 0; // BURST_COUNT
1184 let Word1{21} = eop;
1185 let Word1{22} = 1; // VALID_PIXEL_MODE
1186 let Word1{30-23} = inst;
1187 let Word1{31} = 1; // BARRIER
1189 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>;
1191 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$CNT),
1192 "TEX $CNT @$ADDR"> {
1195 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$CNT),
1196 "VTX $CNT @$ADDR"> {
1199 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR),
1200 "LOOP_START_DX10 @$ADDR"> {
1204 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1208 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR),
1209 "LOOP_BREAK @$ADDR"> {
1213 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR),
1214 "CONTINUE @$ADDR"> {
1218 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1219 "JUMP @$ADDR POP:$POP_COUNT"> {
1222 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1223 "ELSE @$ADDR POP:$POP_COUNT"> {
1226 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> {
1231 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1232 "POP @$ADDR POP:$POP_COUNT"> {
1235 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> {
1239 let END_OF_PROGRAM = 1;
1244 //===----------------------------------------------------------------------===//
1245 // R700 Only instructions
1246 //===----------------------------------------------------------------------===//
1248 let Predicates = [isR700] in {
1249 def SIN_r700 : SIN_Common<0x6E>;
1250 def COS_r700 : COS_Common<0x6F>;
1253 //===----------------------------------------------------------------------===//
1254 // Evergreen / Cayman store instructions
1255 //===----------------------------------------------------------------------===//
1257 let Predicates = [isEGorCayman] in {
1259 class CF_MEM_RAT_CACHELESS <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins,
1260 string name, list<dag> pattern>
1261 : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins,
1262 "MEM_RAT_CACHELESS "#name, pattern>;
1264 class CF_MEM_RAT <bits<6> rat_inst, bits<4> rat_id, dag ins, string name,
1266 : EG_CF_RAT <0x56, rat_inst, rat_id, 0xf /* mask */, (outs), ins,
1267 "MEM_RAT "#name, pattern>;
1269 def RAT_MSKOR : CF_MEM_RAT <0x11, 0,
1270 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
1271 "MSKOR $rw_gpr.XW, $index_gpr",
1272 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)]
1277 } // End Predicates = [isEGorCayman]
1280 //===----------------------------------------------------------------------===//
1281 // Evergreen Only instructions
1282 //===----------------------------------------------------------------------===//
1284 let Predicates = [isEG] in {
1286 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
1287 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
1289 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
1290 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
1291 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
1292 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
1293 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
1294 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
1295 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
1296 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
1297 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
1298 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
1299 def SIN_eg : SIN_Common<0x8D>;
1300 def COS_eg : COS_Common<0x8E>;
1302 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>;
1303 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>;
1305 //===----------------------------------------------------------------------===//
1306 // Memory read/write instructions
1307 //===----------------------------------------------------------------------===//
1309 let usesCustomInserter = 1 in {
1312 def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1,
1313 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1314 "STORE_RAW $rw_gpr, $index_gpr, $eop",
1315 [(global_store i32:$rw_gpr, i32:$index_gpr)]
1319 def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3,
1320 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1321 "STORE_RAW $rw_gpr.XY, $index_gpr, $eop",
1322 [(global_store v2i32:$rw_gpr, i32:$index_gpr)]
1326 def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf,
1327 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1328 "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop",
1329 [(global_store v4i32:$rw_gpr, i32:$index_gpr)]
1332 } // End usesCustomInserter = 1
1334 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
1335 : VTX_WORD0_eg, VTX_READ<name, buffer_id, outs, pattern> {
1340 let FETCH_WHOLE_QUAD = 0;
1341 let BUFFER_ID = buffer_id;
1343 // XXX: We can infer this field based on the SRC_GPR. This would allow us
1344 // to store vertex addresses in any channel, not just X.
1347 let Inst{31-0} = Word0;
1350 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
1351 : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
1352 (outs R600_TReg32_X:$dst_gpr), pattern> {
1354 let MEGA_FETCH_COUNT = 1;
1356 let DST_SEL_Y = 7; // Masked
1357 let DST_SEL_Z = 7; // Masked
1358 let DST_SEL_W = 7; // Masked
1359 let DATA_FORMAT = 1; // FMT_8
1362 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
1363 : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
1364 (outs R600_TReg32_X:$dst_gpr), pattern> {
1365 let MEGA_FETCH_COUNT = 2;
1367 let DST_SEL_Y = 7; // Masked
1368 let DST_SEL_Z = 7; // Masked
1369 let DST_SEL_W = 7; // Masked
1370 let DATA_FORMAT = 5; // FMT_16
1374 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
1375 : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
1376 (outs R600_TReg32_X:$dst_gpr), pattern> {
1378 let MEGA_FETCH_COUNT = 4;
1380 let DST_SEL_Y = 7; // Masked
1381 let DST_SEL_Z = 7; // Masked
1382 let DST_SEL_W = 7; // Masked
1383 let DATA_FORMAT = 0xD; // COLOR_32
1385 // This is not really necessary, but there were some GPU hangs that appeared
1386 // to be caused by ALU instructions in the next instruction group that wrote
1387 // to the $src_gpr registers of the VTX_READ.
1389 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
1390 // %T2_X<def> = MOV %ZERO
1391 //Adding this constraint prevents this from happening.
1392 let Constraints = "$src_gpr.ptr = $dst_gpr";
1395 class VTX_READ_64_eg <bits<8> buffer_id, list<dag> pattern>
1396 : VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr", buffer_id,
1397 (outs R600_Reg64:$dst_gpr), pattern> {
1399 let MEGA_FETCH_COUNT = 8;
1404 let DATA_FORMAT = 0x1D; // COLOR_32_32
1407 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
1408 : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
1409 (outs R600_Reg128:$dst_gpr), pattern> {
1411 let MEGA_FETCH_COUNT = 16;
1416 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1418 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1419 // that holds its buffer address to avoid potential hangs. We can't use
1420 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
1421 // registers are different sizes.
1424 //===----------------------------------------------------------------------===//
1425 // VTX Read from parameter memory space
1426 //===----------------------------------------------------------------------===//
1428 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0,
1429 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))]
1432 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0,
1433 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))]
1436 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0,
1437 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1440 def VTX_READ_PARAM_64_eg : VTX_READ_64_eg <0,
1441 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1444 def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0,
1445 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1448 //===----------------------------------------------------------------------===//
1449 // VTX Read from global memory space
1450 //===----------------------------------------------------------------------===//
1453 def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1,
1454 [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))]
1457 def VTX_READ_GLOBAL_16_eg : VTX_READ_16_eg <1,
1458 [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))]
1462 def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1,
1463 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1467 def VTX_READ_GLOBAL_64_eg : VTX_READ_64_eg <1,
1468 [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1472 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
1473 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1476 } // End Predicates = [isEG]
1478 //===----------------------------------------------------------------------===//
1479 // Evergreen / Cayman Instructions
1480 //===----------------------------------------------------------------------===//
1482 let Predicates = [isEGorCayman] in {
1484 // BFE_UINT - bit_extract, an optimization for mask and shift
1489 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
1494 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
1495 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
1496 // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
1497 // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
1498 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
1499 [(set i32:$dst, (int_AMDIL_bit_extract_u32 i32:$src0, i32:$src1,
1503 def : BFEPattern <BFE_UINT_eg>;
1505 def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", [], VecALU>;
1506 defm : BFIPatterns <BFI_INT_eg>;
1508 def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24",
1509 [(set i32:$dst, (add (mul U24:$src0, U24:$src1), i32:$src2))], VecALU
1511 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>;
1512 def : ROTRPattern <BIT_ALIGN_INT_eg>;
1514 def MULADD_eg : MULADD_Common<0x14>;
1515 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
1516 def ASHR_eg : ASHR_Common<0x15>;
1517 def LSHR_eg : LSHR_Common<0x16>;
1518 def LSHL_eg : LSHL_Common<0x17>;
1519 def CNDE_eg : CNDE_Common<0x19>;
1520 def CNDGT_eg : CNDGT_Common<0x1A>;
1521 def CNDGE_eg : CNDGE_Common<0x1B>;
1522 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
1523 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
1524 def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24",
1525 [(set i32:$dst, (mul U24:$src0, U24:$src1))], VecALU
1527 def DOT4_eg : DOT4_Common<0xBE>;
1528 defm CUBE_eg : CUBE_Common<0xC0>;
1530 let hasSideEffects = 1 in {
1531 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", []>;
1534 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
1536 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
1538 let Itinerary = AnyALU;
1541 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
1543 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
1547 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
1549 def GROUP_BARRIER : InstR600 <
1550 (outs), (ins), " GROUP_BARRIER", [(int_AMDGPU_barrier_local)], AnyALU>,
1552 R600ALU_Word1_OP2 <0x54> {
1568 let bank_swizzle = 0;
1570 let update_exec_mask = 0;
1571 let update_pred = 0;
1573 let Inst{31-0} = Word0;
1574 let Inst{63-32} = Word1;
1579 //===----------------------------------------------------------------------===//
1581 //===----------------------------------------------------------------------===//
1582 class R600_LDS <bits<6> op, dag outs, dag ins, string asm,
1583 list<dag> pattern = []> :
1585 InstR600 <outs, ins, asm, pattern, XALU>,
1592 let Word1{27} = offset{0};
1593 let Word1{12} = offset{1};
1594 let Word1{28} = offset{2};
1595 let Word1{31} = offset{3};
1596 let Word0{12} = offset{4};
1597 let Word0{25} = offset{5};
1600 let Inst{31-0} = Word0;
1601 let Inst{63-32} = Word1;
1604 let HasNativeOperands = 1;
1605 let UseNamedOperandTable = 1;
1608 class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS <
1610 (outs R600_Reg32:$dst),
1611 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
1612 LAST:$last, R600_Pred:$pred_sel,
1613 BANK_SWIZZLE:$bank_swizzle),
1614 " "#name#" $last OQAP, $src0$src0_rel $pred_sel",
1624 let usesCustomInserter = 1;
1626 let DisableEncoding = "$dst";
1629 class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern,
1633 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
1634 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
1635 LAST:$last, R600_Pred:$pred_sel,
1636 BANK_SWIZZLE:$bank_swizzle),
1637 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel",
1641 field string BaseOp;
1648 class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> :
1649 R600_LDS_1A1D <lds_op, (outs), name, pattern> {
1653 class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> :
1654 R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name##"_RET", pattern, "OQAP, "> {
1657 let usesCustomInserter = 1;
1658 let DisableEncoding = "$dst";
1662 class R600_LDS_1A2D <bits<6> lds_op, string name, list<dag> pattern> :
1666 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
1667 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
1668 R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel,
1669 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle),
1670 " "#name# "$last $src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel",
1675 def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >;
1676 def LDS_SUB : R600_LDS_1A1D_NORET <0x1, "LDS_SUB", [] >;
1677 def LDS_WRITE : R600_LDS_1A1D_NORET <0xD, "LDS_WRITE",
1678 [(local_store (i32 R600_Reg32:$src1), R600_Reg32:$src0)]
1680 def LDS_BYTE_WRITE : R600_LDS_1A1D_NORET<0x12, "LDS_BYTE_WRITE",
1681 [(truncstorei8_local i32:$src1, i32:$src0)]
1683 def LDS_SHORT_WRITE : R600_LDS_1A1D_NORET<0x13, "LDS_SHORT_WRITE",
1684 [(truncstorei16_local i32:$src1, i32:$src0)]
1686 def LDS_ADD_RET : R600_LDS_1A1D_RET <0x20, "LDS_ADD",
1687 [(set i32:$dst, (atomic_load_add_local i32:$src0, i32:$src1))]
1689 def LDS_SUB_RET : R600_LDS_1A1D_RET <0x21, "LDS_SUB",
1690 [(set i32:$dst, (atomic_load_sub_local i32:$src0, i32:$src1))]
1692 def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET",
1693 [(set (i32 R600_Reg32:$dst), (local_load R600_Reg32:$src0))]
1695 def LDS_BYTE_READ_RET : R600_LDS_1A <0x36, "LDS_BYTE_READ_RET",
1696 [(set i32:$dst, (sextloadi8_local i32:$src0))]
1698 def LDS_UBYTE_READ_RET : R600_LDS_1A <0x37, "LDS_UBYTE_READ_RET",
1699 [(set i32:$dst, (az_extloadi8_local i32:$src0))]
1701 def LDS_SHORT_READ_RET : R600_LDS_1A <0x38, "LDS_SHORT_READ_RET",
1702 [(set i32:$dst, (sextloadi16_local i32:$src0))]
1704 def LDS_USHORT_READ_RET : R600_LDS_1A <0x39, "LDS_USHORT_READ_RET",
1705 [(set i32:$dst, (az_extloadi16_local i32:$src0))]
1708 // TRUNC is used for the FLT_TO_INT instructions to work around a
1709 // perceived problem where the rounding modes are applied differently
1710 // depending on the instruction and the slot they are in.
1712 // https://bugs.freedesktop.org/show_bug.cgi?id=50232
1713 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
1715 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
1716 // which do not need to be truncated since the fp values are 0.0f or 1.0f.
1717 // We should look into handling these cases separately.
1718 def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>;
1720 def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>;
1723 def : SHA256MaPattern <BFI_INT_eg, XOR_INT>;
1725 def EG_ExportSwz : ExportSwzInst {
1726 let Word1{19-16} = 0; // BURST_COUNT
1727 let Word1{20} = 1; // VALID_PIXEL_MODE
1728 let Word1{21} = eop;
1729 let Word1{29-22} = inst;
1730 let Word1{30} = 0; // MARK
1731 let Word1{31} = 1; // BARRIER
1733 defm : ExportPattern<EG_ExportSwz, 83>;
1735 def EG_ExportBuf : ExportBufInst {
1736 let Word1{19-16} = 0; // BURST_COUNT
1737 let Word1{20} = 1; // VALID_PIXEL_MODE
1738 let Word1{21} = eop;
1739 let Word1{29-22} = inst;
1740 let Word1{30} = 0; // MARK
1741 let Word1{31} = 1; // BARRIER
1743 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
1745 def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),
1746 "TEX $COUNT @$ADDR"> {
1749 def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),
1750 "VTX $COUNT @$ADDR"> {
1753 def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),
1754 "LOOP_START_DX10 @$ADDR"> {
1758 def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1762 def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),
1763 "LOOP_BREAK @$ADDR"> {
1767 def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),
1768 "CONTINUE @$ADDR"> {
1772 def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1773 "JUMP @$ADDR POP:$POP_COUNT"> {
1776 def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1777 "ELSE @$ADDR POP:$POP_COUNT"> {
1780 def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> {
1785 def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1786 "POP @$ADDR POP:$POP_COUNT"> {
1789 def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> {
1793 let END_OF_PROGRAM = 1;
1796 } // End Predicates = [isEGorCayman]
1798 //===----------------------------------------------------------------------===//
1799 // Regist loads and stores - for indirect addressing
1800 //===----------------------------------------------------------------------===//
1802 defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;
1804 //===----------------------------------------------------------------------===//
1805 // Cayman Instructions
1806 //===----------------------------------------------------------------------===//
1808 let Predicates = [isCayman] in {
1810 def MULADD_INT24_cm : R600_3OP <0x08, "MULADD_INT24",
1811 [(set i32:$dst, (add (mul I24:$src0, I24:$src1), i32:$src2))], VecALU
1813 def MUL_INT24_cm : R600_2OP <0x5B, "MUL_INT24",
1814 [(set i32:$dst, (mul I24:$src0, I24:$src1))], VecALU
1817 let isVector = 1 in {
1819 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
1821 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
1822 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
1823 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
1824 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
1825 def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
1826 def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
1827 def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;
1828 def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
1829 def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
1830 def SIN_cm : SIN_Common<0x8D>;
1831 def COS_cm : COS_Common<0x8E>;
1832 } // End isVector = 1
1834 def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>;
1836 defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
1838 // RECIP_UINT emulation for Cayman
1839 // The multiplication scales from [0,1] to the unsigned integer range
1841 (AMDGPUurecip i32:$src0),
1842 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)),
1843 (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1)))
1846 def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> {
1852 def : Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>;
1854 class RAT_STORE_DWORD <RegisterClass rc, ValueType vt, bits<4> mask> :
1855 CF_MEM_RAT_CACHELESS <0x14, 0, mask,
1856 (ins rc:$rw_gpr, R600_TReg32_X:$index_gpr),
1857 "STORE_DWORD $rw_gpr, $index_gpr",
1858 [(global_store vt:$rw_gpr, i32:$index_gpr)]> {
1859 let eop = 0; // This bit is not used on Cayman.
1862 def RAT_STORE_DWORD32 : RAT_STORE_DWORD <R600_TReg32_X, i32, 0x1>;
1863 def RAT_STORE_DWORD64 : RAT_STORE_DWORD <R600_Reg64, v2i32, 0x3>;
1864 def RAT_STORE_DWORD128 : RAT_STORE_DWORD <R600_Reg128, v4i32, 0xf>;
1866 class VTX_READ_cm <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
1867 : VTX_WORD0_cm, VTX_READ<name, buffer_id, outs, pattern> {
1872 let FETCH_WHOLE_QUAD = 0;
1873 let BUFFER_ID = buffer_id;
1875 // XXX: We can infer this field based on the SRC_GPR. This would allow us
1876 // to store vertex addresses in any channel, not just X.
1879 let STRUCTURED_READ = 0;
1881 let COALESCED_READ = 0;
1883 let Inst{31-0} = Word0;
1886 class VTX_READ_8_cm <bits<8> buffer_id, list<dag> pattern>
1887 : VTX_READ_cm <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
1888 (outs R600_TReg32_X:$dst_gpr), pattern> {
1891 let DST_SEL_Y = 7; // Masked
1892 let DST_SEL_Z = 7; // Masked
1893 let DST_SEL_W = 7; // Masked
1894 let DATA_FORMAT = 1; // FMT_8
1897 class VTX_READ_16_cm <bits<8> buffer_id, list<dag> pattern>
1898 : VTX_READ_cm <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
1899 (outs R600_TReg32_X:$dst_gpr), pattern> {
1901 let DST_SEL_Y = 7; // Masked
1902 let DST_SEL_Z = 7; // Masked
1903 let DST_SEL_W = 7; // Masked
1904 let DATA_FORMAT = 5; // FMT_16
1908 class VTX_READ_32_cm <bits<8> buffer_id, list<dag> pattern>
1909 : VTX_READ_cm <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
1910 (outs R600_TReg32_X:$dst_gpr), pattern> {
1913 let DST_SEL_Y = 7; // Masked
1914 let DST_SEL_Z = 7; // Masked
1915 let DST_SEL_W = 7; // Masked
1916 let DATA_FORMAT = 0xD; // COLOR_32
1918 // This is not really necessary, but there were some GPU hangs that appeared
1919 // to be caused by ALU instructions in the next instruction group that wrote
1920 // to the $src_gpr registers of the VTX_READ.
1922 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
1923 // %T2_X<def> = MOV %ZERO
1924 //Adding this constraint prevents this from happening.
1925 let Constraints = "$src_gpr.ptr = $dst_gpr";
1928 class VTX_READ_64_cm <bits<8> buffer_id, list<dag> pattern>
1929 : VTX_READ_cm <"VTX_READ_64 $dst_gpr, $src_gpr", buffer_id,
1930 (outs R600_Reg64:$dst_gpr), pattern> {
1936 let DATA_FORMAT = 0x1D; // COLOR_32_32
1939 class VTX_READ_128_cm <bits<8> buffer_id, list<dag> pattern>
1940 : VTX_READ_cm <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
1941 (outs R600_Reg128:$dst_gpr), pattern> {
1947 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1949 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1950 // that holds its buffer address to avoid potential hangs. We can't use
1951 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
1952 // registers are different sizes.
1955 //===----------------------------------------------------------------------===//
1956 // VTX Read from parameter memory space
1957 //===----------------------------------------------------------------------===//
1958 def VTX_READ_PARAM_8_cm : VTX_READ_8_cm <0,
1959 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))]
1962 def VTX_READ_PARAM_16_cm : VTX_READ_16_cm <0,
1963 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))]
1966 def VTX_READ_PARAM_32_cm : VTX_READ_32_cm <0,
1967 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1970 def VTX_READ_PARAM_64_cm : VTX_READ_64_cm <0,
1971 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1974 def VTX_READ_PARAM_128_cm : VTX_READ_128_cm <0,
1975 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1978 //===----------------------------------------------------------------------===//
1979 // VTX Read from global memory space
1980 //===----------------------------------------------------------------------===//
1983 def VTX_READ_GLOBAL_8_cm : VTX_READ_8_cm <1,
1984 [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))]
1987 def VTX_READ_GLOBAL_16_cm : VTX_READ_16_cm <1,
1988 [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))]
1992 def VTX_READ_GLOBAL_32_cm : VTX_READ_32_cm <1,
1993 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1997 def VTX_READ_GLOBAL_64_cm : VTX_READ_64_cm <1,
1998 [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
2002 def VTX_READ_GLOBAL_128_cm : VTX_READ_128_cm <1,
2003 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
2008 //===----------------------------------------------------------------------===//
2009 // Branch Instructions
2010 //===----------------------------------------------------------------------===//
2013 def IF_PREDICATE_SET : ILFormat<(outs), (ins GPRI32:$src),
2014 "IF_PREDICATE_SET $src", []>;
2016 //===----------------------------------------------------------------------===//
2017 // Pseudo instructions
2018 //===----------------------------------------------------------------------===//
2020 let isPseudo = 1 in {
2022 def PRED_X : InstR600 <
2023 (outs R600_Predicate_Bit:$dst),
2024 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
2026 let FlagOperandIdx = 3;
2029 let isTerminator = 1, isBranch = 1 in {
2030 def JUMP_COND : InstR600 <
2032 (ins brtarget:$target, R600_Predicate_Bit:$p),
2033 "JUMP $target ($p)",
2037 def JUMP : InstR600 <
2039 (ins brtarget:$target),
2044 let isPredicable = 1;
2048 } // End isTerminator = 1, isBranch = 1
2050 let usesCustomInserter = 1 in {
2052 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
2054 def MASK_WRITE : AMDGPUShaderInst <
2056 (ins R600_Reg32:$src),
2061 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
2065 (outs R600_Reg128:$dst),
2066 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
2067 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
2068 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
2069 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2,
2070 imm:$resourceId, imm:$samplerId, imm:$textureTarget))],
2075 def TXD_SHADOW: InstR600 <
2076 (outs R600_Reg128:$dst),
2077 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
2078 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
2079 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
2080 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2,
2081 imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))],
2086 } // End isPseudo = 1
2087 } // End usesCustomInserter = 1
2089 def CLAMP_R600 : CLAMP <R600_Reg32>;
2090 def FABS_R600 : FABS<R600_Reg32>;
2091 def FNEG_R600 : FNEG<R600_Reg32>;
2093 //===---------------------------------------------------------------------===//
2094 // Return instruction
2095 //===---------------------------------------------------------------------===//
2096 let isTerminator = 1, isReturn = 1, hasCtrlDep = 1,
2097 usesCustomInserter = 1 in {
2098 def RETURN : ILFormat<(outs), (ins variable_ops),
2099 "RETURN", [(IL_retflag)]>;
2103 //===----------------------------------------------------------------------===//
2104 // Constant Buffer Addressing Support
2105 //===----------------------------------------------------------------------===//
2107 let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
2108 def CONST_COPY : Instruction {
2109 let OutOperandList = (outs R600_Reg32:$dst);
2110 let InOperandList = (ins i32imm:$src);
2112 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
2113 let AsmString = "CONST_COPY";
2114 let neverHasSideEffects = 1;
2115 let isAsCheapAsAMove = 1;
2116 let Itinerary = NullALU;
2118 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
2120 def TEX_VTX_CONSTBUF :
2121 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "VTX_READ_eg $dst, $ptr",
2122 [(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$BUFFER_ID)))]>,
2123 VTX_WORD1_GPR, VTX_WORD0_eg {
2127 let FETCH_WHOLE_QUAD = 0;
2131 let USE_CONST_FIELDS = 0;
2132 let NUM_FORMAT_ALL = 2;
2133 let FORMAT_COMP_ALL = 1;
2134 let SRF_MODE_ALL = 1;
2135 let MEGA_FETCH_COUNT = 16;
2140 let DATA_FORMAT = 35;
2142 let Inst{31-0} = Word0;
2143 let Inst{63-32} = Word1;
2145 // LLVM can only encode 64-bit instructions, so these fields are manually
2146 // encoded in R600CodeEmitter
2149 // bits<2> ENDIAN_SWAP = 0;
2150 // bits<1> CONST_BUF_NO_STRIDE = 0;
2151 // bits<1> MEGA_FETCH = 0;
2152 // bits<1> ALT_CONST = 0;
2153 // bits<2> BUFFER_INDEX_MODE = 0;
2157 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
2158 // is done in R600CodeEmitter
2160 // Inst{79-64} = OFFSET;
2161 // Inst{81-80} = ENDIAN_SWAP;
2162 // Inst{82} = CONST_BUF_NO_STRIDE;
2163 // Inst{83} = MEGA_FETCH;
2164 // Inst{84} = ALT_CONST;
2165 // Inst{86-85} = BUFFER_INDEX_MODE;
2166 // Inst{95-86} = 0; Reserved
2168 // VTX_WORD3 (Padding)
2170 // Inst{127-96} = 0;
2175 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr",
2176 [(set v4f32:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>,
2177 VTX_WORD1_GPR, VTX_WORD0_eg {
2181 let FETCH_WHOLE_QUAD = 0;
2185 let USE_CONST_FIELDS = 1;
2186 let NUM_FORMAT_ALL = 0;
2187 let FORMAT_COMP_ALL = 0;
2188 let SRF_MODE_ALL = 1;
2189 let MEGA_FETCH_COUNT = 16;
2194 let DATA_FORMAT = 0;
2196 let Inst{31-0} = Word0;
2197 let Inst{63-32} = Word1;
2199 // LLVM can only encode 64-bit instructions, so these fields are manually
2200 // encoded in R600CodeEmitter
2203 // bits<2> ENDIAN_SWAP = 0;
2204 // bits<1> CONST_BUF_NO_STRIDE = 0;
2205 // bits<1> MEGA_FETCH = 0;
2206 // bits<1> ALT_CONST = 0;
2207 // bits<2> BUFFER_INDEX_MODE = 0;
2211 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
2212 // is done in R600CodeEmitter
2214 // Inst{79-64} = OFFSET;
2215 // Inst{81-80} = ENDIAN_SWAP;
2216 // Inst{82} = CONST_BUF_NO_STRIDE;
2217 // Inst{83} = MEGA_FETCH;
2218 // Inst{84} = ALT_CONST;
2219 // Inst{86-85} = BUFFER_INDEX_MODE;
2220 // Inst{95-86} = 0; Reserved
2222 // VTX_WORD3 (Padding)
2224 // Inst{127-96} = 0;
2230 //===--------------------------------------------------------------------===//
2231 // Instructions support
2232 //===--------------------------------------------------------------------===//
2233 //===---------------------------------------------------------------------===//
2234 // Custom Inserter for Branches and returns, this eventually will be a
2236 //===---------------------------------------------------------------------===//
2237 let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
2238 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
2239 "; Pseudo unconditional branch instruction",
2241 defm BRANCH_COND : BranchConditional<IL_brcond>;
2244 //===---------------------------------------------------------------------===//
2245 // Flow and Program control Instructions
2246 //===---------------------------------------------------------------------===//
2247 let isTerminator=1 in {
2248 def SWITCH : ILFormat< (outs), (ins GPRI32:$src),
2249 !strconcat("SWITCH", " $src"), []>;
2250 def CASE : ILFormat< (outs), (ins GPRI32:$src),
2251 !strconcat("CASE", " $src"), []>;
2252 def BREAK : ILFormat< (outs), (ins),
2254 def CONTINUE : ILFormat< (outs), (ins),
2256 def DEFAULT : ILFormat< (outs), (ins),
2258 def ELSE : ILFormat< (outs), (ins),
2260 def ENDSWITCH : ILFormat< (outs), (ins),
2262 def ENDMAIN : ILFormat< (outs), (ins),
2264 def END : ILFormat< (outs), (ins),
2266 def ENDFUNC : ILFormat< (outs), (ins),
2268 def ENDIF : ILFormat< (outs), (ins),
2270 def WHILELOOP : ILFormat< (outs), (ins),
2272 def ENDLOOP : ILFormat< (outs), (ins),
2274 def FUNC : ILFormat< (outs), (ins),
2276 def RETDYN : ILFormat< (outs), (ins),
2278 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2279 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">;
2280 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2281 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">;
2282 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2283 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">;
2284 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2285 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">;
2286 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2287 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">;
2288 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2289 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">;
2290 defm IFC : BranchInstr2<"IFC">;
2291 defm BREAKC : BranchInstr2<"BREAKC">;
2292 defm CONTINUEC : BranchInstr2<"CONTINUEC">;
2295 //===----------------------------------------------------------------------===//
2297 //===----------------------------------------------------------------------===//
2299 // CND*_INT Pattterns for f32 True / False values
2301 class CND_INT_f32 <InstR600 cnd, CondCode cc> : Pat <
2302 (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc),
2303 (cnd $src0, $src1, $src2)
2306 def : CND_INT_f32 <CNDE_INT, SETEQ>;
2307 def : CND_INT_f32 <CNDGT_INT, SETGT>;
2308 def : CND_INT_f32 <CNDGE_INT, SETGE>;
2310 //CNDGE_INT extra pattern
2312 (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_GT),
2313 (CNDGE_INT $src0, $src1, $src2)
2319 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
2323 (int_AMDGPU_kill f32:$src0),
2324 (MASK_WRITE (KILLGT (f32 ZERO), $src0))
2327 // The next two patterns are special cases for handling 'true if ordered' and
2328 // 'true if unordered' conditionals. The assumption here is that the behavior of
2329 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
2331 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
2332 // We assume that SETE returns false when one of the operands is NAN and
2333 // SNE returns true when on of the operands is NAN
2335 //SETE - 'true if ordered'
2337 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, SETO),
2341 //SETE_DX10 - 'true if ordered'
2343 (selectcc f32:$src0, f32:$src1, -1, 0, SETO),
2344 (SETE_DX10 $src0, $src1)
2347 //SNE - 'true if unordered'
2349 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, SETUO),
2353 //SETNE_DX10 - 'true if ordered'
2355 (selectcc f32:$src0, f32:$src1, -1, 0, SETUO),
2356 (SETNE_DX10 $src0, $src1)
2359 def : Extract_Element <f32, v4f32, 0, sub0>;
2360 def : Extract_Element <f32, v4f32, 1, sub1>;
2361 def : Extract_Element <f32, v4f32, 2, sub2>;
2362 def : Extract_Element <f32, v4f32, 3, sub3>;
2364 def : Insert_Element <f32, v4f32, 0, sub0>;
2365 def : Insert_Element <f32, v4f32, 1, sub1>;
2366 def : Insert_Element <f32, v4f32, 2, sub2>;
2367 def : Insert_Element <f32, v4f32, 3, sub3>;
2369 def : Extract_Element <i32, v4i32, 0, sub0>;
2370 def : Extract_Element <i32, v4i32, 1, sub1>;
2371 def : Extract_Element <i32, v4i32, 2, sub2>;
2372 def : Extract_Element <i32, v4i32, 3, sub3>;
2374 def : Insert_Element <i32, v4i32, 0, sub0>;
2375 def : Insert_Element <i32, v4i32, 1, sub1>;
2376 def : Insert_Element <i32, v4i32, 2, sub2>;
2377 def : Insert_Element <i32, v4i32, 3, sub3>;
2379 def : Vector4_Build <v4f32, f32>;
2380 def : Vector4_Build <v4i32, i32>;
2382 def : Extract_Element <f32, v2f32, 0, sub0>;
2383 def : Extract_Element <f32, v2f32, 1, sub1>;
2385 def : Insert_Element <f32, v2f32, 0, sub0>;
2386 def : Insert_Element <f32, v2f32, 1, sub1>;
2388 def : Extract_Element <i32, v2i32, 0, sub0>;
2389 def : Extract_Element <i32, v2i32, 1, sub1>;
2391 def : Insert_Element <i32, v2i32, 0, sub0>;
2392 def : Insert_Element <i32, v2i32, 1, sub1>;
2394 // bitconvert patterns
2396 def : BitConvert <i32, f32, R600_Reg32>;
2397 def : BitConvert <f32, i32, R600_Reg32>;
2398 def : BitConvert <v2f32, v2i32, R600_Reg64>;
2399 def : BitConvert <v2i32, v2f32, R600_Reg64>;
2400 def : BitConvert <v4f32, v4i32, R600_Reg128>;
2401 def : BitConvert <v4i32, v4f32, R600_Reg128>;
2403 // DWORDADDR pattern
2404 def : DwordAddrPat <i32, R600_Reg32>;
2406 } // End isR600toCayman Predicate
2408 def getLDSNoRetOp : InstrMapping {
2409 let FilterClass = "R600_LDS_1A1D";
2410 let RowFields = ["BaseOp"];
2411 let ColFields = ["DisableEncoding"];
2412 let KeyCol = ["$dst"];
2413 let ValueCols = [[""""]];