1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // R600 Tablegen instruction definitions
12 //===----------------------------------------------------------------------===//
14 include "R600Intrinsics.td"
15 include "R600InstrFormats.td"
17 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
18 InstR600 <outs, ins, asm, pattern, NullALU> {
20 let Namespace = "AMDGPU";
23 def MEMxi : Operand<iPTR> {
24 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
25 let PrintMethod = "printMemOperand";
28 def MEMrr : Operand<iPTR> {
29 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
32 // Operands for non-registers
34 class InstFlag<string PM = "printOperand", int Default = 0>
35 : OperandWithDefaultOps <i32, (ops (i32 Default))> {
39 // src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
40 def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
41 let PrintMethod = "printSel";
43 def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> {
44 let PrintMethod = "printBankSwizzle";
47 def LITERAL : InstFlag<"printLiteral">;
49 def WRITE : InstFlag <"printWrite", 1>;
50 def OMOD : InstFlag <"printOMOD">;
51 def REL : InstFlag <"printRel">;
52 def CLAMP : InstFlag <"printClamp">;
53 def NEG : InstFlag <"printNeg">;
54 def ABS : InstFlag <"printAbs">;
55 def UEM : InstFlag <"printUpdateExecMask">;
56 def UP : InstFlag <"printUpdatePred">;
58 // XXX: The r600g finalizer in Mesa expects last to be one in most cases.
59 // Once we start using the packetizer in this backend we should have this
61 def LAST : InstFlag<"printLast", 1>;
62 def RSel : Operand<i32> {
63 let PrintMethod = "printRSel";
65 def CT: Operand<i32> {
66 let PrintMethod = "printCT";
69 def FRAMEri : Operand<iPTR> {
70 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index);
73 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
74 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
75 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
76 def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;
77 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
78 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
81 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
85 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
87 // Class for instructions with only one source register.
88 // If you add new ins to this instruction, make sure they are listed before
89 // $literal, because the backend currently assumes that the last operand is
90 // a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in
91 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(),
92 // and R600InstrInfo::getOperandIdx().
93 class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
94 InstrItinClass itin = AnyALU> :
95 InstR600 <(outs R600_Reg32:$dst),
96 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
97 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
98 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
99 BANK_SWIZZLE:$bank_swizzle),
100 !strconcat(" ", opName,
101 "$clamp $last $dst$write$dst_rel$omod, "
102 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
103 "$pred_sel $bank_swizzle"),
107 R600ALU_Word1_OP2 <inst> {
113 let update_exec_mask = 0;
115 let HasNativeOperands = 1;
118 let DisableEncoding = "$literal";
119 let UseNamedOperandTable = 1;
121 let Inst{31-0} = Word0;
122 let Inst{63-32} = Word1;
125 class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
126 InstrItinClass itin = AnyALU> :
127 R600_1OP <inst, opName,
128 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))]
131 // If you add or change the operands for R600_2OP instructions, you must
132 // also update the R600Op2OperandIndex::ROI enum in R600Defines.h,
133 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
134 class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
135 InstrItinClass itin = AnyALU> :
136 InstR600 <(outs R600_Reg32:$dst),
137 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
138 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
139 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
140 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
141 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
142 BANK_SWIZZLE:$bank_swizzle),
143 !strconcat(" ", opName,
144 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
145 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
146 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
147 "$pred_sel $bank_swizzle"),
151 R600ALU_Word1_OP2 <inst> {
153 let HasNativeOperands = 1;
156 let DisableEncoding = "$literal";
157 let UseNamedOperandTable = 1;
159 let Inst{31-0} = Word0;
160 let Inst{63-32} = Word1;
163 class R600_2OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
164 InstrItinClass itim = AnyALU> :
165 R600_2OP <inst, opName,
166 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
170 // If you add our change the operands for R600_3OP instructions, you must
171 // also update the R600Op3OperandIndex::ROI enum in R600Defines.h,
172 // R600InstrInfo::buildDefaultInstruction(), and
173 // R600InstrInfo::getOperandIdx().
174 class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
175 InstrItinClass itin = AnyALU> :
176 InstR600 <(outs R600_Reg32:$dst),
177 (ins REL:$dst_rel, CLAMP:$clamp,
178 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
179 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
180 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
181 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
182 BANK_SWIZZLE:$bank_swizzle),
183 !strconcat(" ", opName, "$clamp $last $dst$dst_rel, "
184 "$src0_neg$src0$src0_rel, "
185 "$src1_neg$src1$src1_rel, "
186 "$src2_neg$src2$src2_rel, "
192 R600ALU_Word1_OP3<inst>{
194 let HasNativeOperands = 1;
195 let DisableEncoding = "$literal";
197 let UseNamedOperandTable = 1;
200 let Inst{31-0} = Word0;
201 let Inst{63-32} = Word1;
204 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
205 InstrItinClass itin = VecALU> :
206 InstR600 <(outs R600_Reg32:$dst),
214 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
216 def TEX_SHADOW : PatLeaf<
218 [{uint32_t TType = (uint32_t)N->getZExtValue();
219 return (TType >= 6 && TType <= 8) || (TType >= 11 && TType <= 13);
223 def TEX_RECT : PatLeaf<
225 [{uint32_t TType = (uint32_t)N->getZExtValue();
230 def TEX_ARRAY : PatLeaf<
232 [{uint32_t TType = (uint32_t)N->getZExtValue();
233 return TType == 9 || TType == 10 || TType == 15 || TType == 16;
237 def TEX_SHADOW_ARRAY : PatLeaf<
239 [{uint32_t TType = (uint32_t)N->getZExtValue();
240 return TType == 11 || TType == 12 || TType == 17;
244 class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> mask, dag outs,
245 dag ins, string asm, list<dag> pattern> :
246 InstR600ISA <outs, ins, asm, pattern>,
247 CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF {
250 let rat_inst = ratinst;
252 // XXX: Have a separate instruction for non-indexed writes.
258 let comp_mask = mask;
261 let cf_inst = cfinst;
265 let Inst{31-0} = Word0;
266 let Inst{63-32} = Word1;
270 class VTX_READ <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
271 : InstR600ISA <outs, (ins MEMxi:$src_gpr), name, pattern>,
276 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
277 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
278 // however, based on my testing if USE_CONST_FIELDS is set, then all
279 // these fields need to be set to 0.
280 let USE_CONST_FIELDS = 0;
281 let NUM_FORMAT_ALL = 1;
282 let FORMAT_COMP_ALL = 0;
283 let SRF_MODE_ALL = 0;
285 let Inst{63-32} = Word1;
286 // LLVM can only encode 64-bit instructions, so these fields are manually
287 // encoded in R600CodeEmitter
290 // bits<2> ENDIAN_SWAP = 0;
291 // bits<1> CONST_BUF_NO_STRIDE = 0;
292 // bits<1> MEGA_FETCH = 0;
293 // bits<1> ALT_CONST = 0;
294 // bits<2> BUFFER_INDEX_MODE = 0;
296 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
297 // is done in R600CodeEmitter
299 // Inst{79-64} = OFFSET;
300 // Inst{81-80} = ENDIAN_SWAP;
301 // Inst{82} = CONST_BUF_NO_STRIDE;
302 // Inst{83} = MEGA_FETCH;
303 // Inst{84} = ALT_CONST;
304 // Inst{86-85} = BUFFER_INDEX_MODE;
305 // Inst{95-86} = 0; Reserved
307 // VTX_WORD3 (Padding)
314 class LoadParamFrag <PatFrag load_type> : PatFrag <
315 (ops node:$ptr), (load_type node:$ptr),
316 [{ return isParamLoad(dyn_cast<LoadSDNode>(N)); }]
319 def load_param : LoadParamFrag<load>;
320 def load_param_zexti8 : LoadParamFrag<zextloadi8>;
321 def load_param_zexti16 : LoadParamFrag<zextloadi16>;
323 def isR600 : Predicate<"Subtarget.getGeneration() <= AMDGPUSubtarget::R700">;
324 def isR700 : Predicate<"Subtarget.getGeneration() == AMDGPUSubtarget::R700">;
325 def isEG : Predicate<
326 "Subtarget.getGeneration() >= AMDGPUSubtarget::EVERGREEN && "
327 "Subtarget.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && "
328 "!Subtarget.hasCaymanISA()">;
330 def isCayman : Predicate<"Subtarget.hasCaymanISA()">;
331 def isEGorCayman : Predicate<"Subtarget.getGeneration() == "
332 "AMDGPUSubtarget::EVERGREEN"
333 "|| Subtarget.getGeneration() =="
334 "AMDGPUSubtarget::NORTHERN_ISLANDS">;
336 def isR600toCayman : Predicate<
337 "Subtarget.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">;
339 //===----------------------------------------------------------------------===//
341 //===----------------------------------------------------------------------===//
343 def INTERP_PAIR_XY : AMDGPUShaderInst <
344 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),
345 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
346 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
349 def INTERP_PAIR_ZW : AMDGPUShaderInst <
350 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),
351 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
352 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
355 def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS",
356 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>,
360 def DOT4 : SDNode<"AMDGPUISD::DOT4",
361 SDTypeProfile<1, 8, [SDTCisFP<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32>,
362 SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>,
363 SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>,
367 def COS_HW : SDNode<"AMDGPUISD::COS_HW",
368 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>
371 def SIN_HW : SDNode<"AMDGPUISD::SIN_HW",
372 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>
375 def TEXTURE_FETCH_Type : SDTypeProfile<1, 19, [SDTCisFP<0>]>;
377 def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>;
379 multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> {
380 def : Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR,
381 (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw),
382 (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz),
383 (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z),
384 (i32 imm:$DST_SEL_W),
385 (i32 imm:$RESOURCE_ID), (i32 imm:$SAMPLER_ID),
386 (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z),
387 (i32 imm:$COORD_TYPE_W)),
388 (inst R600_Reg128:$SRC_GPR,
389 imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw,
390 imm:$offsetx, imm:$offsety, imm:$offsetz,
391 imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z,
393 imm:$RESOURCE_ID, imm:$SAMPLER_ID,
394 imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z,
398 //===----------------------------------------------------------------------===//
399 // Interpolation Instructions
400 //===----------------------------------------------------------------------===//
402 def INTERP_VEC_LOAD : AMDGPUShaderInst <
403 (outs R600_Reg128:$dst),
405 "INTERP_LOAD $src0 : $dst",
408 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {
409 let bank_swizzle = 5;
412 def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> {
413 let bank_swizzle = 5;
416 def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
418 //===----------------------------------------------------------------------===//
419 // Export Instructions
420 //===----------------------------------------------------------------------===//
422 def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
424 def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
425 [SDNPHasChain, SDNPSideEffect]>;
428 field bits<32> Word0;
435 let Word0{12-0} = arraybase;
436 let Word0{14-13} = type;
437 let Word0{21-15} = gpr;
438 let Word0{22} = 0; // RW_REL
439 let Word0{29-23} = 0; // INDEX_GPR
440 let Word0{31-30} = elem_size;
443 class ExportSwzWord1 {
444 field bits<32> Word1;
453 let Word1{2-0} = sw_x;
454 let Word1{5-3} = sw_y;
455 let Word1{8-6} = sw_z;
456 let Word1{11-9} = sw_w;
459 class ExportBufWord1 {
460 field bits<32> Word1;
467 let Word1{11-0} = arraySize;
468 let Word1{15-12} = compMask;
471 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
472 def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg),
474 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
475 0, 61, 0, 7, 7, 7, cf_inst, 0)
478 def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg),
480 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
481 0, 61, 7, 0, 7, 7, cf_inst, 0)
484 def : Pat<(int_R600_store_dummy (i32 imm:$type)),
486 (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
489 def : Pat<(int_R600_store_dummy 1),
491 (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
494 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
495 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
496 (ExportInst R600_Reg128:$src, imm:$type, imm:$base,
497 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)
502 multiclass SteamOutputExportPattern<Instruction ExportInst,
503 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
505 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
506 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),
507 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
508 4095, imm:$mask, buf0inst, 0)>;
510 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
511 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),
512 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
513 4095, imm:$mask, buf1inst, 0)>;
515 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
516 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),
517 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
518 4095, imm:$mask, buf2inst, 0)>;
520 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
521 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),
522 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
523 4095, imm:$mask, buf3inst, 0)>;
526 // Export Instructions should not be duplicated by TailDuplication pass
527 // (which assumes that duplicable instruction are affected by exec mask)
528 let usesCustomInserter = 1, isNotDuplicable = 1 in {
530 class ExportSwzInst : InstR600ISA<(
532 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
533 RSel:$sw_x, RSel:$sw_y, RSel:$sw_z, RSel:$sw_w, i32imm:$inst,
535 !strconcat("EXPORT", " $gpr.$sw_x$sw_y$sw_z$sw_w"),
536 []>, ExportWord0, ExportSwzWord1 {
538 let Inst{31-0} = Word0;
539 let Inst{63-32} = Word1;
542 } // End usesCustomInserter = 1
544 class ExportBufInst : InstR600ISA<(
546 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
547 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop),
548 !strconcat("EXPORT", " $gpr"),
549 []>, ExportWord0, ExportBufWord1 {
551 let Inst{31-0} = Word0;
552 let Inst{63-32} = Word1;
555 //===----------------------------------------------------------------------===//
556 // Control Flow Instructions
557 //===----------------------------------------------------------------------===//
560 def KCACHE : InstFlag<"printKCache">;
562 class ALU_CLAUSE<bits<4> inst, string OpName> : AMDGPUInst <(outs),
563 (ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1,
564 KCACHE:$KCACHE_MODE0, KCACHE:$KCACHE_MODE1,
565 i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1,
566 i32imm:$COUNT, i32imm:$Enabled),
567 !strconcat(OpName, " $COUNT, @$ADDR, "
568 "KC0[$KCACHE_MODE0], KC1[$KCACHE_MODE1]"),
569 [] >, CF_ALU_WORD0, CF_ALU_WORD1 {
574 let WHOLE_QUAD_MODE = 0;
577 let Inst{31-0} = Word0;
578 let Inst{63-32} = Word1;
581 class CF_WORD0_R600 {
582 field bits<32> Word0;
589 class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
590 ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 {
597 let VALID_PIXEL_MODE = 0;
599 let COUNT = CNT{2-0};
601 let COUNT_3 = CNT{3};
602 let END_OF_PROGRAM = 0;
603 let WHOLE_QUAD_MODE = 0;
605 let Inst{31-0} = Word0;
606 let Inst{63-32} = Word1;
609 class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
610 ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG {
615 let JUMPTABLE_SEL = 0;
617 let VALID_PIXEL_MODE = 0;
619 let END_OF_PROGRAM = 0;
621 let Inst{31-0} = Word0;
622 let Inst{63-32} = Word1;
625 def CF_ALU : ALU_CLAUSE<8, "ALU">;
626 def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">;
628 def FETCH_CLAUSE : AMDGPUInst <(outs),
629 (ins i32imm:$addr), "Fetch clause starting at $addr:", [] > {
635 def ALU_CLAUSE : AMDGPUInst <(outs),
636 (ins i32imm:$addr), "ALU clause starting at $addr:", [] > {
642 def LITERALS : AMDGPUInst <(outs),
643 (ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > {
648 let Inst{31-0} = literal1;
649 let Inst{63-32} = literal2;
652 def PAD : AMDGPUInst <(outs), (ins), "PAD", [] > {
656 let Predicates = [isR600toCayman] in {
658 //===----------------------------------------------------------------------===//
659 // Common Instructions R600, R700, Evergreen, Cayman
660 //===----------------------------------------------------------------------===//
662 def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;
663 // Non-IEEE MUL: 0 * anything = 0
664 def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>;
665 def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
666 def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax>;
667 def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin>;
669 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
670 // so some of the instruction names don't match the asm string.
671 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
672 def SETE : R600_2OP <
674 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_EQ))]
679 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_GT))]
684 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_GE))]
689 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_NE))]
692 def SETE_DX10 : R600_2OP <
694 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_EQ))]
697 def SETGT_DX10 : R600_2OP <
699 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_GT))]
702 def SETGE_DX10 : R600_2OP <
704 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_GE))]
707 def SETNE_DX10 : R600_2OP <
709 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_NE))]
712 def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;
713 def TRUNC : R600_1OP_Helper <0x11, "TRUNC", int_AMDGPU_trunc>;
714 def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
715 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
716 def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
718 def MOV : R600_1OP <0x19, "MOV", []>;
720 let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
722 class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst <
723 (outs R600_Reg32:$dst),
729 } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1
731 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
734 (MOV_IMM_I32 imm:$val)
737 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
740 (MOV_IMM_F32 fpimm:$val)
743 def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>;
744 def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>;
745 def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>;
746 def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>;
748 let hasSideEffects = 1 in {
750 def KILLGT : R600_2OP <0x2D, "KILLGT", []>;
752 } // end hasSideEffects
754 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
755 def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;
756 def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;
757 def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;
758 def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;
759 def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;
760 def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>;
761 def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>;
762 def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUumax>;
763 def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>;
765 def SETE_INT : R600_2OP <
767 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETEQ))]
770 def SETGT_INT : R600_2OP <
772 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))]
775 def SETGE_INT : R600_2OP <
777 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))]
780 def SETNE_INT : R600_2OP <
782 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))]
785 def SETGT_UINT : R600_2OP <
787 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))]
790 def SETGE_UINT : R600_2OP <
792 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))]
795 def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>;
796 def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>;
797 def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>;
798 def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>;
800 def CNDE_INT : R600_3OP <
802 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_EQ))]
805 def CNDGE_INT : R600_3OP <
807 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_GE))]
810 def CNDGT_INT : R600_3OP <
812 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_GT))]
815 //===----------------------------------------------------------------------===//
816 // Texture instructions
817 //===----------------------------------------------------------------------===//
819 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
821 class R600_TEX <bits<11> inst, string opName> :
822 InstR600 <(outs R600_Reg128:$DST_GPR),
823 (ins R600_Reg128:$SRC_GPR,
824 RSel:$srcx, RSel:$srcy, RSel:$srcz, RSel:$srcw,
825 i32imm:$offsetx, i32imm:$offsety, i32imm:$offsetz,
826 RSel:$DST_SEL_X, RSel:$DST_SEL_Y, RSel:$DST_SEL_Z, RSel:$DST_SEL_W,
827 i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID,
828 CT:$COORD_TYPE_X, CT:$COORD_TYPE_Y, CT:$COORD_TYPE_Z,
831 " $DST_GPR.$DST_SEL_X$DST_SEL_Y$DST_SEL_Z$DST_SEL_W, "
832 "$SRC_GPR.$srcx$srcy$srcz$srcw "
833 "RID:$RESOURCE_ID SID:$SAMPLER_ID "
834 "CT:$COORD_TYPE_X$COORD_TYPE_Y$COORD_TYPE_Z$COORD_TYPE_W"),
836 NullALU>, TEX_WORD0, TEX_WORD1, TEX_WORD2 {
837 let Inst{31-0} = Word0;
838 let Inst{63-32} = Word1;
840 let TEX_INST = inst{4-0};
846 let FETCH_WHOLE_QUAD = 0;
848 let SAMPLER_INDEX_MODE = 0;
849 let RESOURCE_INDEX_MODE = 0;
854 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
858 def TEX_SAMPLE : R600_TEX <0x10, "TEX_SAMPLE">;
859 def TEX_SAMPLE_C : R600_TEX <0x18, "TEX_SAMPLE_C">;
860 def TEX_SAMPLE_L : R600_TEX <0x11, "TEX_SAMPLE_L">;
861 def TEX_SAMPLE_C_L : R600_TEX <0x19, "TEX_SAMPLE_C_L">;
862 def TEX_SAMPLE_LB : R600_TEX <0x12, "TEX_SAMPLE_LB">;
863 def TEX_SAMPLE_C_LB : R600_TEX <0x1A, "TEX_SAMPLE_C_LB">;
864 def TEX_LD : R600_TEX <0x03, "TEX_LD">;
865 def TEX_GET_TEXTURE_RESINFO : R600_TEX <0x04, "TEX_GET_TEXTURE_RESINFO">;
866 def TEX_GET_GRADIENTS_H : R600_TEX <0x07, "TEX_GET_GRADIENTS_H">;
867 def TEX_GET_GRADIENTS_V : R600_TEX <0x08, "TEX_GET_GRADIENTS_V">;
868 def TEX_SET_GRADIENTS_H : R600_TEX <0x0B, "TEX_SET_GRADIENTS_H">;
869 def TEX_SET_GRADIENTS_V : R600_TEX <0x0C, "TEX_SET_GRADIENTS_V">;
870 def TEX_SAMPLE_G : R600_TEX <0x14, "TEX_SAMPLE_G">;
871 def TEX_SAMPLE_C_G : R600_TEX <0x1C, "TEX_SAMPLE_C_G">;
873 defm : TexPattern<0, TEX_SAMPLE>;
874 defm : TexPattern<1, TEX_SAMPLE_C>;
875 defm : TexPattern<2, TEX_SAMPLE_L>;
876 defm : TexPattern<3, TEX_SAMPLE_C_L>;
877 defm : TexPattern<4, TEX_SAMPLE_LB>;
878 defm : TexPattern<5, TEX_SAMPLE_C_LB>;
879 defm : TexPattern<6, TEX_LD, v4i32>;
880 defm : TexPattern<7, TEX_GET_TEXTURE_RESINFO, v4i32>;
881 defm : TexPattern<8, TEX_GET_GRADIENTS_H>;
882 defm : TexPattern<9, TEX_GET_GRADIENTS_V>;
884 //===----------------------------------------------------------------------===//
885 // Helper classes for common instructions
886 //===----------------------------------------------------------------------===//
888 class MUL_LIT_Common <bits<5> inst> : R600_3OP <
893 class MULADD_Common <bits<5> inst> : R600_3OP <
898 class MULADD_IEEE_Common <bits<5> inst> : R600_3OP <
900 [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))]
903 class CNDE_Common <bits<5> inst> : R600_3OP <
905 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_EQ))]
908 class CNDGT_Common <bits<5> inst> : R600_3OP <
910 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_GT))]
913 class CNDGE_Common <bits<5> inst> : R600_3OP <
915 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_GE))]
919 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
920 class R600_VEC2OP<list<dag> pattern> : InstR600 <(outs R600_Reg32:$dst), (ins
922 UEM:$update_exec_mask_X, UP:$update_pred_X, WRITE:$write_X,
923 OMOD:$omod_X, REL:$dst_rel_X, CLAMP:$clamp_X,
924 R600_TReg32_X:$src0_X, NEG:$src0_neg_X, REL:$src0_rel_X, ABS:$src0_abs_X, SEL:$src0_sel_X,
925 R600_TReg32_X:$src1_X, NEG:$src1_neg_X, REL:$src1_rel_X, ABS:$src1_abs_X, SEL:$src1_sel_X,
926 R600_Pred:$pred_sel_X,
928 UEM:$update_exec_mask_Y, UP:$update_pred_Y, WRITE:$write_Y,
929 OMOD:$omod_Y, REL:$dst_rel_Y, CLAMP:$clamp_Y,
930 R600_TReg32_Y:$src0_Y, NEG:$src0_neg_Y, REL:$src0_rel_Y, ABS:$src0_abs_Y, SEL:$src0_sel_Y,
931 R600_TReg32_Y:$src1_Y, NEG:$src1_neg_Y, REL:$src1_rel_Y, ABS:$src1_abs_Y, SEL:$src1_sel_Y,
932 R600_Pred:$pred_sel_Y,
934 UEM:$update_exec_mask_Z, UP:$update_pred_Z, WRITE:$write_Z,
935 OMOD:$omod_Z, REL:$dst_rel_Z, CLAMP:$clamp_Z,
936 R600_TReg32_Z:$src0_Z, NEG:$src0_neg_Z, REL:$src0_rel_Z, ABS:$src0_abs_Z, SEL:$src0_sel_Z,
937 R600_TReg32_Z:$src1_Z, NEG:$src1_neg_Z, REL:$src1_rel_Z, ABS:$src1_abs_Z, SEL:$src1_sel_Z,
938 R600_Pred:$pred_sel_Z,
940 UEM:$update_exec_mask_W, UP:$update_pred_W, WRITE:$write_W,
941 OMOD:$omod_W, REL:$dst_rel_W, CLAMP:$clamp_W,
942 R600_TReg32_W:$src0_W, NEG:$src0_neg_W, REL:$src0_rel_W, ABS:$src0_abs_W, SEL:$src0_sel_W,
943 R600_TReg32_W:$src1_W, NEG:$src1_neg_W, REL:$src1_rel_W, ABS:$src1_abs_W, SEL:$src1_sel_W,
944 R600_Pred:$pred_sel_W,
945 LITERAL:$literal0, LITERAL:$literal1),
950 let UseNamedOperandTable = 1;
955 def DOT_4 : R600_VEC2OP<[(set R600_Reg32:$dst, (DOT4
956 R600_TReg32_X:$src0_X, R600_TReg32_X:$src1_X,
957 R600_TReg32_Y:$src0_Y, R600_TReg32_Y:$src1_Y,
958 R600_TReg32_Z:$src0_Z, R600_TReg32_Z:$src1_Z,
959 R600_TReg32_W:$src0_W, R600_TReg32_W:$src1_W))]>;
962 class DOT4_Common <bits<11> inst> : R600_2OP <inst, "DOT4", []>;
965 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
966 multiclass CUBE_Common <bits<11> inst> {
968 def _pseudo : InstR600 <
969 (outs R600_Reg128:$dst),
970 (ins R600_Reg128:$src0),
972 [(set v4f32:$dst, (int_AMDGPU_cube v4f32:$src0))],
976 let UseNamedOperandTable = 1;
979 def _real : R600_2OP <inst, "CUBE", []>;
981 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
983 class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
984 inst, "EXP_IEEE", fexp2
987 let Itinerary = TransALU;
990 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper <
991 inst, "FLT_TO_INT", fp_to_sint
994 let Itinerary = TransALU;
997 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
998 inst, "INT_TO_FLT", sint_to_fp
1001 let Itinerary = TransALU;
1004 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1005 inst, "FLT_TO_UINT", fp_to_uint
1008 let Itinerary = TransALU;
1011 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1012 inst, "UINT_TO_FLT", uint_to_fp
1015 let Itinerary = TransALU;
1018 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
1019 inst, "LOG_CLAMPED", []
1022 class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1023 inst, "LOG_IEEE", flog2
1026 let Itinerary = TransALU;
1029 class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;
1030 class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;
1031 class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;
1032 class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <
1033 inst, "MULHI_INT", mulhs
1036 let Itinerary = TransALU;
1038 class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <
1039 inst, "MULHI", mulhu
1042 let Itinerary = TransALU;
1044 class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <
1045 inst, "MULLO_INT", mul
1048 let Itinerary = TransALU;
1050 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []> {
1052 let Itinerary = TransALU;
1055 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
1056 inst, "RECIP_CLAMPED", []
1059 let Itinerary = TransALU;
1062 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
1063 inst, "RECIP_IEEE", [(set f32:$dst, (fdiv FP_ONE, f32:$src0))]
1066 let Itinerary = TransALU;
1069 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1070 inst, "RECIP_UINT", AMDGPUurecip
1073 let Itinerary = TransALU;
1076 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <
1077 inst, "RECIPSQRT_CLAMPED", int_AMDGPU_rsq
1080 let Itinerary = TransALU;
1083 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP <
1084 inst, "RECIPSQRT_IEEE", []
1087 let Itinerary = TransALU;
1090 class SIN_Common <bits<11> inst> : R600_1OP <
1091 inst, "SIN", [(set f32:$dst, (SIN_HW f32:$src0))]>{
1094 let Itinerary = TransALU;
1097 class COS_Common <bits<11> inst> : R600_1OP <
1098 inst, "COS", [(set f32:$dst, (COS_HW f32:$src0))]> {
1101 let Itinerary = TransALU;
1104 //===----------------------------------------------------------------------===//
1105 // Helper patterns for complex intrinsics
1106 //===----------------------------------------------------------------------===//
1108 multiclass DIV_Common <InstR600 recip_ieee> {
1110 (int_AMDGPU_div f32:$src0, f32:$src1),
1111 (MUL_IEEE $src0, (recip_ieee $src1))
1115 (fdiv f32:$src0, f32:$src1),
1116 (MUL_IEEE $src0, (recip_ieee $src1))
1120 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee>
1122 (int_TGSI_lit_z f32:$src_x, f32:$src_y, f32:$src_w),
1123 (exp_ieee (mul_lit (log_clamped (MAX $src_y, (f32 ZERO))), $src_w, $src_x))
1126 //===----------------------------------------------------------------------===//
1127 // R600 / R700 Instructions
1128 //===----------------------------------------------------------------------===//
1130 let Predicates = [isR600] in {
1132 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
1133 def MULADD_r600 : MULADD_Common<0x10>;
1134 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>;
1135 def CNDE_r600 : CNDE_Common<0x18>;
1136 def CNDGT_r600 : CNDGT_Common<0x19>;
1137 def CNDGE_r600 : CNDGE_Common<0x1A>;
1138 def DOT4_r600 : DOT4_Common<0x50>;
1139 defm CUBE_r600 : CUBE_Common<0x52>;
1140 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
1141 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
1142 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
1143 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
1144 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
1145 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
1146 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
1147 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
1148 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
1149 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
1150 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
1151 def SIN_r600 : SIN_Common<0x6E>;
1152 def COS_r600 : COS_Common<0x6F>;
1153 def ASHR_r600 : ASHR_Common<0x70>;
1154 def LSHR_r600 : LSHR_Common<0x71>;
1155 def LSHL_r600 : LSHL_Common<0x72>;
1156 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
1157 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
1158 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
1159 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
1160 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
1162 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
1163 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>;
1164 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
1166 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>;
1168 def R600_ExportSwz : ExportSwzInst {
1169 let Word1{20-17} = 0; // BURST_COUNT
1170 let Word1{21} = eop;
1171 let Word1{22} = 1; // VALID_PIXEL_MODE
1172 let Word1{30-23} = inst;
1173 let Word1{31} = 1; // BARRIER
1175 defm : ExportPattern<R600_ExportSwz, 39>;
1177 def R600_ExportBuf : ExportBufInst {
1178 let Word1{20-17} = 0; // BURST_COUNT
1179 let Word1{21} = eop;
1180 let Word1{22} = 1; // VALID_PIXEL_MODE
1181 let Word1{30-23} = inst;
1182 let Word1{31} = 1; // BARRIER
1184 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>;
1186 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$CNT),
1187 "TEX $CNT @$ADDR"> {
1190 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$CNT),
1191 "VTX $CNT @$ADDR"> {
1194 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR),
1195 "LOOP_START_DX10 @$ADDR"> {
1199 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1203 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR),
1204 "LOOP_BREAK @$ADDR"> {
1208 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR),
1209 "CONTINUE @$ADDR"> {
1213 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1214 "JUMP @$ADDR POP:$POP_COUNT"> {
1217 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1218 "ELSE @$ADDR POP:$POP_COUNT"> {
1221 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> {
1226 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1227 "POP @$ADDR POP:$POP_COUNT"> {
1230 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> {
1234 let END_OF_PROGRAM = 1;
1239 //===----------------------------------------------------------------------===//
1240 // R700 Only instructions
1241 //===----------------------------------------------------------------------===//
1243 let Predicates = [isR700] in {
1244 def SIN_r700 : SIN_Common<0x6E>;
1245 def COS_r700 : COS_Common<0x6F>;
1248 //===----------------------------------------------------------------------===//
1249 // Evergreen Only instructions
1250 //===----------------------------------------------------------------------===//
1252 let Predicates = [isEG] in {
1254 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
1255 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
1257 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
1258 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
1259 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
1260 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
1261 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
1262 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
1263 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
1264 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
1265 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
1266 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
1267 def SIN_eg : SIN_Common<0x8D>;
1268 def COS_eg : COS_Common<0x8E>;
1270 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>;
1271 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>;
1273 //===----------------------------------------------------------------------===//
1274 // Memory read/write instructions
1275 //===----------------------------------------------------------------------===//
1276 let usesCustomInserter = 1 in {
1278 class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> mask, string name,
1280 : EG_CF_RAT <0x57, 0x2, mask, (outs), ins, name, pattern> {
1283 } // End usesCustomInserter = 1
1286 def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
1287 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1288 0x1, "RAT_WRITE_CACHELESS_32_eg $rw_gpr, $index_gpr, $eop",
1289 [(global_store i32:$rw_gpr, i32:$index_gpr)]
1293 def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
1294 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1295 0xf, "RAT_WRITE_CACHELESS_128 $rw_gpr.XYZW, $index_gpr, $eop",
1296 [(global_store v4i32:$rw_gpr, i32:$index_gpr)]
1299 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
1300 : VTX_WORD0_eg, VTX_READ<name, buffer_id, outs, pattern> {
1305 let FETCH_WHOLE_QUAD = 0;
1306 let BUFFER_ID = buffer_id;
1308 // XXX: We can infer this field based on the SRC_GPR. This would allow us
1309 // to store vertex addresses in any channel, not just X.
1312 let Inst{31-0} = Word0;
1315 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
1316 : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
1317 (outs R600_TReg32_X:$dst_gpr), pattern> {
1319 let MEGA_FETCH_COUNT = 1;
1321 let DST_SEL_Y = 7; // Masked
1322 let DST_SEL_Z = 7; // Masked
1323 let DST_SEL_W = 7; // Masked
1324 let DATA_FORMAT = 1; // FMT_8
1327 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
1328 : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
1329 (outs R600_TReg32_X:$dst_gpr), pattern> {
1330 let MEGA_FETCH_COUNT = 2;
1332 let DST_SEL_Y = 7; // Masked
1333 let DST_SEL_Z = 7; // Masked
1334 let DST_SEL_W = 7; // Masked
1335 let DATA_FORMAT = 5; // FMT_16
1339 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
1340 : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
1341 (outs R600_TReg32_X:$dst_gpr), pattern> {
1343 let MEGA_FETCH_COUNT = 4;
1345 let DST_SEL_Y = 7; // Masked
1346 let DST_SEL_Z = 7; // Masked
1347 let DST_SEL_W = 7; // Masked
1348 let DATA_FORMAT = 0xD; // COLOR_32
1350 // This is not really necessary, but there were some GPU hangs that appeared
1351 // to be caused by ALU instructions in the next instruction group that wrote
1352 // to the $src_gpr registers of the VTX_READ.
1354 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
1355 // %T2_X<def> = MOV %ZERO
1356 //Adding this constraint prevents this from happening.
1357 let Constraints = "$src_gpr.ptr = $dst_gpr";
1360 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
1361 : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
1362 (outs R600_Reg128:$dst_gpr), pattern> {
1364 let MEGA_FETCH_COUNT = 16;
1369 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1371 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1372 // that holds its buffer address to avoid potential hangs. We can't use
1373 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
1374 // registers are different sizes.
1377 //===----------------------------------------------------------------------===//
1378 // VTX Read from parameter memory space
1379 //===----------------------------------------------------------------------===//
1381 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0,
1382 [(set i32:$dst_gpr, (load_param_zexti8 ADDRVTX_READ:$src_gpr))]
1385 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0,
1386 [(set i32:$dst_gpr, (load_param_zexti16 ADDRVTX_READ:$src_gpr))]
1389 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0,
1390 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1393 def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0,
1394 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1397 //===----------------------------------------------------------------------===//
1398 // VTX Read from global memory space
1399 //===----------------------------------------------------------------------===//
1402 def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1,
1403 [(set i32:$dst_gpr, (zextloadi8_global ADDRVTX_READ:$src_gpr))]
1407 def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1,
1408 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1412 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
1413 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1416 //===----------------------------------------------------------------------===//
1418 // XXX: We are currently storing all constants in the global address space.
1419 //===----------------------------------------------------------------------===//
1421 def CONSTANT_LOAD_eg : VTX_READ_32_eg <1,
1422 [(set i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))]
1426 } // End Predicates = [isEG]
1428 //===----------------------------------------------------------------------===//
1429 // Evergreen / Cayman Instructions
1430 //===----------------------------------------------------------------------===//
1432 let Predicates = [isEGorCayman] in {
1434 // BFE_UINT - bit_extract, an optimization for mask and shift
1439 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
1444 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
1445 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
1446 // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
1447 // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
1448 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
1449 [(set i32:$dst, (int_AMDIL_bit_extract_u32 i32:$src0, i32:$src1,
1453 def : BFEPattern <BFE_UINT_eg>;
1455 def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", [], VecALU>;
1456 defm : BFIPatterns <BFI_INT_eg>;
1458 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>;
1459 def : ROTRPattern <BIT_ALIGN_INT_eg>;
1461 def MULADD_eg : MULADD_Common<0x14>;
1462 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
1463 def ASHR_eg : ASHR_Common<0x15>;
1464 def LSHR_eg : LSHR_Common<0x16>;
1465 def LSHL_eg : LSHL_Common<0x17>;
1466 def CNDE_eg : CNDE_Common<0x19>;
1467 def CNDGT_eg : CNDGT_Common<0x1A>;
1468 def CNDGE_eg : CNDGE_Common<0x1B>;
1469 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
1470 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
1471 def DOT4_eg : DOT4_Common<0xBE>;
1472 defm CUBE_eg : CUBE_Common<0xC0>;
1474 let hasSideEffects = 1 in {
1475 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", []>;
1478 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
1480 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
1483 let Itinerary = AnyALU;
1486 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
1488 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
1492 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
1494 def GROUP_BARRIER : InstR600 <
1495 (outs), (ins), " GROUP_BARRIER", [(int_AMDGPU_barrier_local)], AnyALU>,
1497 R600ALU_Word1_OP2 <0x54> {
1513 let bank_swizzle = 0;
1515 let update_exec_mask = 0;
1516 let update_pred = 0;
1518 let Inst{31-0} = Word0;
1519 let Inst{63-32} = Word1;
1524 //===----------------------------------------------------------------------===//
1526 //===----------------------------------------------------------------------===//
1527 class R600_LDS <bits<6> op, dag outs, dag ins, string asm,
1528 list<dag> pattern = []> :
1530 InstR600 <outs, ins, asm, pattern, XALU>,
1537 let Word1{27} = offset{0};
1538 let Word1{12} = offset{1};
1539 let Word1{28} = offset{2};
1540 let Word1{31} = offset{3};
1541 let Word0{12} = offset{4};
1542 let Word0{25} = offset{5};
1545 let Inst{31-0} = Word0;
1546 let Inst{63-32} = Word1;
1549 let HasNativeOperands = 1;
1550 let UseNamedOperandTable = 1;
1553 class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS <
1555 (outs R600_Reg32:$dst),
1556 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
1557 LAST:$last, R600_Pred:$pred_sel,
1558 BANK_SWIZZLE:$bank_swizzle),
1559 " "#name#" $last OQAP, $src0$src0_rel $pred_sel",
1569 let usesCustomInserter = 1;
1571 let DisableEncoding = "$dst";
1574 class R600_LDS_1A1D <bits<6> lds_op, string name, list<dag> pattern> :
1578 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
1579 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
1580 LAST:$last, R600_Pred:$pred_sel,
1581 BANK_SWIZZLE:$bank_swizzle),
1582 " "#name#" $last $src0$src0_rel, $src1$src1_rel, $pred_sel",
1591 def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET",
1592 [(set (i32 R600_Reg32:$dst), (local_load R600_Reg32:$src0))]
1595 def LDS_WRITE : R600_LDS_1A1D <0xD, "LDS_WRITE",
1596 [(local_store (i32 R600_Reg32:$src1), R600_Reg32:$src0)]
1599 // TRUNC is used for the FLT_TO_INT instructions to work around a
1600 // perceived problem where the rounding modes are applied differently
1601 // depending on the instruction and the slot they are in.
1603 // https://bugs.freedesktop.org/show_bug.cgi?id=50232
1604 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
1606 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
1607 // which do not need to be truncated since the fp values are 0.0f or 1.0f.
1608 // We should look into handling these cases separately.
1609 def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>;
1611 def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>;
1614 def : SHA256MaPattern <BFI_INT_eg, XOR_INT>;
1616 def EG_ExportSwz : ExportSwzInst {
1617 let Word1{19-16} = 0; // BURST_COUNT
1618 let Word1{20} = 1; // VALID_PIXEL_MODE
1619 let Word1{21} = eop;
1620 let Word1{29-22} = inst;
1621 let Word1{30} = 0; // MARK
1622 let Word1{31} = 1; // BARRIER
1624 defm : ExportPattern<EG_ExportSwz, 83>;
1626 def EG_ExportBuf : ExportBufInst {
1627 let Word1{19-16} = 0; // BURST_COUNT
1628 let Word1{20} = 1; // VALID_PIXEL_MODE
1629 let Word1{21} = eop;
1630 let Word1{29-22} = inst;
1631 let Word1{30} = 0; // MARK
1632 let Word1{31} = 1; // BARRIER
1634 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
1636 def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),
1637 "TEX $COUNT @$ADDR"> {
1640 def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),
1641 "VTX $COUNT @$ADDR"> {
1644 def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),
1645 "LOOP_START_DX10 @$ADDR"> {
1649 def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1653 def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),
1654 "LOOP_BREAK @$ADDR"> {
1658 def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),
1659 "CONTINUE @$ADDR"> {
1663 def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1664 "JUMP @$ADDR POP:$POP_COUNT"> {
1667 def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1668 "ELSE @$ADDR POP:$POP_COUNT"> {
1671 def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> {
1676 def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1677 "POP @$ADDR POP:$POP_COUNT"> {
1680 def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> {
1684 let END_OF_PROGRAM = 1;
1687 } // End Predicates = [isEGorCayman]
1689 //===----------------------------------------------------------------------===//
1690 // Regist loads and stores - for indirect addressing
1691 //===----------------------------------------------------------------------===//
1693 defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;
1695 //===----------------------------------------------------------------------===//
1696 // Cayman Instructions
1697 //===----------------------------------------------------------------------===//
1699 let Predicates = [isCayman] in {
1701 let isVector = 1 in {
1703 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
1705 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
1706 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
1707 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
1708 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
1709 def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
1710 def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
1711 def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;
1712 def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
1713 def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
1714 def SIN_cm : SIN_Common<0x8D>;
1715 def COS_cm : COS_Common<0x8E>;
1716 } // End isVector = 1
1718 def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>;
1720 defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
1722 // RECIP_UINT emulation for Cayman
1723 // The multiplication scales from [0,1] to the unsigned integer range
1725 (AMDGPUurecip i32:$src0),
1726 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)),
1727 (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1)))
1730 def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> {
1736 def : Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>;
1739 def RAT_STORE_DWORD_cm : EG_CF_RAT <
1740 0x57, 0x14, 0x1, (outs),
1741 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr),
1742 "EXPORT_RAT_INST_STORE_DWORD $rw_gpr, $index_gpr",
1743 [(global_store i32:$rw_gpr, i32:$index_gpr)]
1745 let eop = 0; // This bit is not used on Cayman.
1748 class VTX_READ_cm <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
1749 : VTX_WORD0_cm, VTX_READ<name, buffer_id, outs, pattern> {
1754 let FETCH_WHOLE_QUAD = 0;
1755 let BUFFER_ID = buffer_id;
1757 // XXX: We can infer this field based on the SRC_GPR. This would allow us
1758 // to store vertex addresses in any channel, not just X.
1761 let STRUCTURED_READ = 0;
1763 let COALESCED_READ = 0;
1765 let Inst{31-0} = Word0;
1768 class VTX_READ_8_cm <bits<8> buffer_id, list<dag> pattern>
1769 : VTX_READ_cm <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
1770 (outs R600_TReg32_X:$dst_gpr), pattern> {
1773 let DST_SEL_Y = 7; // Masked
1774 let DST_SEL_Z = 7; // Masked
1775 let DST_SEL_W = 7; // Masked
1776 let DATA_FORMAT = 1; // FMT_8
1779 class VTX_READ_16_cm <bits<8> buffer_id, list<dag> pattern>
1780 : VTX_READ_cm <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
1781 (outs R600_TReg32_X:$dst_gpr), pattern> {
1783 let DST_SEL_Y = 7; // Masked
1784 let DST_SEL_Z = 7; // Masked
1785 let DST_SEL_W = 7; // Masked
1786 let DATA_FORMAT = 5; // FMT_16
1790 class VTX_READ_32_cm <bits<8> buffer_id, list<dag> pattern>
1791 : VTX_READ_cm <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
1792 (outs R600_TReg32_X:$dst_gpr), pattern> {
1795 let DST_SEL_Y = 7; // Masked
1796 let DST_SEL_Z = 7; // Masked
1797 let DST_SEL_W = 7; // Masked
1798 let DATA_FORMAT = 0xD; // COLOR_32
1800 // This is not really necessary, but there were some GPU hangs that appeared
1801 // to be caused by ALU instructions in the next instruction group that wrote
1802 // to the $src_gpr registers of the VTX_READ.
1804 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
1805 // %T2_X<def> = MOV %ZERO
1806 //Adding this constraint prevents this from happening.
1807 let Constraints = "$src_gpr.ptr = $dst_gpr";
1810 class VTX_READ_128_cm <bits<8> buffer_id, list<dag> pattern>
1811 : VTX_READ_cm <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
1812 (outs R600_Reg128:$dst_gpr), pattern> {
1818 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1820 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1821 // that holds its buffer address to avoid potential hangs. We can't use
1822 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
1823 // registers are different sizes.
1826 //===----------------------------------------------------------------------===//
1827 // VTX Read from parameter memory space
1828 //===----------------------------------------------------------------------===//
1829 def VTX_READ_PARAM_8_cm : VTX_READ_8_cm <0,
1830 [(set i32:$dst_gpr, (load_param_zexti8 ADDRVTX_READ:$src_gpr))]
1833 def VTX_READ_PARAM_16_cm : VTX_READ_16_cm <0,
1834 [(set i32:$dst_gpr, (load_param_zexti16 ADDRVTX_READ:$src_gpr))]
1837 def VTX_READ_PARAM_32_cm : VTX_READ_32_cm <0,
1838 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1841 def VTX_READ_PARAM_128_cm : VTX_READ_128_cm <0,
1842 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1845 //===----------------------------------------------------------------------===//
1846 // VTX Read from global memory space
1847 //===----------------------------------------------------------------------===//
1850 def VTX_READ_GLOBAL_8_cm : VTX_READ_8_cm <1,
1851 [(set i32:$dst_gpr, (zextloadi8_global ADDRVTX_READ:$src_gpr))]
1855 def VTX_READ_GLOBAL_32_cm : VTX_READ_32_cm <1,
1856 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1860 def VTX_READ_GLOBAL_128_cm : VTX_READ_128_cm <1,
1861 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1864 //===----------------------------------------------------------------------===//
1866 // XXX: We are currently storing all constants in the global address space.
1867 //===----------------------------------------------------------------------===//
1869 def CONSTANT_LOAD_cm : VTX_READ_32_cm <1,
1870 [(set i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))]
1875 //===----------------------------------------------------------------------===//
1876 // Branch Instructions
1877 //===----------------------------------------------------------------------===//
1880 def IF_PREDICATE_SET : ILFormat<(outs), (ins GPRI32:$src),
1881 "IF_PREDICATE_SET $src", []>;
1883 def PREDICATED_BREAK : ILFormat<(outs), (ins GPRI32:$src),
1884 "PREDICATED_BREAK $src", []>;
1886 //===----------------------------------------------------------------------===//
1887 // Pseudo instructions
1888 //===----------------------------------------------------------------------===//
1890 let isPseudo = 1 in {
1892 def PRED_X : InstR600 <
1893 (outs R600_Predicate_Bit:$dst),
1894 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
1896 let FlagOperandIdx = 3;
1899 let isTerminator = 1, isBranch = 1 in {
1900 def JUMP_COND : InstR600 <
1902 (ins brtarget:$target, R600_Predicate_Bit:$p),
1903 "JUMP $target ($p)",
1907 def JUMP : InstR600 <
1909 (ins brtarget:$target),
1914 let isPredicable = 1;
1918 } // End isTerminator = 1, isBranch = 1
1920 let usesCustomInserter = 1 in {
1922 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
1924 def MASK_WRITE : AMDGPUShaderInst <
1926 (ins R600_Reg32:$src),
1931 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
1935 (outs R600_Reg128:$dst),
1936 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
1937 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1938 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1939 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2,
1940 imm:$resourceId, imm:$samplerId, imm:$textureTarget))],
1945 def TXD_SHADOW: InstR600 <
1946 (outs R600_Reg128:$dst),
1947 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
1948 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1949 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1950 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2,
1951 imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))],
1956 } // End isPseudo = 1
1957 } // End usesCustomInserter = 1
1959 def CLAMP_R600 : CLAMP <R600_Reg32>;
1960 def FABS_R600 : FABS<R600_Reg32>;
1961 def FNEG_R600 : FNEG<R600_Reg32>;
1963 //===---------------------------------------------------------------------===//
1964 // Return instruction
1965 //===---------------------------------------------------------------------===//
1966 let isTerminator = 1, isReturn = 1, hasCtrlDep = 1,
1967 usesCustomInserter = 1 in {
1968 def RETURN : ILFormat<(outs), (ins variable_ops),
1969 "RETURN", [(IL_retflag)]>;
1973 //===----------------------------------------------------------------------===//
1974 // Constant Buffer Addressing Support
1975 //===----------------------------------------------------------------------===//
1977 let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
1978 def CONST_COPY : Instruction {
1979 let OutOperandList = (outs R600_Reg32:$dst);
1980 let InOperandList = (ins i32imm:$src);
1982 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
1983 let AsmString = "CONST_COPY";
1984 let neverHasSideEffects = 1;
1985 let isAsCheapAsAMove = 1;
1986 let Itinerary = NullALU;
1988 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
1990 def TEX_VTX_CONSTBUF :
1991 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "VTX_READ_eg $dst, $ptr",
1992 [(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$BUFFER_ID)))]>,
1993 VTX_WORD1_GPR, VTX_WORD0_eg {
1997 let FETCH_WHOLE_QUAD = 0;
2001 let USE_CONST_FIELDS = 0;
2002 let NUM_FORMAT_ALL = 2;
2003 let FORMAT_COMP_ALL = 1;
2004 let SRF_MODE_ALL = 1;
2005 let MEGA_FETCH_COUNT = 16;
2010 let DATA_FORMAT = 35;
2012 let Inst{31-0} = Word0;
2013 let Inst{63-32} = Word1;
2015 // LLVM can only encode 64-bit instructions, so these fields are manually
2016 // encoded in R600CodeEmitter
2019 // bits<2> ENDIAN_SWAP = 0;
2020 // bits<1> CONST_BUF_NO_STRIDE = 0;
2021 // bits<1> MEGA_FETCH = 0;
2022 // bits<1> ALT_CONST = 0;
2023 // bits<2> BUFFER_INDEX_MODE = 0;
2027 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
2028 // is done in R600CodeEmitter
2030 // Inst{79-64} = OFFSET;
2031 // Inst{81-80} = ENDIAN_SWAP;
2032 // Inst{82} = CONST_BUF_NO_STRIDE;
2033 // Inst{83} = MEGA_FETCH;
2034 // Inst{84} = ALT_CONST;
2035 // Inst{86-85} = BUFFER_INDEX_MODE;
2036 // Inst{95-86} = 0; Reserved
2038 // VTX_WORD3 (Padding)
2040 // Inst{127-96} = 0;
2045 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr",
2046 [(set v4f32:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>,
2047 VTX_WORD1_GPR, VTX_WORD0_eg {
2051 let FETCH_WHOLE_QUAD = 0;
2055 let USE_CONST_FIELDS = 1;
2056 let NUM_FORMAT_ALL = 0;
2057 let FORMAT_COMP_ALL = 0;
2058 let SRF_MODE_ALL = 1;
2059 let MEGA_FETCH_COUNT = 16;
2064 let DATA_FORMAT = 0;
2066 let Inst{31-0} = Word0;
2067 let Inst{63-32} = Word1;
2069 // LLVM can only encode 64-bit instructions, so these fields are manually
2070 // encoded in R600CodeEmitter
2073 // bits<2> ENDIAN_SWAP = 0;
2074 // bits<1> CONST_BUF_NO_STRIDE = 0;
2075 // bits<1> MEGA_FETCH = 0;
2076 // bits<1> ALT_CONST = 0;
2077 // bits<2> BUFFER_INDEX_MODE = 0;
2081 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
2082 // is done in R600CodeEmitter
2084 // Inst{79-64} = OFFSET;
2085 // Inst{81-80} = ENDIAN_SWAP;
2086 // Inst{82} = CONST_BUF_NO_STRIDE;
2087 // Inst{83} = MEGA_FETCH;
2088 // Inst{84} = ALT_CONST;
2089 // Inst{86-85} = BUFFER_INDEX_MODE;
2090 // Inst{95-86} = 0; Reserved
2092 // VTX_WORD3 (Padding)
2094 // Inst{127-96} = 0;
2100 //===--------------------------------------------------------------------===//
2101 // Instructions support
2102 //===--------------------------------------------------------------------===//
2103 //===---------------------------------------------------------------------===//
2104 // Custom Inserter for Branches and returns, this eventually will be a
2106 //===---------------------------------------------------------------------===//
2107 let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
2108 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
2109 "; Pseudo unconditional branch instruction",
2111 defm BRANCH_COND : BranchConditional<IL_brcond>;
2114 //===---------------------------------------------------------------------===//
2115 // Flow and Program control Instructions
2116 //===---------------------------------------------------------------------===//
2117 let isTerminator=1 in {
2118 def SWITCH : ILFormat< (outs), (ins GPRI32:$src),
2119 !strconcat("SWITCH", " $src"), []>;
2120 def CASE : ILFormat< (outs), (ins GPRI32:$src),
2121 !strconcat("CASE", " $src"), []>;
2122 def BREAK : ILFormat< (outs), (ins),
2124 def CONTINUE : ILFormat< (outs), (ins),
2126 def DEFAULT : ILFormat< (outs), (ins),
2128 def ELSE : ILFormat< (outs), (ins),
2130 def ENDSWITCH : ILFormat< (outs), (ins),
2132 def ENDMAIN : ILFormat< (outs), (ins),
2134 def END : ILFormat< (outs), (ins),
2136 def ENDFUNC : ILFormat< (outs), (ins),
2138 def ENDIF : ILFormat< (outs), (ins),
2140 def WHILELOOP : ILFormat< (outs), (ins),
2142 def ENDLOOP : ILFormat< (outs), (ins),
2144 def FUNC : ILFormat< (outs), (ins),
2146 def RETDYN : ILFormat< (outs), (ins),
2148 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2149 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">;
2150 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2151 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">;
2152 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2153 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">;
2154 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2155 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">;
2156 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2157 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">;
2158 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2159 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">;
2160 defm IFC : BranchInstr2<"IFC">;
2161 defm BREAKC : BranchInstr2<"BREAKC">;
2162 defm CONTINUEC : BranchInstr2<"CONTINUEC">;
2165 //===----------------------------------------------------------------------===//
2167 //===----------------------------------------------------------------------===//
2169 // CND*_INT Pattterns for f32 True / False values
2171 class CND_INT_f32 <InstR600 cnd, CondCode cc> : Pat <
2172 (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc),
2173 (cnd $src0, $src1, $src2)
2176 def : CND_INT_f32 <CNDE_INT, SETEQ>;
2177 def : CND_INT_f32 <CNDGT_INT, SETGT>;
2178 def : CND_INT_f32 <CNDGE_INT, SETGE>;
2180 //CNDGE_INT extra pattern
2182 (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_GT),
2183 (CNDGE_INT $src0, $src1, $src2)
2189 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
2193 (int_AMDGPU_kill f32:$src0),
2194 (MASK_WRITE (KILLGT (f32 ZERO), $src0))
2199 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_LT),
2205 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_LE),
2209 // SETGT_DX10 reverse args
2211 (selectcc f32:$src0, f32:$src1, -1, 0, COND_LT),
2212 (SETGT_DX10 $src1, $src0)
2215 // SETGE_DX10 reverse args
2217 (selectcc f32:$src0, f32:$src1, -1, 0, COND_LE),
2218 (SETGE_DX10 $src1, $src0)
2221 // SETGT_INT reverse args
2223 (selectcc i32:$src0, i32:$src1, -1, 0, SETLT),
2224 (SETGT_INT $src1, $src0)
2227 // SETGE_INT reverse args
2229 (selectcc i32:$src0, i32:$src1, -1, 0, SETLE),
2230 (SETGE_INT $src1, $src0)
2233 // SETGT_UINT reverse args
2235 (selectcc i32:$src0, i32:$src1, -1, 0, SETULT),
2236 (SETGT_UINT $src1, $src0)
2239 // SETGE_UINT reverse args
2241 (selectcc i32:$src0, i32:$src1, -1, 0, SETULE),
2242 (SETGE_UINT $src1, $src0)
2245 // The next two patterns are special cases for handling 'true if ordered' and
2246 // 'true if unordered' conditionals. The assumption here is that the behavior of
2247 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
2249 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
2250 // We assume that SETE returns false when one of the operands is NAN and
2251 // SNE returns true when on of the operands is NAN
2253 //SETE - 'true if ordered'
2255 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, SETO),
2259 //SETE_DX10 - 'true if ordered'
2261 (selectcc f32:$src0, f32:$src1, -1, 0, SETO),
2262 (SETE_DX10 $src0, $src1)
2265 //SNE - 'true if unordered'
2267 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, SETUO),
2271 //SETNE_DX10 - 'true if ordered'
2273 (selectcc f32:$src0, f32:$src1, -1, 0, SETUO),
2274 (SETNE_DX10 $src0, $src1)
2277 def : Extract_Element <f32, v4f32, 0, sub0>;
2278 def : Extract_Element <f32, v4f32, 1, sub1>;
2279 def : Extract_Element <f32, v4f32, 2, sub2>;
2280 def : Extract_Element <f32, v4f32, 3, sub3>;
2282 def : Insert_Element <f32, v4f32, 0, sub0>;
2283 def : Insert_Element <f32, v4f32, 1, sub1>;
2284 def : Insert_Element <f32, v4f32, 2, sub2>;
2285 def : Insert_Element <f32, v4f32, 3, sub3>;
2287 def : Extract_Element <i32, v4i32, 0, sub0>;
2288 def : Extract_Element <i32, v4i32, 1, sub1>;
2289 def : Extract_Element <i32, v4i32, 2, sub2>;
2290 def : Extract_Element <i32, v4i32, 3, sub3>;
2292 def : Insert_Element <i32, v4i32, 0, sub0>;
2293 def : Insert_Element <i32, v4i32, 1, sub1>;
2294 def : Insert_Element <i32, v4i32, 2, sub2>;
2295 def : Insert_Element <i32, v4i32, 3, sub3>;
2297 def : Vector4_Build <v4f32, f32>;
2298 def : Vector4_Build <v4i32, i32>;
2300 // bitconvert patterns
2302 def : BitConvert <i32, f32, R600_Reg32>;
2303 def : BitConvert <f32, i32, R600_Reg32>;
2304 def : BitConvert <v4f32, v4i32, R600_Reg128>;
2305 def : BitConvert <v4i32, v4f32, R600_Reg128>;
2307 // DWORDADDR pattern
2308 def : DwordAddrPat <i32, R600_Reg32>;
2310 } // End isR600toCayman Predicate