1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // R600 Tablegen instruction definitions
12 //===----------------------------------------------------------------------===//
14 include "R600Intrinsics.td"
16 class InstR600 <dag outs, dag ins, string asm, list<dag> pattern,
18 : AMDGPUInst <outs, ins, asm, pattern> {
24 bits<2> FlagOperandIdx = 0;
27 bit HasNativeOperands = 0;
31 let Namespace = "AMDGPU";
32 let OutOperandList = outs;
33 let InOperandList = ins;
35 let Pattern = pattern;
38 let TSFlags{4} = Trig;
41 // Vector instructions are instructions that must fill all slots in an
43 let TSFlags{6} = isVector;
44 let TSFlags{8-7} = FlagOperandIdx;
45 let TSFlags{9} = HasNativeOperands;
46 let TSFlags{10} = Op1;
47 let TSFlags{11} = Op2;
48 let TSFlags{12} = VTXInst;
49 let TSFlags{13} = TEXInst;
52 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
53 InstR600 <outs, ins, asm, pattern, NullALU> {
55 let Namespace = "AMDGPU";
58 def MEMxi : Operand<iPTR> {
59 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
60 let PrintMethod = "printMemOperand";
63 def MEMrr : Operand<iPTR> {
64 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
67 // Operands for non-registers
69 class InstFlag<string PM = "printOperand", int Default = 0>
70 : OperandWithDefaultOps <i32, (ops (i32 Default))> {
74 // src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
75 def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
76 let PrintMethod = "printSel";
78 def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> {
79 let PrintMethod = "printSel";
82 def LITERAL : InstFlag<"printLiteral">;
84 def WRITE : InstFlag <"printWrite", 1>;
85 def OMOD : InstFlag <"printOMOD">;
86 def REL : InstFlag <"printRel">;
87 def CLAMP : InstFlag <"printClamp">;
88 def NEG : InstFlag <"printNeg">;
89 def ABS : InstFlag <"printAbs">;
90 def UEM : InstFlag <"printUpdateExecMask">;
91 def UP : InstFlag <"printUpdatePred">;
93 // XXX: The r600g finalizer in Mesa expects last to be one in most cases.
94 // Once we start using the packetizer in this backend we should have this
96 def LAST : InstFlag<"printLast", 1>;
98 def FRAMEri : Operand<iPTR> {
99 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index);
102 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
103 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
104 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
105 def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;
106 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
107 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
109 class R600ALU_Word0 {
110 field bits<32> Word0;
118 bits<3> index_mode = 0;
122 bits<9> src0_sel = src0{8-0};
123 bits<2> src0_chan = src0{10-9};
124 bits<9> src1_sel = src1{8-0};
125 bits<2> src1_chan = src1{10-9};
127 let Word0{8-0} = src0_sel;
128 let Word0{9} = src0_rel;
129 let Word0{11-10} = src0_chan;
130 let Word0{12} = src0_neg;
131 let Word0{21-13} = src1_sel;
132 let Word0{22} = src1_rel;
133 let Word0{24-23} = src1_chan;
134 let Word0{25} = src1_neg;
135 let Word0{28-26} = index_mode;
136 let Word0{30-29} = pred_sel;
137 let Word0{31} = last;
140 class R600ALU_Word1 {
141 field bits<32> Word1;
144 bits<3> bank_swizzle;
148 bits<7> dst_sel = dst{6-0};
149 bits<2> dst_chan = dst{10-9};
151 let Word1{20-18} = bank_swizzle;
152 let Word1{27-21} = dst_sel;
153 let Word1{28} = dst_rel;
154 let Word1{30-29} = dst_chan;
155 let Word1{31} = clamp;
158 class R600ALU_Word1_OP2 <bits<11> alu_inst> : R600ALU_Word1{
162 bits<1> update_exec_mask;
167 let Word1{0} = src0_abs;
168 let Word1{1} = src1_abs;
169 let Word1{2} = update_exec_mask;
170 let Word1{3} = update_pred;
171 let Word1{4} = write;
172 let Word1{6-5} = omod;
173 let Word1{17-7} = alu_inst;
176 class R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{
182 bits<9> src2_sel = src2{8-0};
183 bits<2> src2_chan = src2{10-9};
185 let Word1{8-0} = src2_sel;
186 let Word1{9} = src2_rel;
187 let Word1{11-10} = src2_chan;
188 let Word1{12} = src2_neg;
189 let Word1{17-13} = alu_inst;
193 field bits<32> Word0;
197 bits<1> FETCH_WHOLE_QUAD;
201 bits<6> MEGA_FETCH_COUNT;
203 let Word0{4-0} = VC_INST;
204 let Word0{6-5} = FETCH_TYPE;
205 let Word0{7} = FETCH_WHOLE_QUAD;
206 let Word0{15-8} = BUFFER_ID;
207 let Word0{22-16} = SRC_GPR;
208 let Word0{23} = SRC_REL;
209 let Word0{25-24} = SRC_SEL_X;
210 let Word0{31-26} = MEGA_FETCH_COUNT;
213 class VTX_WORD1_GPR {
214 field bits<32> Word1;
221 bits<1> USE_CONST_FIELDS;
223 bits<2> NUM_FORMAT_ALL;
224 bits<1> FORMAT_COMP_ALL;
225 bits<1> SRF_MODE_ALL;
227 let Word1{6-0} = DST_GPR;
228 let Word1{7} = DST_REL;
229 let Word1{8} = 0; // Reserved
230 let Word1{11-9} = DST_SEL_X;
231 let Word1{14-12} = DST_SEL_Y;
232 let Word1{17-15} = DST_SEL_Z;
233 let Word1{20-18} = DST_SEL_W;
234 let Word1{21} = USE_CONST_FIELDS;
235 let Word1{27-22} = DATA_FORMAT;
236 let Word1{29-28} = NUM_FORMAT_ALL;
237 let Word1{30} = FORMAT_COMP_ALL;
238 let Word1{31} = SRF_MODE_ALL;
242 field bits<32> Word0;
246 bits<1> FETCH_WHOLE_QUAD;
251 bits<2> RESOURCE_INDEX_MODE;
252 bits<2> SAMPLER_INDEX_MODE;
254 let Word0{4-0} = TEX_INST;
255 let Word0{6-5} = INST_MOD;
256 let Word0{7} = FETCH_WHOLE_QUAD;
257 let Word0{15-8} = RESOURCE_ID;
258 let Word0{22-16} = SRC_GPR;
259 let Word0{23} = SRC_REL;
260 let Word0{24} = ALT_CONST;
261 let Word0{26-25} = RESOURCE_INDEX_MODE;
262 let Word0{28-27} = SAMPLER_INDEX_MODE;
266 field bits<32> Word1;
275 bits<1> COORD_TYPE_X;
276 bits<1> COORD_TYPE_Y;
277 bits<1> COORD_TYPE_Z;
278 bits<1> COORD_TYPE_W;
280 let Word1{6-0} = DST_GPR;
281 let Word1{7} = DST_REL;
282 let Word1{11-9} = DST_SEL_X;
283 let Word1{14-12} = DST_SEL_Y;
284 let Word1{17-15} = DST_SEL_Z;
285 let Word1{20-18} = DST_SEL_W;
286 let Word1{27-21} = LOD_BIAS;
287 let Word1{28} = COORD_TYPE_X;
288 let Word1{29} = COORD_TYPE_Y;
289 let Word1{30} = COORD_TYPE_Z;
290 let Word1{31} = COORD_TYPE_W;
294 field bits<32> Word2;
305 let Word2{4-0} = OFFSET_X;
306 let Word2{9-5} = OFFSET_Y;
307 let Word2{14-10} = OFFSET_Z;
308 let Word2{19-15} = SAMPLER_ID;
309 let Word2{22-20} = SRC_SEL_X;
310 let Word2{25-23} = SRC_SEL_Y;
311 let Word2{28-26} = SRC_SEL_Z;
312 let Word2{31-29} = SRC_SEL_W;
316 XXX: R600 subtarget uses a slightly different encoding than the other
317 subtargets. We currently handle this in R600MCCodeEmitter, but we may
318 want to use these instruction classes in the future.
320 class R600ALU_Word1_OP2_r600 : R600ALU_Word1_OP2 {
325 let Inst{37} = fog_merge;
326 let Inst{39-38} = omod;
327 let Inst{49-40} = alu_inst;
330 class R600ALU_Word1_OP2_r700 : R600ALU_Word1_OP2 {
334 let Inst{38-37} = omod;
335 let Inst{49-39} = alu_inst;
339 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
343 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
345 // Class for instructions with only one source register.
346 // If you add new ins to this instruction, make sure they are listed before
347 // $literal, because the backend currently assumes that the last operand is
348 // a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in
349 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(),
350 // and R600InstrInfo::getOperandIdx().
351 class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
352 InstrItinClass itin = AnyALU> :
353 InstR600 <(outs R600_Reg32:$dst),
354 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
355 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
356 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
357 BANK_SWIZZLE:$bank_swizzle),
358 !strconcat(" ", opName,
359 "$clamp $dst$write$dst_rel$omod, "
360 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
361 "$literal $pred_sel$last"),
365 R600ALU_Word1_OP2 <inst> {
371 let update_exec_mask = 0;
373 let HasNativeOperands = 1;
375 let DisableEncoding = "$literal";
377 let Inst{31-0} = Word0;
378 let Inst{63-32} = Word1;
381 class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
382 InstrItinClass itin = AnyALU> :
383 R600_1OP <inst, opName,
384 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))]
387 // If you add our change the operands for R600_2OP instructions, you must
388 // also update the R600Op2OperandIndex::ROI enum in R600Defines.h,
389 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
390 class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
391 InstrItinClass itin = AnyALU> :
392 InstR600 <(outs R600_Reg32:$dst),
393 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
394 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
395 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
396 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
397 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
398 BANK_SWIZZLE:$bank_swizzle),
399 !strconcat(" ", opName,
400 "$clamp $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
401 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
402 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
403 "$literal $pred_sel$last"),
407 R600ALU_Word1_OP2 <inst> {
409 let HasNativeOperands = 1;
411 let DisableEncoding = "$literal";
413 let Inst{31-0} = Word0;
414 let Inst{63-32} = Word1;
417 class R600_2OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
418 InstrItinClass itim = AnyALU> :
419 R600_2OP <inst, opName,
420 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
424 // If you add our change the operands for R600_3OP instructions, you must
425 // also update the R600Op3OperandIndex::ROI enum in R600Defines.h,
426 // R600InstrInfo::buildDefaultInstruction(), and
427 // R600InstrInfo::getOperandIdx().
428 class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
429 InstrItinClass itin = AnyALU> :
430 InstR600 <(outs R600_Reg32:$dst),
431 (ins REL:$dst_rel, CLAMP:$clamp,
432 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
433 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
434 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
435 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
436 BANK_SWIZZLE:$bank_swizzle),
437 !strconcat(" ", opName, "$clamp $dst$dst_rel, "
438 "$src0_neg$src0$src0_rel, "
439 "$src1_neg$src1$src1_rel, "
440 "$src2_neg$src2$src2_rel, "
441 "$literal $pred_sel$last"),
445 R600ALU_Word1_OP3<inst>{
447 let HasNativeOperands = 1;
448 let DisableEncoding = "$literal";
451 let Inst{31-0} = Word0;
452 let Inst{63-32} = Word1;
455 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
456 InstrItinClass itin = VecALU> :
457 InstR600 <(outs R600_Reg32:$dst),
463 class R600_TEX <bits<11> inst, string opName, list<dag> pattern,
464 InstrItinClass itin = AnyALU> :
465 InstR600 <(outs R600_Reg128:$DST_GPR),
466 (ins R600_Reg128:$SRC_GPR, i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID, i32imm:$textureTarget),
467 !strconcat(opName, "$DST_GPR, $SRC_GPR, $RESOURCE_ID, $SAMPLER_ID, $textureTarget"),
469 itin>, TEX_WORD0, TEX_WORD1, TEX_WORD2 {
470 let Inst{31-0} = Word0;
471 let Inst{63-32} = Word1;
473 let TEX_INST = inst{4-0};
483 let FETCH_WHOLE_QUAD = 0;
485 let SAMPLER_INDEX_MODE = 0;
486 let RESOURCE_INDEX_MODE = 0;
488 let COORD_TYPE_X = 0;
489 let COORD_TYPE_Y = 0;
490 let COORD_TYPE_Z = 0;
491 let COORD_TYPE_W = 0;
496 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
498 def TEX_SHADOW : PatLeaf<
500 [{uint32_t TType = (uint32_t)N->getZExtValue();
501 return (TType >= 6 && TType <= 8) || (TType >= 11 && TType <= 13);
505 def TEX_RECT : PatLeaf<
507 [{uint32_t TType = (uint32_t)N->getZExtValue();
512 def TEX_ARRAY : PatLeaf<
514 [{uint32_t TType = (uint32_t)N->getZExtValue();
515 return TType == 9 || TType == 10 || TType == 15 || TType == 16;
519 def TEX_SHADOW_ARRAY : PatLeaf<
521 [{uint32_t TType = (uint32_t)N->getZExtValue();
522 return TType == 11 || TType == 12 || TType == 17;
526 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
527 dag ins, string asm, list<dag> pattern> :
528 InstR600ISA <outs, ins, asm, pattern> {
545 // CF_ALLOC_EXPORT_WORD0_RAT
546 let Inst{3-0} = rat_id;
547 let Inst{9-4} = rat_inst;
548 let Inst{10} = 0; // Reserved
549 let Inst{12-11} = RIM;
550 let Inst{14-13} = TYPE;
551 let Inst{21-15} = RW_GPR;
552 let Inst{22} = RW_REL;
553 let Inst{29-23} = INDEX_GPR;
554 let Inst{31-30} = ELEM_SIZE;
556 // CF_ALLOC_EXPORT_WORD1_BUF
557 let Inst{43-32} = ARRAY_SIZE;
558 let Inst{47-44} = COMP_MASK;
559 let Inst{51-48} = BURST_COUNT;
562 let Inst{61-54} = cf_inst;
564 let Inst{63} = BARRIER;
567 class LoadParamFrag <PatFrag load_type> : PatFrag <
568 (ops node:$ptr), (load_type node:$ptr),
569 [{ return isParamLoad(dyn_cast<LoadSDNode>(N)); }]
572 def load_param : LoadParamFrag<load>;
573 def load_param_zexti8 : LoadParamFrag<zextloadi8>;
574 def load_param_zexti16 : LoadParamFrag<zextloadi16>;
576 def isR600 : Predicate<"Subtarget.device()"
577 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX">;
578 def isR700 : Predicate<"Subtarget.device()"
579 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX &&"
580 "Subtarget.device()->getDeviceFlag()"
581 ">= OCL_DEVICE_RV710">;
582 def isEG : Predicate<
583 "Subtarget.device()->getGeneration() >= AMDGPUDeviceInfo::HD5XXX && "
584 "Subtarget.device()->getGeneration() < AMDGPUDeviceInfo::HD7XXX && "
585 "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
587 def isCayman : Predicate<"Subtarget.device()"
588 "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
589 def isEGorCayman : Predicate<"Subtarget.device()"
590 "->getGeneration() == AMDGPUDeviceInfo::HD5XXX"
591 "|| Subtarget.device()->getGeneration() =="
592 "AMDGPUDeviceInfo::HD6XXX">;
594 def isR600toCayman : Predicate<
595 "Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX">;
597 //===----------------------------------------------------------------------===//
599 //===----------------------------------------------------------------------===//
601 def INTERP_PAIR_XY : AMDGPUShaderInst <
602 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),
603 (ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
604 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
607 def INTERP_PAIR_ZW : AMDGPUShaderInst <
608 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),
609 (ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
610 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
613 def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS",
614 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>,
618 //===----------------------------------------------------------------------===//
619 // Interpolation Instructions
620 //===----------------------------------------------------------------------===//
622 def INTERP_VEC_LOAD : AMDGPUShaderInst <
623 (outs R600_Reg128:$dst),
625 "INTERP_LOAD $src0 : $dst",
628 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {
629 let bank_swizzle = 5;
632 def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> {
633 let bank_swizzle = 5;
636 def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
638 //===----------------------------------------------------------------------===//
639 // Export Instructions
640 //===----------------------------------------------------------------------===//
642 def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
644 def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
645 [SDNPHasChain, SDNPSideEffect]>;
648 field bits<32> Word0;
655 let Word0{12-0} = arraybase;
656 let Word0{14-13} = type;
657 let Word0{21-15} = gpr;
658 let Word0{22} = 0; // RW_REL
659 let Word0{29-23} = 0; // INDEX_GPR
660 let Word0{31-30} = elem_size;
663 class ExportSwzWord1 {
664 field bits<32> Word1;
673 let Word1{2-0} = sw_x;
674 let Word1{5-3} = sw_y;
675 let Word1{8-6} = sw_z;
676 let Word1{11-9} = sw_w;
679 class ExportBufWord1 {
680 field bits<32> Word1;
687 let Word1{11-0} = arraySize;
688 let Word1{15-12} = compMask;
691 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
692 def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg),
694 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
695 0, 61, 0, 7, 7, 7, cf_inst, 0)
698 def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg),
700 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
701 0, 61, 7, 0, 7, 7, cf_inst, 0)
704 def : Pat<(int_R600_store_dummy (i32 imm:$type)),
706 (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
709 def : Pat<(int_R600_store_dummy 1),
711 (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
714 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
715 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
716 (ExportInst R600_Reg128:$src, imm:$type, imm:$base,
717 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)
722 multiclass SteamOutputExportPattern<Instruction ExportInst,
723 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
725 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
726 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),
727 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
728 4095, imm:$mask, buf0inst, 0)>;
730 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
731 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),
732 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
733 4095, imm:$mask, buf1inst, 0)>;
735 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
736 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),
737 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
738 4095, imm:$mask, buf2inst, 0)>;
740 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
741 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),
742 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
743 4095, imm:$mask, buf3inst, 0)>;
746 // Export Instructions should not be duplicated by TailDuplication pass
747 // (which assumes that duplicable instruction are affected by exec mask)
748 let usesCustomInserter = 1, isNotDuplicable = 1 in {
750 class ExportSwzInst : InstR600ISA<(
752 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
753 i32imm:$sw_x, i32imm:$sw_y, i32imm:$sw_z, i32imm:$sw_w, i32imm:$inst,
755 !strconcat("EXPORT", " $gpr"),
756 []>, ExportWord0, ExportSwzWord1 {
758 let Inst{31-0} = Word0;
759 let Inst{63-32} = Word1;
762 } // End usesCustomInserter = 1
764 class ExportBufInst : InstR600ISA<(
766 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
767 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop),
768 !strconcat("EXPORT", " $gpr"),
769 []>, ExportWord0, ExportBufWord1 {
771 let Inst{31-0} = Word0;
772 let Inst{63-32} = Word1;
775 //===----------------------------------------------------------------------===//
776 // Control Flow Instructions
777 //===----------------------------------------------------------------------===//
780 field bits<32> Word0;
783 bits<4> KCACHE_BANK0;
784 bits<4> KCACHE_BANK1;
785 bits<2> KCACHE_MODE0;
787 let Word0{21-0} = ADDR;
788 let Word0{25-22} = KCACHE_BANK0;
789 let Word0{29-26} = KCACHE_BANK1;
790 let Word0{31-30} = KCACHE_MODE0;
794 field bits<32> Word1;
796 bits<2> KCACHE_MODE1;
797 bits<8> KCACHE_ADDR0;
798 bits<8> KCACHE_ADDR1;
802 bits<1> WHOLE_QUAD_MODE;
805 let Word1{1-0} = KCACHE_MODE1;
806 let Word1{9-2} = KCACHE_ADDR0;
807 let Word1{17-10} = KCACHE_ADDR1;
808 let Word1{24-18} = COUNT;
809 let Word1{25} = ALT_CONST;
810 let Word1{29-26} = CF_INST;
811 let Word1{30} = WHOLE_QUAD_MODE;
812 let Word1{31} = BARRIER;
815 class ALU_CLAUSE<bits<4> inst, string OpName> : AMDGPUInst <(outs),
816 (ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1, i32imm:$KCACHE_MODE0, i32imm:$KCACHE_MODE1,
817 i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1, i32imm:$COUNT),
818 !strconcat(OpName, " $COUNT, @$ADDR, "
819 "KC0[CB$KCACHE_BANK0:$KCACHE_ADDR0-$KCACHE_ADDR0+32]"
820 ", KC1[CB$KCACHE_BANK1:$KCACHE_ADDR1-$KCACHE_ADDR1+32]"),
821 [] >, CF_ALU_WORD0, CF_ALU_WORD1 {
826 let WHOLE_QUAD_MODE = 0;
829 let Inst{31-0} = Word0;
830 let Inst{63-32} = Word1;
833 class CF_WORD0_R600 {
834 field bits<32> Word0;
841 class CF_WORD1_R600 {
842 field bits<32> Word1;
850 bits<1> END_OF_PROGRAM;
851 bits<1> VALID_PIXEL_MODE;
853 bits<1> WHOLE_QUAD_MODE;
856 let Word1{2-0} = POP_COUNT;
857 let Word1{7-3} = CF_CONST;
858 let Word1{9-8} = COND;
859 let Word1{12-10} = COUNT;
860 let Word1{18-13} = CALL_COUNT;
861 let Word1{19} = COUNT_3;
862 let Word1{21} = END_OF_PROGRAM;
863 let Word1{22} = VALID_PIXEL_MODE;
864 let Word1{29-23} = CF_INST;
865 let Word1{30} = WHOLE_QUAD_MODE;
866 let Word1{31} = BARRIER;
869 class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
870 ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 {
876 let VALID_PIXEL_MODE = 0;
880 let END_OF_PROGRAM = 0;
881 let WHOLE_QUAD_MODE = 0;
883 let Inst{31-0} = Word0;
884 let Inst{63-32} = Word1;
888 field bits<32> Word0;
891 bits<3> JUMPTABLE_SEL;
893 let Word0{23-0} = ADDR;
894 let Word0{26-24} = JUMPTABLE_SEL;
898 field bits<32> Word1;
904 bits<1> VALID_PIXEL_MODE;
905 bits<1> END_OF_PROGRAM;
909 let Word1{2-0} = POP_COUNT;
910 let Word1{7-3} = CF_CONST;
911 let Word1{9-8} = COND;
912 let Word1{15-10} = COUNT;
913 let Word1{20} = VALID_PIXEL_MODE;
914 let Word1{21} = END_OF_PROGRAM;
915 let Word1{29-22} = CF_INST;
916 let Word1{31} = BARRIER;
919 class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
920 ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG {
925 let JUMPTABLE_SEL = 0;
927 let VALID_PIXEL_MODE = 0;
929 let END_OF_PROGRAM = 0;
931 let Inst{31-0} = Word0;
932 let Inst{63-32} = Word1;
935 def CF_ALU : ALU_CLAUSE<8, "ALU">;
936 def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">;
938 def FETCH_CLAUSE : AMDGPUInst <(outs),
939 (ins i32imm:$addr), "Fetch clause starting at $addr:", [] > {
945 def PAD : AMDGPUInst <(outs), (ins), "PAD", [] > {
949 let Predicates = [isR600toCayman] in {
951 //===----------------------------------------------------------------------===//
952 // Common Instructions R600, R700, Evergreen, Cayman
953 //===----------------------------------------------------------------------===//
955 def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;
956 // Non-IEEE MUL: 0 * anything = 0
957 def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>;
958 def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
959 def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax>;
960 def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin>;
962 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
963 // so some of the instruction names don't match the asm string.
964 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
965 def SETE : R600_2OP <
967 [(set R600_Reg32:$dst,
968 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
974 [(set R600_Reg32:$dst,
975 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
981 [(set R600_Reg32:$dst,
982 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
988 [(set R600_Reg32:$dst,
989 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
993 def SETE_DX10 : R600_2OP <
995 [(set R600_Reg32:$dst,
996 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
1000 def SETGT_DX10 : R600_2OP <
1002 [(set R600_Reg32:$dst,
1003 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
1007 def SETGE_DX10 : R600_2OP <
1009 [(set R600_Reg32:$dst,
1010 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
1014 def SETNE_DX10 : R600_2OP <
1016 [(set R600_Reg32:$dst,
1017 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
1021 def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;
1022 def TRUNC : R600_1OP_Helper <0x11, "TRUNC", int_AMDGPU_trunc>;
1023 def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
1024 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
1025 def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
1027 def MOV : R600_1OP <0x19, "MOV", []>;
1029 let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
1031 class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst <
1032 (outs R600_Reg32:$dst),
1038 } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1
1040 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
1043 (MOV_IMM_I32 imm:$val)
1046 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
1049 (MOV_IMM_F32 fpimm:$val)
1052 def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>;
1053 def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>;
1054 def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>;
1055 def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>;
1057 let hasSideEffects = 1 in {
1059 def KILLGT : R600_2OP <0x2D, "KILLGT", []>;
1061 } // end hasSideEffects
1063 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
1064 def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;
1065 def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;
1066 def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;
1067 def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;
1068 def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;
1069 def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>;
1070 def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>;
1071 def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUumax>;
1072 def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>;
1074 def SETE_INT : R600_2OP <
1076 [(set (i32 R600_Reg32:$dst),
1077 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
1080 def SETGT_INT : R600_2OP <
1082 [(set (i32 R600_Reg32:$dst),
1083 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
1086 def SETGE_INT : R600_2OP <
1088 [(set (i32 R600_Reg32:$dst),
1089 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
1092 def SETNE_INT : R600_2OP <
1094 [(set (i32 R600_Reg32:$dst),
1095 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
1098 def SETGT_UINT : R600_2OP <
1100 [(set (i32 R600_Reg32:$dst),
1101 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
1104 def SETGE_UINT : R600_2OP <
1106 [(set (i32 R600_Reg32:$dst),
1107 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
1110 def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>;
1111 def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>;
1112 def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>;
1113 def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>;
1115 def CNDE_INT : R600_3OP <
1117 [(set (i32 R600_Reg32:$dst),
1118 (selectcc (i32 R600_Reg32:$src0), 0,
1119 (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
1123 def CNDGE_INT : R600_3OP <
1125 [(set (i32 R600_Reg32:$dst),
1126 (selectcc (i32 R600_Reg32:$src0), 0,
1127 (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
1131 def CNDGT_INT : R600_3OP <
1133 [(set (i32 R600_Reg32:$dst),
1134 (selectcc (i32 R600_Reg32:$src0), 0,
1135 (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
1139 //===----------------------------------------------------------------------===//
1140 // Texture instructions
1141 //===----------------------------------------------------------------------===//
1143 def TEX_LD : R600_TEX <
1145 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txf R600_Reg128:$SRC_GPR,
1146 imm:$OFFSET_X, imm:$OFFSET_Y, imm:$OFFSET_Z, imm:$RESOURCE_ID,
1147 imm:$SAMPLER_ID, imm:$textureTarget))]
1149 let AsmString = "TEX_LD $DST_GPR, $SRC_GPR, $OFFSET_X, $OFFSET_Y, $OFFSET_Z,"
1150 "$RESOURCE_ID, $SAMPLER_ID, $textureTarget";
1151 let InOperandList = (ins R600_Reg128:$SRC_GPR, i32imm:$OFFSET_X,
1152 i32imm:$OFFSET_Y, i32imm:$OFFSET_Z, i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID,
1153 i32imm:$textureTarget);
1156 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
1157 0x04, "TEX_GET_TEXTURE_RESINFO",
1158 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txq R600_Reg128:$SRC_GPR,
1159 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1162 def TEX_GET_GRADIENTS_H : R600_TEX <
1163 0x07, "TEX_GET_GRADIENTS_H",
1164 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_ddx R600_Reg128:$SRC_GPR,
1165 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1168 def TEX_GET_GRADIENTS_V : R600_TEX <
1169 0x08, "TEX_GET_GRADIENTS_V",
1170 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_ddy R600_Reg128:$SRC_GPR,
1171 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1174 def TEX_SET_GRADIENTS_H : R600_TEX <
1175 0x0B, "TEX_SET_GRADIENTS_H",
1179 def TEX_SET_GRADIENTS_V : R600_TEX <
1180 0x0C, "TEX_SET_GRADIENTS_V",
1184 def TEX_SAMPLE : R600_TEX <
1186 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_tex R600_Reg128:$SRC_GPR,
1187 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1190 def TEX_SAMPLE_C : R600_TEX <
1191 0x18, "TEX_SAMPLE_C",
1192 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_tex R600_Reg128:$SRC_GPR,
1193 imm:$RESOURCE_ID, imm:$SAMPLER_ID, TEX_SHADOW:$textureTarget))]
1196 def TEX_SAMPLE_L : R600_TEX <
1197 0x11, "TEX_SAMPLE_L",
1198 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txl R600_Reg128:$SRC_GPR,
1199 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1202 def TEX_SAMPLE_C_L : R600_TEX <
1203 0x19, "TEX_SAMPLE_C_L",
1204 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txl R600_Reg128:$SRC_GPR,
1205 imm:$RESOURCE_ID, imm:$SAMPLER_ID, TEX_SHADOW:$textureTarget))]
1208 def TEX_SAMPLE_LB : R600_TEX <
1209 0x12, "TEX_SAMPLE_LB",
1210 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txb R600_Reg128:$SRC_GPR,
1211 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1214 def TEX_SAMPLE_C_LB : R600_TEX <
1215 0x1A, "TEX_SAMPLE_C_LB",
1216 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txb R600_Reg128:$SRC_GPR,
1217 imm:$RESOURCE_ID, imm:$SAMPLER_ID, TEX_SHADOW:$textureTarget))]
1220 def TEX_SAMPLE_G : R600_TEX <
1221 0x14, "TEX_SAMPLE_G",
1225 def TEX_SAMPLE_C_G : R600_TEX <
1226 0x1C, "TEX_SAMPLE_C_G",
1230 //===----------------------------------------------------------------------===//
1231 // Helper classes for common instructions
1232 //===----------------------------------------------------------------------===//
1234 class MUL_LIT_Common <bits<5> inst> : R600_3OP <
1239 class MULADD_Common <bits<5> inst> : R600_3OP <
1244 class MULADD_IEEE_Common <bits<5> inst> : R600_3OP <
1245 inst, "MULADD_IEEE",
1246 [(set (f32 R600_Reg32:$dst),
1247 (fadd (fmul R600_Reg32:$src0, R600_Reg32:$src1), R600_Reg32:$src2))]
1250 class CNDE_Common <bits<5> inst> : R600_3OP <
1252 [(set R600_Reg32:$dst,
1253 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
1254 (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
1258 class CNDGT_Common <bits<5> inst> : R600_3OP <
1260 [(set R600_Reg32:$dst,
1261 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
1262 (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
1266 class CNDGE_Common <bits<5> inst> : R600_3OP <
1268 [(set R600_Reg32:$dst,
1269 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
1270 (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
1274 multiclass DOT4_Common <bits<11> inst> {
1276 def _pseudo : R600_REDUCTION <inst,
1277 (ins R600_Reg128:$src0, R600_Reg128:$src1),
1278 "DOT4 $dst $src0, $src1",
1279 [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
1282 def _real : R600_2OP <inst, "DOT4", []>;
1285 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
1286 multiclass CUBE_Common <bits<11> inst> {
1288 def _pseudo : InstR600 <
1289 (outs R600_Reg128:$dst),
1290 (ins R600_Reg128:$src),
1292 [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
1298 def _real : R600_2OP <inst, "CUBE", []>;
1300 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
1302 class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1303 inst, "EXP_IEEE", fexp2
1306 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper <
1307 inst, "FLT_TO_INT", fp_to_sint
1310 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1311 inst, "INT_TO_FLT", sint_to_fp
1314 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1315 inst, "FLT_TO_UINT", fp_to_uint
1318 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1319 inst, "UINT_TO_FLT", uint_to_fp
1322 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
1323 inst, "LOG_CLAMPED", []
1326 class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1327 inst, "LOG_IEEE", flog2
1330 class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;
1331 class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;
1332 class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;
1333 class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <
1334 inst, "MULHI_INT", mulhs
1336 class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <
1337 inst, "MULHI", mulhu
1339 class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <
1340 inst, "MULLO_INT", mul
1342 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []>;
1344 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
1345 inst, "RECIP_CLAMPED", []
1348 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
1349 inst, "RECIP_IEEE", [(set R600_Reg32:$dst, (fdiv FP_ONE, R600_Reg32:$src0))]
1352 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1353 inst, "RECIP_UINT", AMDGPUurecip
1356 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <
1357 inst, "RECIPSQRT_CLAMPED", int_AMDGPU_rsq
1360 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP <
1361 inst, "RECIPSQRT_IEEE", []
1364 class SIN_Common <bits<11> inst> : R600_1OP <
1369 class COS_Common <bits<11> inst> : R600_1OP <
1374 //===----------------------------------------------------------------------===//
1375 // Helper patterns for complex intrinsics
1376 //===----------------------------------------------------------------------===//
1378 multiclass DIV_Common <InstR600 recip_ieee> {
1380 (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
1381 (MUL_IEEE R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
1385 (fdiv R600_Reg32:$src0, R600_Reg32:$src1),
1386 (MUL_IEEE R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
1390 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
1391 (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
1392 (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
1395 //===----------------------------------------------------------------------===//
1396 // R600 / R700 Instructions
1397 //===----------------------------------------------------------------------===//
1399 let Predicates = [isR600] in {
1401 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
1402 def MULADD_r600 : MULADD_Common<0x10>;
1403 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>;
1404 def CNDE_r600 : CNDE_Common<0x18>;
1405 def CNDGT_r600 : CNDGT_Common<0x19>;
1406 def CNDGE_r600 : CNDGE_Common<0x1A>;
1407 defm DOT4_r600 : DOT4_Common<0x50>;
1408 defm CUBE_r600 : CUBE_Common<0x52>;
1409 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
1410 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
1411 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
1412 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
1413 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
1414 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
1415 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
1416 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
1417 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
1418 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
1419 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
1420 def SIN_r600 : SIN_Common<0x6E>;
1421 def COS_r600 : COS_Common<0x6F>;
1422 def ASHR_r600 : ASHR_Common<0x70>;
1423 def LSHR_r600 : LSHR_Common<0x71>;
1424 def LSHL_r600 : LSHL_Common<0x72>;
1425 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
1426 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
1427 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
1428 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
1429 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
1431 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
1432 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL, R600_Reg32>;
1433 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
1435 def : Pat<(fsqrt R600_Reg32:$src),
1436 (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_r600 R600_Reg32:$src))>;
1438 def R600_ExportSwz : ExportSwzInst {
1439 let Word1{20-17} = 0; // BURST_COUNT
1440 let Word1{21} = eop;
1441 let Word1{22} = 1; // VALID_PIXEL_MODE
1442 let Word1{30-23} = inst;
1443 let Word1{31} = 1; // BARRIER
1445 defm : ExportPattern<R600_ExportSwz, 39>;
1447 def R600_ExportBuf : ExportBufInst {
1448 let Word1{20-17} = 0; // BURST_COUNT
1449 let Word1{21} = eop;
1450 let Word1{22} = 1; // VALID_PIXEL_MODE
1451 let Word1{30-23} = inst;
1452 let Word1{31} = 1; // BARRIER
1454 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>;
1456 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$COUNT),
1457 "TEX $COUNT @$ADDR"> {
1460 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$COUNT),
1461 "VTX $COUNT @$ADDR"> {
1464 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR),
1465 "LOOP_START_DX10 @$ADDR"> {
1469 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1473 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR),
1474 "LOOP_BREAK @$ADDR"> {
1478 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR),
1479 "CONTINUE @$ADDR"> {
1483 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1484 "JUMP @$ADDR POP:$POP_COUNT"> {
1487 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1488 "ELSE @$ADDR POP:$POP_COUNT"> {
1491 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> {
1496 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1497 "POP @$ADDR POP:$POP_COUNT"> {
1500 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> {
1504 let END_OF_PROGRAM = 1;
1509 // Helper pattern for normalizing inputs to triginomic instructions for R700+
1511 class COS_PAT <InstR600 trig> : Pat<
1512 (fcos R600_Reg32:$src),
1513 (trig (MUL_IEEE (MOV_IMM_I32 CONST.TWO_PI_INV), R600_Reg32:$src))
1516 class SIN_PAT <InstR600 trig> : Pat<
1517 (fsin R600_Reg32:$src),
1518 (trig (MUL_IEEE (MOV_IMM_I32 CONST.TWO_PI_INV), R600_Reg32:$src))
1521 //===----------------------------------------------------------------------===//
1522 // R700 Only instructions
1523 //===----------------------------------------------------------------------===//
1525 let Predicates = [isR700] in {
1526 def SIN_r700 : SIN_Common<0x6E>;
1527 def COS_r700 : COS_Common<0x6F>;
1529 // R700 normalizes inputs to SIN/COS the same as EG
1530 def : SIN_PAT <SIN_r700>;
1531 def : COS_PAT <COS_r700>;
1534 //===----------------------------------------------------------------------===//
1535 // Evergreen Only instructions
1536 //===----------------------------------------------------------------------===//
1538 let Predicates = [isEG] in {
1540 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
1541 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
1543 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
1544 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
1545 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
1546 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
1547 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
1548 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
1549 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
1550 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
1551 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
1552 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
1553 def SIN_eg : SIN_Common<0x8D>;
1554 def COS_eg : COS_Common<0x8E>;
1556 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL, R600_Reg32>;
1557 def : SIN_PAT <SIN_eg>;
1558 def : COS_PAT <COS_eg>;
1559 def : Pat<(fsqrt R600_Reg32:$src),
1560 (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_eg R600_Reg32:$src))>;
1561 } // End Predicates = [isEG]
1563 //===----------------------------------------------------------------------===//
1564 // Evergreen / Cayman Instructions
1565 //===----------------------------------------------------------------------===//
1567 let Predicates = [isEGorCayman] in {
1569 // BFE_UINT - bit_extract, an optimization for mask and shift
1574 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
1579 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
1580 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
1581 // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
1582 // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
1583 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
1584 [(set R600_Reg32:$dst, (int_AMDIL_bit_extract_u32 R600_Reg32:$src0,
1586 R600_Reg32:$src2))],
1590 def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", []>;
1591 defm : BFIPatterns <BFI_INT_eg>;
1593 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT",
1594 [(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1,
1595 R600_Reg32:$src2))],
1599 def MULADD_eg : MULADD_Common<0x14>;
1600 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
1601 def ASHR_eg : ASHR_Common<0x15>;
1602 def LSHR_eg : LSHR_Common<0x16>;
1603 def LSHL_eg : LSHL_Common<0x17>;
1604 def CNDE_eg : CNDE_Common<0x19>;
1605 def CNDGT_eg : CNDGT_Common<0x1A>;
1606 def CNDGE_eg : CNDGE_Common<0x1B>;
1607 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
1608 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
1609 defm DOT4_eg : DOT4_Common<0xBE>;
1610 defm CUBE_eg : CUBE_Common<0xC0>;
1612 let hasSideEffects = 1 in {
1613 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", []>;
1616 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
1618 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
1622 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
1624 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
1628 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
1630 // TRUNC is used for the FLT_TO_INT instructions to work around a
1631 // perceived problem where the rounding modes are applied differently
1632 // depending on the instruction and the slot they are in.
1634 // https://bugs.freedesktop.org/show_bug.cgi?id=50232
1635 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
1637 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
1638 // which do not need to be truncated since the fp values are 0.0f or 1.0f.
1639 // We should look into handling these cases separately.
1640 def : Pat<(fp_to_sint R600_Reg32:$src0),
1641 (FLT_TO_INT_eg (TRUNC R600_Reg32:$src0))>;
1643 def : Pat<(fp_to_uint R600_Reg32:$src0),
1644 (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src0))>;
1646 def EG_ExportSwz : ExportSwzInst {
1647 let Word1{19-16} = 0; // BURST_COUNT
1648 let Word1{20} = 1; // VALID_PIXEL_MODE
1649 let Word1{21} = eop;
1650 let Word1{29-22} = inst;
1651 let Word1{30} = 0; // MARK
1652 let Word1{31} = 1; // BARRIER
1654 defm : ExportPattern<EG_ExportSwz, 83>;
1656 def EG_ExportBuf : ExportBufInst {
1657 let Word1{19-16} = 0; // BURST_COUNT
1658 let Word1{20} = 1; // VALID_PIXEL_MODE
1659 let Word1{21} = eop;
1660 let Word1{29-22} = inst;
1661 let Word1{30} = 0; // MARK
1662 let Word1{31} = 1; // BARRIER
1664 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
1666 def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),
1667 "TEX $COUNT @$ADDR"> {
1670 def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),
1671 "VTX $COUNT @$ADDR"> {
1674 def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),
1675 "LOOP_START_DX10 @$ADDR"> {
1679 def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1683 def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),
1684 "LOOP_BREAK @$ADDR"> {
1688 def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),
1689 "CONTINUE @$ADDR"> {
1693 def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1694 "JUMP @$ADDR POP:$POP_COUNT"> {
1697 def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1698 "ELSE @$ADDR POP:$POP_COUNT"> {
1701 def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> {
1706 def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1707 "POP @$ADDR POP:$POP_COUNT"> {
1710 def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> {
1714 let END_OF_PROGRAM = 1;
1717 //===----------------------------------------------------------------------===//
1718 // Memory read/write instructions
1719 //===----------------------------------------------------------------------===//
1720 let usesCustomInserter = 1 in {
1722 class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> comp_mask, string name,
1724 : EG_CF_RAT <0x57, 0x2, 0, (outs), ins,
1725 !strconcat(name, " $rw_gpr, $index_gpr, $eop"), pattern> {
1727 // XXX: Have a separate instruction for non-indexed writes.
1733 let COMP_MASK = comp_mask;
1734 let BURST_COUNT = 0;
1740 } // End usesCustomInserter = 1
1743 def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
1744 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1745 0x1, "RAT_WRITE_CACHELESS_32_eg",
1746 [(global_store (i32 R600_TReg32_X:$rw_gpr), R600_TReg32_X:$index_gpr)]
1750 def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
1751 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1752 0xf, "RAT_WRITE_CACHELESS_128",
1753 [(global_store (v4i32 R600_Reg128:$rw_gpr), R600_TReg32_X:$index_gpr)]
1756 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
1757 : InstR600ISA <outs, (ins MEMxi:$ptr), name#" $dst, $ptr", pattern>,
1758 VTX_WORD1_GPR, VTX_WORD0 {
1763 let FETCH_WHOLE_QUAD = 0;
1764 let BUFFER_ID = buffer_id;
1766 // XXX: We can infer this field based on the SRC_GPR. This would allow us
1767 // to store vertex addresses in any channel, not just X.
1770 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
1771 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
1772 // however, based on my testing if USE_CONST_FIELDS is set, then all
1773 // these fields need to be set to 0.
1774 let USE_CONST_FIELDS = 0;
1775 let NUM_FORMAT_ALL = 1;
1776 let FORMAT_COMP_ALL = 0;
1777 let SRF_MODE_ALL = 0;
1779 let Inst{31-0} = Word0;
1780 let Inst{63-32} = Word1;
1781 // LLVM can only encode 64-bit instructions, so these fields are manually
1782 // encoded in R600CodeEmitter
1785 // bits<2> ENDIAN_SWAP = 0;
1786 // bits<1> CONST_BUF_NO_STRIDE = 0;
1787 // bits<1> MEGA_FETCH = 0;
1788 // bits<1> ALT_CONST = 0;
1789 // bits<2> BUFFER_INDEX_MODE = 0;
1793 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1794 // is done in R600CodeEmitter
1796 // Inst{79-64} = OFFSET;
1797 // Inst{81-80} = ENDIAN_SWAP;
1798 // Inst{82} = CONST_BUF_NO_STRIDE;
1799 // Inst{83} = MEGA_FETCH;
1800 // Inst{84} = ALT_CONST;
1801 // Inst{86-85} = BUFFER_INDEX_MODE;
1802 // Inst{95-86} = 0; Reserved
1804 // VTX_WORD3 (Padding)
1806 // Inst{127-96} = 0;
1811 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
1812 : VTX_READ_eg <"VTX_READ_8", buffer_id, (outs R600_TReg32_X:$dst),
1815 let MEGA_FETCH_COUNT = 1;
1817 let DST_SEL_Y = 7; // Masked
1818 let DST_SEL_Z = 7; // Masked
1819 let DST_SEL_W = 7; // Masked
1820 let DATA_FORMAT = 1; // FMT_8
1823 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
1824 : VTX_READ_eg <"VTX_READ_16", buffer_id, (outs R600_TReg32_X:$dst),
1826 let MEGA_FETCH_COUNT = 2;
1828 let DST_SEL_Y = 7; // Masked
1829 let DST_SEL_Z = 7; // Masked
1830 let DST_SEL_W = 7; // Masked
1831 let DATA_FORMAT = 5; // FMT_16
1835 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
1836 : VTX_READ_eg <"VTX_READ_32", buffer_id, (outs R600_TReg32_X:$dst),
1839 let MEGA_FETCH_COUNT = 4;
1841 let DST_SEL_Y = 7; // Masked
1842 let DST_SEL_Z = 7; // Masked
1843 let DST_SEL_W = 7; // Masked
1844 let DATA_FORMAT = 0xD; // COLOR_32
1846 // This is not really necessary, but there were some GPU hangs that appeared
1847 // to be caused by ALU instructions in the next instruction group that wrote
1848 // to the $ptr registers of the VTX_READ.
1850 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
1851 // %T2_X<def> = MOV %ZERO
1852 //Adding this constraint prevents this from happening.
1853 let Constraints = "$ptr.ptr = $dst";
1856 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
1857 : VTX_READ_eg <"VTX_READ_128", buffer_id, (outs R600_Reg128:$dst),
1860 let MEGA_FETCH_COUNT = 16;
1865 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1867 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1868 // that holds its buffer address to avoid potential hangs. We can't use
1869 // the same constraint as VTX_READ_32_eg, because the $ptr.ptr and $dst
1870 // registers are different sizes.
1873 //===----------------------------------------------------------------------===//
1874 // VTX Read from parameter memory space
1875 //===----------------------------------------------------------------------===//
1877 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0,
1878 [(set (i32 R600_TReg32_X:$dst), (load_param_zexti8 ADDRVTX_READ:$ptr))]
1881 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0,
1882 [(set (i32 R600_TReg32_X:$dst), (load_param_zexti16 ADDRVTX_READ:$ptr))]
1885 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0,
1886 [(set (i32 R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))]
1889 def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0,
1890 [(set (v4i32 R600_Reg128:$dst), (load_param ADDRVTX_READ:$ptr))]
1893 //===----------------------------------------------------------------------===//
1894 // VTX Read from global memory space
1895 //===----------------------------------------------------------------------===//
1898 def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1,
1899 [(set (i32 R600_TReg32_X:$dst), (zextloadi8_global ADDRVTX_READ:$ptr))]
1903 def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1,
1904 [(set (i32 R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))]
1908 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
1909 [(set (v4i32 R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))]
1912 //===----------------------------------------------------------------------===//
1914 // XXX: We are currently storing all constants in the global address space.
1915 //===----------------------------------------------------------------------===//
1917 def CONSTANT_LOAD_eg : VTX_READ_32_eg <1,
1918 [(set (i32 R600_TReg32_X:$dst), (constant_load ADDRVTX_READ:$ptr))]
1923 //===----------------------------------------------------------------------===//
1924 // Regist loads and stores - for indirect addressing
1925 //===----------------------------------------------------------------------===//
1927 defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;
1929 let Predicates = [isCayman] in {
1931 let isVector = 1 in {
1933 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
1935 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
1936 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
1937 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
1938 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
1939 def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
1940 def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
1941 def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;
1942 def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
1943 def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
1944 def SIN_cm : SIN_Common<0x8D>;
1945 def COS_cm : COS_Common<0x8E>;
1946 } // End isVector = 1
1948 def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL, R600_Reg32>;
1949 def : SIN_PAT <SIN_cm>;
1950 def : COS_PAT <COS_cm>;
1952 defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
1954 // RECIP_UINT emulation for Cayman
1955 // The multiplication scales from [0,1] to the unsigned integer range
1957 (AMDGPUurecip R600_Reg32:$src0),
1958 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)),
1959 (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1)))
1962 def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> {
1968 def : Pat<(fsqrt R600_Reg32:$src),
1969 (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm R600_Reg32:$src))>;
1973 //===----------------------------------------------------------------------===//
1974 // Branch Instructions
1975 //===----------------------------------------------------------------------===//
1978 def IF_PREDICATE_SET : ILFormat<(outs), (ins GPRI32:$src),
1979 "IF_PREDICATE_SET $src", []>;
1981 def PREDICATED_BREAK : ILFormat<(outs), (ins GPRI32:$src),
1982 "PREDICATED_BREAK $src", []>;
1984 //===----------------------------------------------------------------------===//
1985 // Pseudo instructions
1986 //===----------------------------------------------------------------------===//
1988 let isPseudo = 1 in {
1990 def PRED_X : InstR600 <
1991 (outs R600_Predicate_Bit:$dst),
1992 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
1994 let FlagOperandIdx = 3;
1997 let isTerminator = 1, isBranch = 1 in {
1998 def JUMP_COND : InstR600 <
2000 (ins brtarget:$target, R600_Predicate_Bit:$p),
2001 "JUMP $target ($p)",
2005 def JUMP : InstR600 <
2007 (ins brtarget:$target),
2012 let isPredicable = 1;
2016 } // End isTerminator = 1, isBranch = 1
2018 let usesCustomInserter = 1 in {
2020 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
2022 def MASK_WRITE : AMDGPUShaderInst <
2024 (ins R600_Reg32:$src),
2029 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
2033 (outs R600_Reg128:$dst),
2034 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
2035 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
2036 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$resourceId, imm:$samplerId, imm:$textureTarget))], NullALU> {
2040 def TXD_SHADOW: InstR600 <
2041 (outs R600_Reg128:$dst),
2042 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
2043 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
2044 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))], NullALU
2048 } // End isPseudo = 1
2049 } // End usesCustomInserter = 1
2051 def CLAMP_R600 : CLAMP <R600_Reg32>;
2052 def FABS_R600 : FABS<R600_Reg32>;
2053 def FNEG_R600 : FNEG<R600_Reg32>;
2055 //===---------------------------------------------------------------------===//
2056 // Return instruction
2057 //===---------------------------------------------------------------------===//
2058 let isTerminator = 1, isReturn = 1, hasCtrlDep = 1,
2059 usesCustomInserter = 1 in {
2060 def RETURN : ILFormat<(outs), (ins variable_ops),
2061 "RETURN", [(IL_retflag)]>;
2065 //===----------------------------------------------------------------------===//
2066 // Constant Buffer Addressing Support
2067 //===----------------------------------------------------------------------===//
2069 let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
2070 def CONST_COPY : Instruction {
2071 let OutOperandList = (outs R600_Reg32:$dst);
2072 let InOperandList = (ins i32imm:$src);
2074 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
2075 let AsmString = "CONST_COPY";
2076 let neverHasSideEffects = 1;
2077 let isAsCheapAsAMove = 1;
2078 let Itinerary = NullALU;
2080 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
2082 def TEX_VTX_CONSTBUF :
2083 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "VTX_READ_eg $dst, $ptr",
2084 [(set R600_Reg128:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$BUFFER_ID)))]>,
2085 VTX_WORD1_GPR, VTX_WORD0 {
2089 let FETCH_WHOLE_QUAD = 0;
2093 let USE_CONST_FIELDS = 0;
2094 let NUM_FORMAT_ALL = 2;
2095 let FORMAT_COMP_ALL = 1;
2096 let SRF_MODE_ALL = 1;
2097 let MEGA_FETCH_COUNT = 16;
2102 let DATA_FORMAT = 35;
2104 let Inst{31-0} = Word0;
2105 let Inst{63-32} = Word1;
2107 // LLVM can only encode 64-bit instructions, so these fields are manually
2108 // encoded in R600CodeEmitter
2111 // bits<2> ENDIAN_SWAP = 0;
2112 // bits<1> CONST_BUF_NO_STRIDE = 0;
2113 // bits<1> MEGA_FETCH = 0;
2114 // bits<1> ALT_CONST = 0;
2115 // bits<2> BUFFER_INDEX_MODE = 0;
2119 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
2120 // is done in R600CodeEmitter
2122 // Inst{79-64} = OFFSET;
2123 // Inst{81-80} = ENDIAN_SWAP;
2124 // Inst{82} = CONST_BUF_NO_STRIDE;
2125 // Inst{83} = MEGA_FETCH;
2126 // Inst{84} = ALT_CONST;
2127 // Inst{86-85} = BUFFER_INDEX_MODE;
2128 // Inst{95-86} = 0; Reserved
2130 // VTX_WORD3 (Padding)
2132 // Inst{127-96} = 0;
2137 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr",
2138 [(set R600_Reg128:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>,
2139 VTX_WORD1_GPR, VTX_WORD0 {
2143 let FETCH_WHOLE_QUAD = 0;
2147 let USE_CONST_FIELDS = 1;
2148 let NUM_FORMAT_ALL = 0;
2149 let FORMAT_COMP_ALL = 0;
2150 let SRF_MODE_ALL = 1;
2151 let MEGA_FETCH_COUNT = 16;
2156 let DATA_FORMAT = 0;
2158 let Inst{31-0} = Word0;
2159 let Inst{63-32} = Word1;
2161 // LLVM can only encode 64-bit instructions, so these fields are manually
2162 // encoded in R600CodeEmitter
2165 // bits<2> ENDIAN_SWAP = 0;
2166 // bits<1> CONST_BUF_NO_STRIDE = 0;
2167 // bits<1> MEGA_FETCH = 0;
2168 // bits<1> ALT_CONST = 0;
2169 // bits<2> BUFFER_INDEX_MODE = 0;
2173 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
2174 // is done in R600CodeEmitter
2176 // Inst{79-64} = OFFSET;
2177 // Inst{81-80} = ENDIAN_SWAP;
2178 // Inst{82} = CONST_BUF_NO_STRIDE;
2179 // Inst{83} = MEGA_FETCH;
2180 // Inst{84} = ALT_CONST;
2181 // Inst{86-85} = BUFFER_INDEX_MODE;
2182 // Inst{95-86} = 0; Reserved
2184 // VTX_WORD3 (Padding)
2186 // Inst{127-96} = 0;
2192 //===--------------------------------------------------------------------===//
2193 // Instructions support
2194 //===--------------------------------------------------------------------===//
2195 //===---------------------------------------------------------------------===//
2196 // Custom Inserter for Branches and returns, this eventually will be a
2198 //===---------------------------------------------------------------------===//
2199 let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
2200 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
2201 "; Pseudo unconditional branch instruction",
2203 defm BRANCH_COND : BranchConditional<IL_brcond>;
2206 //===---------------------------------------------------------------------===//
2207 // Flow and Program control Instructions
2208 //===---------------------------------------------------------------------===//
2209 let isTerminator=1 in {
2210 def SWITCH : ILFormat< (outs), (ins GPRI32:$src),
2211 !strconcat("SWITCH", " $src"), []>;
2212 def CASE : ILFormat< (outs), (ins GPRI32:$src),
2213 !strconcat("CASE", " $src"), []>;
2214 def BREAK : ILFormat< (outs), (ins),
2216 def CONTINUE : ILFormat< (outs), (ins),
2218 def DEFAULT : ILFormat< (outs), (ins),
2220 def ELSE : ILFormat< (outs), (ins),
2222 def ENDSWITCH : ILFormat< (outs), (ins),
2224 def ENDMAIN : ILFormat< (outs), (ins),
2226 def END : ILFormat< (outs), (ins),
2228 def ENDFUNC : ILFormat< (outs), (ins),
2230 def ENDIF : ILFormat< (outs), (ins),
2232 def WHILELOOP : ILFormat< (outs), (ins),
2234 def ENDLOOP : ILFormat< (outs), (ins),
2236 def FUNC : ILFormat< (outs), (ins),
2238 def RETDYN : ILFormat< (outs), (ins),
2240 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2241 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">;
2242 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2243 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">;
2244 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2245 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">;
2246 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2247 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">;
2248 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2249 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">;
2250 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2251 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">;
2252 defm IFC : BranchInstr2<"IFC">;
2253 defm BREAKC : BranchInstr2<"BREAKC">;
2254 defm CONTINUEC : BranchInstr2<"CONTINUEC">;
2257 //===----------------------------------------------------------------------===//
2259 //===----------------------------------------------------------------------===//
2261 // CND*_INT Pattterns for f32 True / False values
2263 class CND_INT_f32 <InstR600 cnd, CondCode cc> : Pat <
2264 (selectcc (i32 R600_Reg32:$src0), 0, (f32 R600_Reg32:$src1),
2265 R600_Reg32:$src2, cc),
2266 (cnd R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2)
2269 def : CND_INT_f32 <CNDE_INT, SETEQ>;
2270 def : CND_INT_f32 <CNDGT_INT, SETGT>;
2271 def : CND_INT_f32 <CNDGE_INT, SETGE>;
2273 //CNDGE_INT extra pattern
2275 (selectcc (i32 R600_Reg32:$src0), -1, (i32 R600_Reg32:$src1),
2276 (i32 R600_Reg32:$src2), COND_GT),
2277 (CNDGE_INT R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2)
2283 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
2287 (int_AMDGPU_kill R600_Reg32:$src0),
2288 (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
2293 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT),
2294 (SGT R600_Reg32:$src1, R600_Reg32:$src0)
2299 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE),
2300 (SGE R600_Reg32:$src1, R600_Reg32:$src0)
2303 // SETGT_DX10 reverse args
2305 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, COND_LT),
2306 (SETGT_DX10 R600_Reg32:$src1, R600_Reg32:$src0)
2309 // SETGE_DX10 reverse args
2311 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, COND_LE),
2312 (SETGE_DX10 R600_Reg32:$src1, R600_Reg32:$src0)
2315 // SETGT_INT reverse args
2317 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
2318 (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0)
2321 // SETGE_INT reverse args
2323 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE),
2324 (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0)
2327 // SETGT_UINT reverse args
2329 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
2330 (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0)
2333 // SETGE_UINT reverse args
2335 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE),
2336 (SETGE_UINT R600_Reg32:$src1, R600_Reg32:$src0)
2339 // The next two patterns are special cases for handling 'true if ordered' and
2340 // 'true if unordered' conditionals. The assumption here is that the behavior of
2341 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
2343 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
2344 // We assume that SETE returns false when one of the operands is NAN and
2345 // SNE returns true when on of the operands is NAN
2347 //SETE - 'true if ordered'
2349 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
2350 (SETE R600_Reg32:$src0, R600_Reg32:$src1)
2353 //SETE_DX10 - 'true if ordered'
2355 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETO),
2356 (SETE_DX10 R600_Reg32:$src0, R600_Reg32:$src1)
2359 //SNE - 'true if unordered'
2361 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO),
2362 (SNE R600_Reg32:$src0, R600_Reg32:$src1)
2365 //SETNE_DX10 - 'true if ordered'
2367 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUO),
2368 (SETNE_DX10 R600_Reg32:$src0, R600_Reg32:$src1)
2371 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sub0>;
2372 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sub1>;
2373 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sub2>;
2374 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sub3>;
2376 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 0, sub0>;
2377 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 1, sub1>;
2378 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 2, sub2>;
2379 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 3, sub3>;
2381 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sub0>;
2382 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sub1>;
2383 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sub2>;
2384 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sub3>;
2386 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 0, sub0>;
2387 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 1, sub1>;
2388 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 2, sub2>;
2389 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 3, sub3>;
2391 def : Vector4_Build <v4f32, R600_Reg128, f32, R600_Reg32>;
2392 def : Vector4_Build <v4i32, R600_Reg128, i32, R600_Reg32>;
2394 // bitconvert patterns
2396 def : BitConvert <i32, f32, R600_Reg32>;
2397 def : BitConvert <f32, i32, R600_Reg32>;
2398 def : BitConvert <v4f32, v4i32, R600_Reg128>;
2399 def : BitConvert <v4i32, v4f32, R600_Reg128>;
2401 // DWORDADDR pattern
2402 def : DwordAddrPat <i32, R600_Reg32>;
2404 } // End isR600toCayman Predicate